diff --git a/board/spike/riscv64/readme.txt b/board/spike/riscv64/readme.txt
index 5ad7df46df..34db625aad 100644
--- a/board/spike/riscv64/readme.txt
+++ b/board/spike/riscv64/readme.txt
@@ -20,11 +20,6 @@ The boot is made with the standard RISC-V OpenSBI boot loader. In
 order to keep the simulation simple, the rootfs is passed as an initrd
 ramfs.
 
-Note: at the time of this writing, Spike v1.1.0 and OpenSBI v1.0 does
-not support console input emulation for 32bit RISC-V systems. A 32bit
-Linux system can boot and reach the login, but it's not possible to
-login. See [4].
-
 
 [1].
 https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
@@ -34,6 +29,3 @@ https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-g
 
 [3].
 https://github.com/riscv/riscv-openocd
-
-[4].
-https://github.com/riscv-software-src/opensbi/blob/v1.0/lib/utils/sys/htif.c#L127