diff --git a/arch/Config.in b/arch/Config.in index 6b54c65df9..de15944eb2 100644 --- a/arch/Config.in +++ b/arch/Config.in @@ -23,6 +23,7 @@ choice config BR2_arcle bool "ARC (little endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help Synopsys' DesignWare ARC Processor Cores are a family of @@ -49,6 +50,7 @@ config BR2_arm config BR2_armeb bool "ARM (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help ARM is a 32-bit reduced instruction set computer (RISC) @@ -67,6 +69,7 @@ config BR2_aarch64 config BR2_aarch64_be bool "AArch64 (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARCH_IS_64 help Aarch64 is a 64-bit architecture developed by ARM Holdings. @@ -82,6 +85,7 @@ config BR2_i386 config BR2_m68k bool "m68k" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS # MMU support is set by the subarchitecture file, arch/Config.in.m68k help Motorola 68000 family microprocessor @@ -89,6 +93,7 @@ config BR2_m68k config BR2_microblazeel bool "Microblaze AXI (little endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help Soft processor core designed for Xilinx FPGAs from Xilinx. AXI @@ -98,6 +103,7 @@ config BR2_microblazeel config BR2_microblazebe bool "Microblaze non-AXI (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help Soft processor core designed for Xilinx FPGAs from Xilinx. PLB @@ -107,6 +113,7 @@ config BR2_microblazebe config BR2_mips bool "MIPS (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help MIPS is a RISC microprocessor from MIPS Technologies. Big @@ -116,6 +123,7 @@ config BR2_mips config BR2_mipsel bool "MIPS (little endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help MIPS is a RISC microprocessor from MIPS Technologies. Little @@ -125,6 +133,7 @@ config BR2_mipsel config BR2_mips64 bool "MIPS64 (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARCH_IS_64 select BR2_USE_MMU help @@ -145,6 +154,7 @@ config BR2_mips64el config BR2_or1k bool "OpenRISC" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help OpenRISC is a free and open processor for embedded system. @@ -152,6 +162,7 @@ config BR2_or1k config BR2_powerpc bool "PowerPC" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help PowerPC is a RISC architecture created by Apple-IBM-Motorola @@ -161,6 +172,7 @@ config BR2_powerpc config BR2_powerpc64 bool "PowerPC64 (big endian)" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARCH_IS_64 select BR2_USE_MMU help @@ -191,6 +203,7 @@ config BR2_riscv config BR2_s390x bool "s390x" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARCH_IS_64 select BR2_USE_MMU help @@ -200,6 +213,7 @@ config BR2_s390x config BR2_sh bool "SuperH" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help SuperH (or SH) is a 32-bit reduced instruction set computer @@ -210,6 +224,7 @@ config BR2_sh config BR2_sparc bool "SPARC" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_USE_MMU help SPARC (from Scalable Processor Architecture) is a RISC @@ -220,6 +235,7 @@ config BR2_sparc config BR2_sparc64 bool "SPARC64" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARCH_IS_64 select BR2_USE_MMU help @@ -240,6 +256,7 @@ config BR2_x86_64 config BR2_xtensa bool "Xtensa" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS # MMU support is set by the subarchitecture file, arch/Config.in.xtensa help Xtensa is a Tensilica processor IP architecture. diff --git a/arch/Config.in.arm b/arch/Config.in.arm index f01dcc4d5a..6996f3d7ca 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -112,22 +112,27 @@ choice if !BR2_ARCH_IS_64 comment "armv4 cores" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS config BR2_arm920t bool "arm920t" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARM_CPU_HAS_ARM select BR2_ARM_CPU_HAS_THUMB select BR2_ARM_CPU_ARMV4 config BR2_arm922t bool "arm922t" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARM_CPU_HAS_ARM select BR2_ARM_CPU_HAS_THUMB select BR2_ARM_CPU_ARMV4 config BR2_fa526 bool "fa526/626" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARM_CPU_HAS_ARM select BR2_ARM_CPU_ARMV4 config BR2_strongarm bool "strongarm sa110/sa1100" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS select BR2_ARM_CPU_HAS_ARM select BR2_ARM_CPU_ARMV4 diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 23d095d1a6..f7ffd5fdc3 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -51,10 +51,12 @@ choice config BR2_RISCV_32 bool "32-bit" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS config BR2_RISCV_64 bool "64-bit" select BR2_ARCH_IS_64 + select BR2_RISCV_USE_MMU if BR2_HIDE_SECONDARY_TARGET_OPTIONS endchoice diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 index f9b32130b2..34ab056b5f 100644 --- a/arch/Config.in.x86 +++ b/arch/Config.in.x86 @@ -42,6 +42,7 @@ choice config BR2_x86_i486 bool "i486" + depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS depends on !BR2_x86_64 config BR2_x86_i586 bool "i586"