From 0175606ad4ef2348997c1657ae3dfae56a5be3b8 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Fri, 15 Apr 2022 15:04:56 -0400 Subject: [PATCH] GP-1790: Spec'd out new aarch64 and arm32 instructions up to v9 --- .../AARCH64/data/languages/AARCH64.ldefs | 4 +- .../AARCH64/data/languages/AARCH64base.sinc | 812 +- .../data/languages/AARCH64instructions.sinc | 3 + .../Processors/ARM/data/languages/ARM.ldefs | 38 +- .../ARM/data/languages/ARMinstructions.sinc | 24 +- .../ARM/data/languages/ARMneon.sinc | 2389 ++++-- .../Processors/ARM/data/languages/ARMv8.sinc | 330 +- Ghidra/Processors/ARM/data/manuals/ARM.idx | 6863 +---------------- 8 files changed, 2646 insertions(+), 7817 deletions(-) diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs b/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs index 75d49d24cf..421644f47e 100644 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs @@ -4,7 +4,7 @@ endian="little" size="64" variant="v8A" - version="1.5" + version="1.6" slafile="AARCH64.sla" processorspec="AARCH64.pspec" manualindexfile="../manuals/AARCH64.idx" @@ -20,7 +20,7 @@ instructionEndian="little" size="64" variant="v8A" - version="1.5" + version="1.6" slafile="AARCH64BE.sla" processorspec="AARCH64.pspec" manualindexfile="../manuals/AARCH64.idx" diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc index 9d5b5cf469..9a89c42e9a 100644 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc @@ -716,6 +716,23 @@ is b_31=0 & b_2630=0x05 & Addr26 goto Addr26; } +# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010 +# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES +# b_0031=01010100...................1.... + +:bc^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=1 & br_cond_op=15 & BranchCondOp +{ + goto Addr19; +} + +:bc^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=1 & BranchCondOp +{ + if (BranchCondOp) goto Addr19; +} + + # C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000 # C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0 # C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000 @@ -1843,6 +1860,51 @@ is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 Rd_GPR64 = tmp; } +# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00 +# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00 +# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00 +# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00 +# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES + +cpyPhase:"p" is opt=0 {export 0:1;} +cpyPhase:"m" is opt=1 {export 1:1;} +cpyPhase:"e" is opt=2 {export 2:1;} + +cpyType: "" is b_1015=0x01 {export 0x01:1; } +cpyType: "n" is b_1015=0x31 {export 0x31:1; } +cpyType: "rn" is b_1015=0x21 {export 0x21:1; } +cpyType: "wn" is b_1015=0x11 {export 0x11:1; } + +cpyType: "rt" is b_1015=0x09 {export 0x09:1; } +cpyType: "rtn" is b_1015=0x39 {export 0x39:1; } +cpyType: "rtrn" is b_1015=0x29 {export 0x29:1; } +cpyType: "rtwn" is b_1015=0x19 {export 0x19:1; } + +cpyType: "t" is b_1015=0x0d {export 0x0d:1; } +cpyType: "tn" is b_1015=0x3d {export 0x3d:1; } +cpyType: "trn" is b_1015=0x2d {export 0x2d:1; } +cpyType: "twn" is b_1015=0x1d {export 0x1d:1; } + +cpyType: "wt" is b_1015=0x03 {export 0x03:1; } +cpyType: "wtn" is b_1015=0x33 {export 0x33:1; } +cpyType: "wtrn" is b_1015=0x23 {export 0x23:1; } +cpyType: "wtwn" is b_1015=0x13 {export 0x13:1; } + + +define pcodeop MemoryCopyForward; +# Memory Copy Forward-only +:cpyf^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!" +is size.ldstr & b_2429=0x19 & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64 +{ + MemoryCopyForward(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase); +} +define pcodeop MemoryCopy; +:cpy^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!" +is size.ldstr & b_2429=0x1d & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64 +{ + MemoryCopy(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase); +} + # C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH # sf == 0 && sz = 00 CRC32CB variant @@ -2257,7 +2319,20 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CR # AUNIT --inst xd503309f/mask=xfffff0ff --status nodest :dsb CRm_dbarrier_op -is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=4 & Rt=0x1f +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10=2 & Op2=4 & Rt=0x1f +{ + types:1 = 0x3; #MBReqTypes_All + domain:1 = CRm_32; + DataSynchronizationBarrier(domain, types); +} + +# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff +# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES +# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=11010101000000110011..1000111111 + +:dsb CRm_32 +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=1 & Rt=0x1f { types:1 = CRm_10; domain:1 = CRm_32; @@ -5238,6 +5313,7 @@ is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x3 & Rn_G Rd_GPR64 = tmp_1; } + # C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f # CONSTRUCT x3a00080d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES @@ -5261,6 +5337,38 @@ is b_1531=0b00111010000000000 & b_14=1 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn OV = (((aa_Wn >> 15) & 1) ^ ((aa_Wn >>16) & 1)) == 1; } + + + +# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 +# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 +# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES + +setPhase:"p" is b_1415=0 {export 0:1;} +setPhase:"m" is b_1415=1 {export 1:1;} +setPhase:"e" is b_1415=2 {export 2:1;} + +setType: "" is b_1013=0x1 {export 1:1; } +setType: "n" is b_1013=0x9 {export 9:1; } +setType: "t" is b_1013=0x5 {export 5:1; } +setType: "tn" is b_1013=0xd {export 13:1; } + +define pcodeop memorySetTag; +:setg^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64 +is size.ldstr & b_2129=0xee & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 { + memorySetTag(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType); +} + + +# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 +# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES +define pcodeop memorySet; +:setp^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64 +is size.ldstr & b_2129=0xce & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 { + memorySet(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType); +} + + # C6.2.280 SEV page C6-1796 line 106224 MATCH xd503209f/mask=xffffffff # C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f # CONSTRUCT xd503209f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES @@ -5337,6 +5445,38 @@ is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Rd_GPR64 = tmp_1; } + +# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES +# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001101000..101111111 + +SVAmodeOp: "SM" is b_0911=0x1 {} +SVAmodeOp: "ZA" is b_0911=0x2 {} +SVAmodeOp: "" is b_0911=0x3 {} + +define pcodeop sveStreamingModeStart; +define pcodeop sveStreamingModeStop; +:smstart "{"^SVAmodeOp^"}" +is b_1131=0x1aa068 & SVAmodeOp & b_08=1 & b_0507=0x3 & op4=0xf { + sveStreamingModeStart(SVAmodeOp); +} + + +# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES +# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001101000..001111111 + +:smstop "{"^SVAmodeOp^"}" +is b_1131=0x1aa068 & SVAmodeOp & b_08=0 & b_0507=0x3 & op4=0xf { + sveStreamingModeStop(SVAmodeOp); +} + + + # C6.2.288 SMULH page C6-1808 line 106800 MATCH x9b400000/mask=xffe08000 # CONSTRUCT x9b400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES # AUNIT --inst x9b400000/mask=xffe08000 --status pass @@ -7165,6 +7305,17 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=2 & Rt=0x1f WaitForEvent(); } +# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0 +# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001100010000000..... + +:wfet Rd_GPR64 +is b_0531=0x6a81880 & Rd_GPR64 +{ + WaitForEvent(Rd_GPR64); +} + # C6.2.398 WFI page C6-2006 line 117439 MATCH xd503207f/mask=xffffffff # C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f # CONSTRUCT xd503207f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES @@ -7176,6 +7327,17 @@ is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=3 & Rt=0x1f WaitForInterrupt(); } +# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0 +# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001100010000001..... + +:wfit Rd_GPR64 +is b_0531=0x6a81881 & Rd_GPR64 +{ + WaitForInterrupt(Rd_GPR64); +} + # C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0 # CONSTRUCT xdac147e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES # AUNIT --inst xdac147e0/mask=xffffffe0 --status noqemu @@ -7652,6 +7814,48 @@ is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp } +# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00 +# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=1111100000111111110100.......... + +# Single-copy Atomic 64-byte Load +:ld64b Rn_GPR64, [Rt_GPR64xsp] +is b_1031=0x3e0ff4 & Rn_GPR64 & Rt_GPR64xsp { + Rn_GPR64 = *Rt_GPR64xsp; +} + + +# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00 +# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:st64b Rn_GPR64, [Rt_GPR64xsp] +is b_1031=0x3e0fe4 & Rn_GPR64 & Rt_GPR64xsp { + *Rt_GPR64xsp = Rn_GPR64; +} + + +# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00 +# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +define pcodeop store64ByteAtomic; +:st64bv Rs_GPR64, Rn_GPR64, [Rt_GPR64xsp] +is b_2131=0x7c1 & Rs_GPR64 & b_1015=0x2c & Rn_GPR64 & Rt_GPR64xsp { + *Rt_GPR64xsp = Rn_GPR64; + Rs_GPR64 = store64ByteAtomic(Rn_GPR64, Rt_GPR64xsp); +} + + +# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00 +# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:st64bv0 +is b_2131=0b11111000001 & Rs_GPR64 & b_1015=0x28 & Rn_GPR64 & Rt_GPR64xsp { + local st64bv_addr:8 = (Rt_GPR64xsp & 0xffff0000) | (accdata & 0xffff); + *st64bv_addr = Rn_GPR64; + Rs_GPR64 = store64ByteAtomic(Rn_GPR64, st64bv_addr); +} + + addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn=0b11111 & addrGranuleIndexed { export addrGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn & addrGranuleIndexed { tmp:8 = addrGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case @@ -8103,6 +8307,48 @@ is sf=1 & b_30=0 & S & SBIT_CZNO & b_2128=0b11010110 & b_1015=0b000000 & Rd_GPR6 } +# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f +# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES + +define pcodeop cancelTransaction; +:tcancel "#"^imm16 +is b_2131=0x6a3 & imm16 & b_0519 & b_2020 & b_0004=0x0 { + local tmp:2 = imm16; + local reason:2 = b_0519; + local retry:1 = b_2020; + cancelTransaction(reason, retry); +} + + +# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff +# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES + +define pcodeop commitTransaction; +:tcommit +is b_0031=0xd503307f { + commitTransaction(); +} + + +# C6.2.379 TSTART page C6-1979 line 116075 + +define pcodeop transactionStart; +:tstart Rd_GPR64 +is b_0531=0x6a9193a & Rd_GPR64 { + transactionStart(Rd_GPR64); +} + + +# C6.2.380 TTEST page C6-1981 line 116175 + +define pcodeop transactionDepth; +:ttest Rd_GPR64 +is b_0531=0x6a9198b & Rd_GPR64 { + Rd_GPR64 = transactionDepth(); +} + + + # C6.2.387 UDF page C6-1993 line 116744 MATCH x00000000/mask=xffff0000 # CONSTRUCT x00000000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES # Undefined instruction @@ -8135,567 +8381,3 @@ is b_1231=0b11010101000000000100 & b_0007=0b00111111 } - - - - -################################ Need implementation - - - - - - -# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010 -# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES -# x54000010/mask=xff000010 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=01010100...................1.... - -:bc -is b_2431=0b01010100 & imm19 & b_0404=0b1 & cond -unimpl - -# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00 -# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 -# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19000400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....000001.......... - -:cpyfp -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b000001 & Rn & Rd -unimpl - -# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00 -# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 -# CONSTRUCT x1900c400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900c400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....110001.......... - -:cpyfpn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b110001 & Rn & Rd -unimpl - -# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00 -# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 -# CONSTRUCT x19008400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19008400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....100001.......... - -:cpyfprn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b100001 & Rn & Rd -unimpl - -# C6.2.71 CPYFPRT, CPYFMRT, CPYFERT page C6-1277 line 74912 MATCH x19002400/mask=x3f20fc00 -# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00 -# CONSTRUCT x19002400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19002400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....001001.......... - -:cpyfprt -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b001001 & Rn & Rd -unimpl - -# C6.2.72 CPYFPRTN, CPYFMRTN, CPYFERTN page C6-1282 line 75245 MATCH x1900e400/mask=x3f20fc00 -# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00 -# CONSTRUCT x1900e400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900e400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....111001.......... - -:cpyfprtn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b111001 & Rn & Rd -unimpl - -# C6.2.73 CPYFPRTRN, CPYFMRTRN, CPYFERTRN page C6-1287 line 75578 MATCH x1900a400/mask=x3f20fc00 -# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00 -# CONSTRUCT x1900a400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900a400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....101001.......... - -:cpyfprtrn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b101001 & Rn & Rd -unimpl - -# C6.2.74 CPYFPRTWN, CPYFMRTWN, CPYFERTWN page C6-1292 line 75911 MATCH x19006400/mask=x3f20fc00 -# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00 -# CONSTRUCT x19006400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19006400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....011001.......... - -:cpyfprtwn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b011001 & Rn & Rd -unimpl - -# C6.2.75 CPYFPT, CPYFMT, CPYFET page C6-1297 line 76244 MATCH x19003400/mask=x3f20fc00 -# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00 -# CONSTRUCT x19003400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19003400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....001101.......... - -:cpyfpt -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b001101 & Rn & Rd -unimpl - -# C6.2.76 CPYFPTN, CPYFMTN, CPYFETN page C6-1302 line 76577 MATCH x1900f400/mask=x3f20fc00 -# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00 -# CONSTRUCT x1900f400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900f400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....111101.......... - -:cpyfptn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b111101 & Rn & Rd -unimpl - -# C6.2.77 CPYFPTRN, CPYFMTRN, CPYFETRN page C6-1307 line 76910 MATCH x1900b400/mask=x3f20fc00 -# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00 -# CONSTRUCT x1900b400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900b400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....101101.......... - -:cpyfptrn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b101101 & Rn & Rd -unimpl - -# C6.2.78 CPYFPTWN, CPYFMTWN, CPYFETWN page C6-1312 line 77243 MATCH x19007400/mask=x3f20fc00 -# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00 -# CONSTRUCT x19007400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19007400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....011101.......... - -:cpyfptwn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b011101 & Rn & Rd -unimpl - -# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00 -# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 -# CONSTRUCT x19004400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19004400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....010001.......... - -:cpyfpwn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b010001 & Rn & Rd -unimpl - -# C6.2.80 CPYFPWT, CPYFMWT, CPYFEWT page C6-1322 line 77909 MATCH x19001400/mask=x3f20fc00 -# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00 -# CONSTRUCT x19001400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19001400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....000101.......... - -:cpyfpwt -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b000101 & Rn & Rd -unimpl - -# C6.2.81 CPYFPWTN, CPYFMWTN, CPYFEWTN page C6-1327 line 78242 MATCH x1900d400/mask=x3f20fc00 -# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00 -# CONSTRUCT x1900d400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1900d400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....110101.......... - -:cpyfpwtn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b110101 & Rn & Rd -unimpl - -# C6.2.82 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN page C6-1332 line 78575 MATCH x19009400/mask=x3f20fc00 -# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00 -# CONSTRUCT x19009400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19009400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....100101.......... - -:cpyfpwtrn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b100101 & Rn & Rd -unimpl - -# C6.2.83 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN page C6-1337 line 78908 MATCH x19005400/mask=x3f20fc00 -# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00 -# CONSTRUCT x19005400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x19005400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001..0.....010101.......... - -:cpyfpwtwn -is size & b_2429=0b011001 & opt & b_2121=0b0 & Rs & b_1015=0b010101 & Rn & Rd -unimpl - -# C6.2.84 CPYP, CPYM, CPYE page C6-1342 line 79241 MATCH x1d000400/mask=x3f20fc00 -# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 -# CONSTRUCT x1d000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d000400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....000001.......... - -:cpyp -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b000001 & Rn & Rd -unimpl - -# C6.2.85 CPYPN, CPYMN, CPYEN page C6-1348 line 79655 MATCH x1d00c400/mask=x3f20fc00 -# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 -# CONSTRUCT x1d00c400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00c400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....110001.......... - -:cpypn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b110001 & Rn & Rd -unimpl - -# C6.2.86 CPYPRN, CPYMRN, CPYERN page C6-1354 line 80068 MATCH x1d008400/mask=x3f20fc00 -# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 -# CONSTRUCT x1d008400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d008400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....100001.......... - -:cpyprn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b100001 & Rn & Rd -unimpl - -# C6.2.87 CPYPRT, CPYMRT, CPYERT page C6-1360 line 80481 MATCH x1d002400/mask=x3f20fc00 -# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00 -# CONSTRUCT x1d002400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d002400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....001001.......... - -:cpyprt -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b001001 & Rn & Rd -unimpl - -# C6.2.88 CPYPRTN, CPYMRTN, CPYERTN page C6-1366 line 80894 MATCH x1d00e400/mask=x3f20fc00 -# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00 -# CONSTRUCT x1d00e400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00e400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....111001.......... - -:cpyprtn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b111001 & Rn & Rd -unimpl - -# C6.2.89 CPYPRTRN, CPYMRTRN, CPYERTRN page C6-1372 line 81307 MATCH x1d00a400/mask=x3f20fc00 -# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00 -# CONSTRUCT x1d00a400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00a400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....101001.......... - -:cpyprtrn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b101001 & Rn & Rd -unimpl - -# C6.2.90 CPYPRTWN, CPYMRTWN, CPYERTWN page C6-1378 line 81720 MATCH x1d006400/mask=x3f20fc00 -# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00 -# CONSTRUCT x1d006400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d006400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....011001.......... - -:cpyprtwn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b011001 & Rn & Rd -unimpl - -# C6.2.91 CPYPT, CPYMT, CPYET page C6-1384 line 82133 MATCH x1d003400/mask=x3f20fc00 -# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00 -# CONSTRUCT x1d003400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d003400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....001101.......... - -:cpypt -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b001101 & Rn & Rd -unimpl - -# C6.2.92 CPYPTN, CPYMTN, CPYETN page C6-1390 line 82546 MATCH x1d00f400/mask=x3f20fc00 -# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00 -# CONSTRUCT x1d00f400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00f400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....111101.......... - -:cpyptn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b111101 & Rn & Rd -unimpl - -# C6.2.93 CPYPTRN, CPYMTRN, CPYETRN page C6-1396 line 82959 MATCH x1d00b400/mask=x3f20fc00 -# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00 -# CONSTRUCT x1d00b400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00b400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....101101.......... - -:cpyptrn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b101101 & Rn & Rd -unimpl - -# C6.2.94 CPYPTWN, CPYMTWN, CPYETWN page C6-1402 line 83372 MATCH x1d007400/mask=x3f20fc00 -# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00 -# CONSTRUCT x1d007400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d007400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....011101.......... - -:cpyptwn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b011101 & Rn & Rd -unimpl - -# C6.2.95 CPYPWN, CPYMWN, CPYEWN page C6-1408 line 83785 MATCH x1d004400/mask=x3f20fc00 -# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 -# CONSTRUCT x1d004400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d004400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....010001.......... - -:cpypwn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b010001 & Rn & Rd -unimpl - -# C6.2.96 CPYPWT, CPYMWT, CPYEWT page C6-1414 line 84198 MATCH x1d001400/mask=x3f20fc00 -# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00 -# CONSTRUCT x1d001400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d001400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....000101.......... - -:cpypwt -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b000101 & Rn & Rd -unimpl - -# C6.2.97 CPYPWTN, CPYMWTN, CPYEWTN page C6-1420 line 84611 MATCH x1d00d400/mask=x3f20fc00 -# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00 -# CONSTRUCT x1d00d400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d00d400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....110101.......... - -:cpypwtn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b110101 & Rn & Rd -unimpl - -# C6.2.98 CPYPWTRN, CPYMWTRN, CPYEWTRN page C6-1426 line 85024 MATCH x1d009400/mask=x3f20fc00 -# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00 -# CONSTRUCT x1d009400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d009400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....100101.......... - -:cpypwtrn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b100101 & Rn & Rd -unimpl - -# C6.2.99 CPYPWTWN, CPYMWTWN, CPYEWTWN page C6-1432 line 85437 MATCH x1d005400/mask=x3f20fc00 -# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00 -# CONSTRUCT x1d005400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES -# x1d005400/mask=x3f20fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101..0.....010101.......... - -:cpypwtwn -is size & b_2429=0b011101 & opt & b_2121=0b0 & Rs & b_1015=0b010101 & Rn & Rd -unimpl - -# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff -# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES -# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=11010101000000110011..1000111111 - -:dsb -is b_1231=0b11010101000000110011 & imm2 & b_0009=0b1000111111 -unimpl - -# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00 -# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES -# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=1111100000111111110100.......... - -:ld64b -is b_1031=0b1111100000111111110100 & Rn & Rt -unimpl - -# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 -# C6.2.84 CPYP, CPYM, CPYE page C6-1342 line 79241 MATCH x1d000400/mask=x3f20fc00 -# C6.2.85 CPYPN, CPYMN, CPYEN page C6-1348 line 79655 MATCH x1d00c400/mask=x3f20fc00 -# C6.2.86 CPYPRN, CPYMRN, CPYERN page C6-1354 line 80068 MATCH x1d008400/mask=x3f20fc00 -# C6.2.95 CPYPWN, CPYMWN, CPYEWN page C6-1408 line 83785 MATCH x1d004400/mask=x3f20fc00 -# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x1dc00400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101110.......0001.......... - -:setgp -is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b0001 & Rn & Rd -unimpl - -# C6.2.273 SETGPN, SETGMN, SETGEN page C6-1765 line 104007 MATCH x1dc02400/mask=x3fe03c00 -# C6.2.87 CPYPRT, CPYMRT, CPYERT page C6-1360 line 80481 MATCH x1d002400/mask=x3f20fc00 -# C6.2.88 CPYPRTN, CPYMRTN, CPYERTN page C6-1366 line 80894 MATCH x1d00e400/mask=x3f20fc00 -# C6.2.89 CPYPRTRN, CPYMRTRN, CPYERTRN page C6-1372 line 81307 MATCH x1d00a400/mask=x3f20fc00 -# C6.2.90 CPYPRTWN, CPYMRTWN, CPYERTWN page C6-1378 line 81720 MATCH x1d006400/mask=x3f20fc00 -# CONSTRUCT x1dc02400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x1dc02400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101110.......1001.......... - -:setgpn -is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b1001 & Rn & Rd -unimpl - -# C6.2.274 SETGPT, SETGMT, SETGET page C6-1770 line 104362 MATCH x1dc01400/mask=x3fe03c00 -# C6.2.96 CPYPWT, CPYMWT, CPYEWT page C6-1414 line 84198 MATCH x1d001400/mask=x3f20fc00 -# C6.2.97 CPYPWTN, CPYMWTN, CPYEWTN page C6-1420 line 84611 MATCH x1d00d400/mask=x3f20fc00 -# C6.2.98 CPYPWTRN, CPYMWTRN, CPYEWTRN page C6-1426 line 85024 MATCH x1d009400/mask=x3f20fc00 -# C6.2.99 CPYPWTWN, CPYMWTWN, CPYEWTWN page C6-1432 line 85437 MATCH x1d005400/mask=x3f20fc00 -# CONSTRUCT x1dc01400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x1dc01400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101110.......0101.......... - -:setgpt -is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b0101 & Rn & Rd -unimpl - -# C6.2.275 SETGPTN, SETGMTN, SETGETN page C6-1775 line 104717 MATCH x1dc03400/mask=x3fe03c00 -# C6.2.91 CPYPT, CPYMT, CPYET page C6-1384 line 82133 MATCH x1d003400/mask=x3f20fc00 -# C6.2.92 CPYPTN, CPYMTN, CPYETN page C6-1390 line 82546 MATCH x1d00f400/mask=x3f20fc00 -# C6.2.93 CPYPTRN, CPYMTRN, CPYETRN page C6-1396 line 82959 MATCH x1d00b400/mask=x3f20fc00 -# C6.2.94 CPYPTWN, CPYMTWN, CPYETWN page C6-1402 line 83372 MATCH x1d007400/mask=x3f20fc00 -# CONSTRUCT x1dc03400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x1dc03400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011101110.......1101.......... - -:setgptn -is size & b_2129=0b011101110 & Rs & x & x & b_1013=0b1101 & Rn & Rd -unimpl - -# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 -# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00 -# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00 -# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00 -# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00 -# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x19c00400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001110.......0001.......... - -:setp -is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b0001 & Rn & Rd -unimpl - -# C6.2.277 SETPN, SETMN, SETEN page C6-1784 line 105360 MATCH x19c02400/mask=x3fe03c00 -# C6.2.71 CPYFPRT, CPYFMRT, CPYFERT page C6-1277 line 74912 MATCH x19002400/mask=x3f20fc00 -# C6.2.72 CPYFPRTN, CPYFMRTN, CPYFERTN page C6-1282 line 75245 MATCH x1900e400/mask=x3f20fc00 -# C6.2.73 CPYFPRTRN, CPYFMRTRN, CPYFERTRN page C6-1287 line 75578 MATCH x1900a400/mask=x3f20fc00 -# C6.2.74 CPYFPRTWN, CPYFMRTWN, CPYFERTWN page C6-1292 line 75911 MATCH x19006400/mask=x3f20fc00 -# CONSTRUCT x19c02400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x19c02400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001110.......1001.......... - -:setpn -is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b1001 & Rn & Rd -unimpl - -# C6.2.278 SETPT, SETMT, SETET page C6-1788 line 105648 MATCH x19c01400/mask=x3fe03c00 -# C6.2.80 CPYFPWT, CPYFMWT, CPYFEWT page C6-1322 line 77909 MATCH x19001400/mask=x3f20fc00 -# C6.2.81 CPYFPWTN, CPYFMWTN, CPYFEWTN page C6-1327 line 78242 MATCH x1900d400/mask=x3f20fc00 -# C6.2.82 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN page C6-1332 line 78575 MATCH x19009400/mask=x3f20fc00 -# C6.2.83 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN page C6-1337 line 78908 MATCH x19005400/mask=x3f20fc00 -# CONSTRUCT x19c01400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x19c01400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001110.......0101.......... - -:setpt -is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b0101 & Rn & Rd -unimpl - -# C6.2.279 SETPTN, SETMTN, SETETN page C6-1792 line 105936 MATCH x19c03400/mask=x3fe03c00 -# C6.2.75 CPYFPT, CPYFMT, CPYFET page C6-1297 line 76244 MATCH x19003400/mask=x3f20fc00 -# C6.2.76 CPYFPTN, CPYFMTN, CPYFETN page C6-1302 line 76577 MATCH x1900f400/mask=x3f20fc00 -# C6.2.77 CPYFPTRN, CPYFMTRN, CPYFETRN page C6-1307 line 76910 MATCH x1900b400/mask=x3f20fc00 -# C6.2.78 CPYFPTWN, CPYFMTWN, CPYFETWN page C6-1312 line 77243 MATCH x19007400/mask=x3f20fc00 -# CONSTRUCT x19c03400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES -# x19c03400/mask=x3fe03c00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=..011001110.......1101.......... - -:setptn -is size & b_2129=0b011001110 & Rs & x & x & b_1013=0b1101 & Rn & Rd -unimpl - -# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff -# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f -# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES -# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010000001101000..101111111 - -:smstart -is b_1131=0b110101010000001101000 & x & x & b_0008=0b101111111 -unimpl - -# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff -# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f -# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES -# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010000001101000..001111111 - -:smstop -is b_1131=0b110101010000001101000 & x & x & b_0008=0b001111111 -unimpl - -# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00 -# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES -# xf83f9000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=1111100000111111100100.......... - -:st64b -is b_1031=0b1111100000111111100100 & Rn & Rt -unimpl - -# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00 -# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES -# xf820b000/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=11111000001.....101100.......... - -:st64bv -is b_2131=0b11111000001 & Rs & b_1015=0b101100 & Rn & Rt -unimpl - -# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00 -# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES -# xf820a000/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=11111000001.....101000.......... - -:st64bv0 -is b_2131=0b11111000001 & Rs & b_1015=0b101000 & Rn & Rt -unimpl - -# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f -# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES -# xd4600000/mask=xffe0001f NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=11010100011................00000 - -:tcancel -is b_2131=0b11010100011 & imm16 & b_0004=0b00000 -unimpl - -# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff -# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES -# xd503307f/mask=xffffffff NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=11010101000000110011000001111111 - -:tcommit -is b_0031=0b11010101000000110011000001111111 -unimpl - -# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0 -# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES -# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010000001100010000000..... - -:wfet -is b_0531=0b110101010000001100010000000 & Rd -unimpl - -# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0 -# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES -# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010000001100010000001..... - -:wfit -is b_0531=0b110101010000001100010000001 & Rd -unimpl - -# C6.2.228 MRS page C6-1683 line 99588 -# xd5300000/mask=xfff00000 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010011.................... - -# C6.2.379 TSTART page C6-1979 line 116075 -# xd5233060/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010010001100110000011..... - -:tstart -is b_0531=0b110101010010001100110000011 & Rt -unimpl - -# C6.2.380 TTEST page C6-1981 line 116175 -# xd5233160/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR -# b_0031=110101010010001100110001011..... - -:ttest -is b_0531=0b110101010010001100110001011 & Rt -unimpl diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc index fa11662cdb..2f62006d83 100644 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc @@ -103,6 +103,7 @@ define register offset=0x1000 size=8 uao pan tco + accdata ]; # System Registers @@ -1201,6 +1202,8 @@ define token instrAARCH64 (32) endian = little b_0509 = (5,9) b_0510 = (5,10) b_0515 = (5,15) + b_0519 = (5,19) + b_0531 = (5,31) b_0607 = (6,7) b_0609 = (6,9) b_0610 = (6,10) diff --git a/Ghidra/Processors/ARM/data/languages/ARM.ldefs b/Ghidra/Processors/ARM/data/languages/ARM.ldefs index ee1a245b79..d327f8806c 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM.ldefs +++ b/Ghidra/Processors/ARM/data/languages/ARM.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="v8" - version="1.103" + version="1.104" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -29,7 +29,7 @@ endian="little" size="32" variant="v8T" - version="1.103" + version="1.104" slafile="ARM8_le.sla" processorspec="ARMtTHUMB.pspec" manualindexfile="../manuals/ARM.idx" @@ -49,7 +49,7 @@ instructionEndian="little" size="32" variant="v8LEInstruction" - version="1.103" + version="1.104" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -64,7 +64,7 @@ endian="big" size="32" variant="v8" - version="1.103" + version="1.104" slafile="ARM8_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -87,7 +87,7 @@ endian="big" size="32" variant="v8T" - version="1.103" + version="1.104" slafile="ARM8_be.sla" processorspec="ARMtTHUMB.pspec" manualindexfile="../manuals/ARM.idx" @@ -104,7 +104,7 @@ endian="little" size="32" variant="v7" - version="1.103" + version="1.104" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -124,7 +124,7 @@ instructionEndian="little" size="32" variant="v7LEInstruction" - version="1.103" + version="1.104" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -139,7 +139,7 @@ endian="big" size="32" variant="v7" - version="1.103" + version="1.104" slafile="ARM7_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -157,7 +157,7 @@ endian="little" size="32" variant="Cortex" - version="1.103" + version="1.104" slafile="ARM7_le.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -177,7 +177,7 @@ endian="big" size="32" variant="Cortex" - version="1.103" + version="1.104" slafile="ARM7_be.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -196,7 +196,7 @@ endian="little" size="32" variant="v6" - version="1.103" + version="1.104" slafile="ARM6_le.sla" processorspec="ARMt_v6.pspec" manualindexfile="../manuals/ARM.idx" @@ -216,7 +216,7 @@ endian="big" size="32" variant="v6" - version="1.103" + version="1.104" slafile="ARM6_be.sla" processorspec="ARMt_v6.pspec" manualindexfile="../manuals/ARM.idx" @@ -236,7 +236,7 @@ endian="little" size="32" variant="v5t" - version="1.103" + version="1.104" slafile="ARM5t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -254,7 +254,7 @@ endian="big" size="32" variant="v5t" - version="1.103" + version="1.104" slafile="ARM5t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -272,7 +272,7 @@ endian="little" size="32" variant="v5" - version="1.103" + version="1.104" slafile="ARM5_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -304,7 +304,7 @@ endian="little" size="32" variant="v4t" - version="1.103" + version="1.104" slafile="ARM4t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -321,7 +321,7 @@ endian="big" size="32" variant="v4t" - version="1.103" + version="1.104" slafile="ARM4t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -338,7 +338,7 @@ endian="little" size="32" variant="v4" - version="1.103" + version="1.104" slafile="ARM4_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -358,7 +358,7 @@ endian="big" size="32" variant="v4" - version="1.103" + version="1.104" slafile="ARM4_be.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" diff --git a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc index a190525137..166ca66cee 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc @@ -103,6 +103,22 @@ define token instrArm (32) Qm1=(0,3) Dn0=(16,19) Dd0=(12,15) + Dd_1=(12,15) + Dd_2=(12,15) + Dd_3=(12,15) + Dd_4=(12,15) + Dd_5=(12,15) + Dd_6=(12,15) + Dd_7=(12,15) + Dd_8=(12,15) + Dd_9=(12,15) + Dd_10=(12,15) + Dd_11=(12,15) + Dd_12=(12,15) + Dd_13=(12,15) + Dd_14=(12,15) + Dd_15=(12,15) + Dd_16=(12,15) Dm0=(0,3) Dn1=(16,19) Dd1=(12,15) @@ -117,6 +133,8 @@ define token instrArm (32) Sd1=(12,15) Sm1=(0,3) Sm1next=(0,3) + Sm0_3=(0,2) + Sm1_3=(0,2) cmode=(8,11) @@ -286,12 +304,14 @@ define token instrArm (32) thv_Sm1=(16,19) thv_Sm1next=(16,19) thv_cmode=(24,27) + thv_Sm0_3=(16,18) + thv_Sm1_3=(16,18) thv_Rd=(28,31) thv_Rt=(28,31) thv_Rn=(0,3) thv_Rm=(16,19) - thv_Rt2=(24,27) + thv_Rt2=(24,27) thv_immed=(16,23) # Arbitrary bit fields for 32-bit Little Endian Thumb @@ -447,6 +467,8 @@ define token instrArm (32) thv_Sd1=(12,15) thv_Sm1=(0,3) thv_Sm1next=(0,3) + thv_Sm0_3=(0,2) + thv_Sm1_3=(0,2) thv_cmode=(8,11) thv_Rd=(12,15) diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc index 67eab34c1c..975155ea5d 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -45,22 +45,22 @@ Qm: thv_Qm1 is TMode=1 & thv_Qm1 & thv_M5=1 { export thv_Qm1; } attach variables [ Dm_3 thv_Dm_3 ] [ d0 d1 d2 d3 d4 d5 d6 d7 ]; attach variables [ Dn0 Dd0 Dm0 Dm_4 thv_Dn0 thv_Dd0 thv_Dm0 thv_Dm_4 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; -attach variables [ thv_Dd_1 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; -attach variables [ thv_Dd_2 ] [ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ ]; -attach variables [ thv_Dd_3 ] [ d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ ]; -attach variables [ thv_Dd_4 ] [ d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ ]; -attach variables [ thv_Dd_5 ] [ d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ ]; -attach variables [ thv_Dd_6 ] [ d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ ]; -attach variables [ thv_Dd_7 ] [ d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ ]; -attach variables [ thv_Dd_8 ] [ d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_9 ] [ d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_10 ] [ d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_11 ] [ d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_12 ] [ d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_13 ] [ d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_14 ] [ d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_15 ] [ d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; -attach variables [ thv_Dd_16 ] [ d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_1 Dd_1 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; +attach variables [ thv_Dd_2 Dd_2 ] [ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ ]; +attach variables [ thv_Dd_3 Dd_3 ] [ d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ ]; +attach variables [ thv_Dd_4 Dd_4 ] [ d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ ]; +attach variables [ thv_Dd_5 Dd_5 ] [ d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ ]; +attach variables [ thv_Dd_6 Dd_6 ] [ d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ ]; +attach variables [ thv_Dd_7 Dd_7 ] [ d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ ]; +attach variables [ thv_Dd_8 Dd_8 ] [ d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_9 Dd_9 ] [ d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_10 Dd_10 ] [ d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_11 Dd_11 ] [ d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_12 Dd_12 ] [ d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_13 Dd_13 ] [ d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_14 Dd_14 ] [ d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_15 Dd_15 ] [ d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_16 Dd_16 ] [ d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; Dd: Dd0 is TMode=0 & Dd0 & D22=0 { export Dd0; } Dn: Dn0 is TMode=0 & Dn0 & N7=0 { export Dn0; } @@ -84,6 +84,14 @@ Dd: thv_Dd1 is TMode=1 & thv_Dd1 & thv_D22=1 { export thv_Dd1; } Dn: thv_Dn1 is TMode=1 & thv_Dn1 & thv_N7=1 { export thv_Dn1; } Dm: thv_Dm1 is TMode=1 & thv_Dm1 & thv_M5=1 { export thv_Dm1; } +attach variables [ Sm0_3 thv_Sm0_3 ][s0 s2 s4 s6 s8 s10 s12 s14]; +attach variables [ Sm1_3 thv_Sm1_3][s1 s3 s5 s7 s9 s11 s13 s15]; + +Sm_3: Sm0_3 is TMode=0 & Sm0_3 & M5=0 { export Sm0_3; } +Sm_3: Sm1_3 is TMode=0 & Sm1_3 & M5=1 { export Sm1_3; } +Sm_3: thv_Sm0_3 is TMode=1 & thv_Sm0_3 & M5=0 { export thv_Sm0_3; } +Sm_3: thv_Sm1_3 is TMode=1 & thv_Sm1_3 & M5=1 { export thv_Sm1_3; } + @endif # SIMD || VFPv3 @if defined(VFPv2) || defined(VFPv3) @@ -342,11 +350,31 @@ esize0607: "16" is TMode=1 & thv_c0607=1 { export 2:4; } esize0607: "32" is TMode=1 & thv_c0607=2 { export 4:4; } esize0607: "64" is TMode=1 & thv_c0607=3 { export 8:4; } # see VLD4 (single 4-element structure to all lanes) -fesize2021: "16" is TMode=0 & c2020=1 { export 4:4; } -fesize2021: "32" is TMode=0 & c2020=0 { export 2:4; } + +fesize2323: "16" is TMode=0 & c2323=1 { export 4:4; } +fesize2323: "32" is TMode=0 & c2323=0 { export 2:4; } +fesize2323: "16" is TMode=1 & thv_c2323=1 { export 4:4; } +fesize2323: "32" is TMode=1 & thv_c2323=0 { export 2:4; } + +fesize2021: "16" is TMode=0 & c2020=1 { export 4:4; } +fesize2021: "32" is TMode=0 & c2020=0 { export 2:4; } fesize2021: "16" is TMode=1 & thv_c2020=1 { export 4:4; } fesize2021: "32" is TMode=1 & thv_c2020=0 { export 2:4; } +fesize1819: "16" is TMode=0 & c1819=1 { export 4:4; } +fesize1819: "32" is TMode=0 & c1819=2 { export 2:4; } +fesize1819: "16" is TMode=1 & thv_c1819=1 { export 4:4; } +fesize1819: "32" is TMode=1 & thv_c1819=2 { export 2:4; } + +roundType: "a" is TMode=0 & c0809=0 { export 0:1; } +roundType: "a" is TMode=1 & thv_c0809=0 { export 0:1; } +roundType: "n" is TMode=0 & c0809=1 { export 1:1; } +roundType: "n" is TMode=1 & thv_c0809=1 { export 1:1; } +roundType: "p" is TMode=0 & c0809=2 { export 2:1; } +roundType: "p" is TMode=1 & thv_c0809=2 { export 2:1; } +roundType: "m" is TMode=0 & c0809=3 { export 3:1; } +roundType: "m" is TMode=1 & thv_c0809=3 { export 3:1; } + define pcodeop VFPExpandImmediate; @@ -457,6 +485,221 @@ define pcodeop VectorAbsolute; define pcodeop FloatVectorAbsolute; @if defined(SIMD) +# CryptOp(val) +# Various crypto algorithms, too numerous for explication at +# this time + +define pcodeop CryptOp; +####### +# AESD single round decryption + +define pcodeop AESInvShiftRows; +define pcodeop AESInvSubBytes; +# F6.1.1 p3235 A1/T1 +:aesd.8 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001101 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001101 & thv_c0404=0)) + & Qd & Qm +{ + local shiftRows:16 = AESInvShiftRows(Qd ^ Qm); + Qd = AESInvSubBytes(shiftRows); +} + +####### +# AESE single round encryption + +define pcodeop AESShiftRows; +define pcodeop AESSubBytes; +# F6.1.2 p3237 A1/T1 +:aese.8 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001100 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001100 & thv_c0404=0)) + & Qd & Qm +{ + local shiftRows:16 = AESInvShiftRows(Qd ^ Qm); + Qd = AESSubBytes(shiftRows); +} + +####### +# AESIMC inverse mix columns + +define pcodeop AESInvMixColumns; +# F6.1.3 p3239 A1/T1 +:aesimc.8 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001111 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001111 & thv_c0404=0)) + & Qd & Qm +{ + Qd = AESInvMixColumns(Qm); +} + +####### +# AESMC mix columns + +define pcodeop AESMixColumns; +# F6.1.4 p3240 A1/T1 +:aesmc.8 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001110 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001110 & thv_c0404=0)) + & Qd & Qm +{ + Qd = AESMixColumns(Qm); +} + +####### +# SHA1C SHA1 hash update (choose) + +define pcodeop SHA1HashUpdateChoose; +# F6.1.7 p3248 A1/T1 +:sha1c.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateChoose(X, Y, W); +} + +####### +# SHA1H SHA1 fixed rotate + +# F6.1.8 p3250 A1/T1 +:sha1h.32 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b01 & c0611=0b001011 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b01 & thv_c0611=0b001011 & thv_c0404=0)) + & Qd & Qm +{ + local W:4 = Qm(0); + Qd = zext(W << 30 | W >> 2); +} + +####### +# SHA1M SHA1 hash update (majority) + +define pcodeop SHA1HashUpdateMajority; +# F6.1.9 p3251 A1/T1 +:sha1m.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateMajority(X, Y, W); +} + +####### +# SHA1P SHA1 hash update (parity) + +define pcodeop SHA1HashUpdateParity; +# F6.1.10 p3253 A1/T1 +:sha1p.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateParity(X, Y, W); +} + +####### +# SHA1SU0 SHA1 schedule update 0 + +# F6.1.11 p3255 A1/T1 +:sha1su0.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b11 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local op1 = Qd; + local op2 = Qn; + local op3 = Qm; + local op2lo:8 = op2(0); + local op1hi:8 = op1(8); + op2 = zext(op2lo << 64) | zext(op1hi); + Qd = op1 ^ op2 ^ op3; +} + +####### +# SHA1SU1 SHA1 schedule update 1 + +# F6.1.12 p3257 A1/T1 +:sha1su1.32 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001110 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001110 & thv_c0404=0)) + & Qd & Qm +{ + local X = Qd; + local Y = Qm; + local Tm = X ^ (Y >> 32); + local t0:4 = Tm(0); + local t1:4 = Tm(4); + local t2:4 = Tm(8); + local t3:4 = Tm(12); + local W0:4 = (t0 << 1 | t0 >> 31); + local W1:4 = (t1 << 1 | t1 >> 31); + local W2:4 = (t2 << 1 | t2 >> 31); + local W3:4 = (t3 << 1 | t3 >> 31) ^ (t0 << 2 | t0 >> 30); + Qd = zext(W3 << 96) | zext(W2 << 64) | zext(W1 << 32) | zext(W0); +} + +####### +# SHA256H SHA256 hash update part 1 + +define pcodeop SHA256hash; +# F6.1.13 p3259 A1/T1 +:sha256h.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local part1:1 = 1; + Qd = SHA256hash(Qd,Qn,Qm, part1); +} + +####### +# SHA256H2 SHA256 hash update part 2 + +# F6.1.14 p3260 A1/T1 +:sha256h2.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local part1:1 = 0; + Qd = SHA256hash(Qd,Qn,Qm, part1); +} + +####### +# SHA256SU0 SHA256 schedule update 0 + +define pcodeop SHA256ScheduleUpdate0; +# F6.1.15 p3261 A1/T1 +:sha256su0.32 Qd,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001111 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001111 & thv_c0404=0)) + & Qd & Qm +{ + Qd = SHA256ScheduleUpdate0(Qd,Qm); +} + +####### +# SHA256SU1 SHA256 schedule update 1 + +define pcodeop SHA256ScheduleUpdate1; +# F6.1.16 p3263 A1/T1 +:sha256su1.32 Qd,Qn,Qm + is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + Qd = SHA256ScheduleUpdate1(Qd,Qn,Qm); +} # TODO: watch out for c2021=3 @@ -496,16 +739,16 @@ define pcodeop FloatVectorAbsolute; Qd = VectorAbsoluteDifference(Dn,Dm,esize2021,udt); } -:vabd.f32 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=6 & c2021=2 & c0811=13 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=13 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & Dn +:vabd.f^fesize2021 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=6 & c0811=13 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=0 & thv_c0404=0 ) ) & fesize2021 & Dd & Dm & Dn { - Dd = FloatVectorAbsoluteDifference(Dn,Dm,2:1,32:1); + Dd = FloatVectorAbsoluteDifference(Dn,Dm,fesize2021); } -:vabd.f32 Qd,Qn,Qm is ( ( $(AMODE) & cond=15 & c2327=6 & c2021=2 & c0811=13 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=13 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & Qn +:vabd.f^fesize2021 Qd,Qn,Qm is ( ( $(AMODE) & cond=15 & c2327=6 & c0811=13 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=1 & thv_c0404=0 ) ) & fesize2021 & Qd & Qm & Qn { - Qd = FloatVectorAbsoluteDifference(Qn,Qm,2:1,32:1); + Qd = FloatVectorAbsoluteDifference(Qn,Qm,fesize2021); } :vabs.s^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=6 & Q6=0 & c0404=0 ) | @@ -521,24 +764,24 @@ define pcodeop FloatVectorAbsolute; } -:vabs.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xe & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xe & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dd +:vabs.f^fesize2021 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1819=2 & c1617=1 & c0711=0xe & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xe & thv_c0606=0 & thv_c0404=0 ) ) & fesize2021 & Dm & Dd { - Dd = FloatVectorAbsolute(Dm,2:1,32:1); + Dd = FloatVectorAbsolute(Dm,fesize2021); } -:vabs.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xe & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xe & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +:vabs.f^fesize2021 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1819=2 & c1617=1 & c0711=0xe & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xe & thv_c0606=1 & thv_c0404=0 ) ) & fesize2021 & Qd & Qm { - Qd = FloatVectorAbsolute(Qm,2:1,32:1); + Qd = FloatVectorAbsolute(Qm,fesize2021); } @endif # SIMD @if defined(VFPv2) || defined(VFPv3) -:vabs^COND^".f32" Sd,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2b & c0404=0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2b & thv_c0404=0 ) ) & Sm & Sd +:vabs^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sm & Sd { build COND; build Sd; @@ -546,8 +789,8 @@ define pcodeop FloatVectorAbsolute; Sd = abs(Sm); } -:vabs^COND^".f64" Dd,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2f & c0404=0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2f & thv_c0404=0 ) ) & Dd & Dm +:vabs^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Dm { build COND; build Dd; @@ -559,6 +802,7 @@ define pcodeop FloatVectorAbsolute; define pcodeop FloatCompareGE; define pcodeop FloatCompareGT; +define pcodeop VectorAbs; define pcodeop VectorAdd; define pcodeop VectorSub; define pcodeop FloatVectorAdd; @@ -570,118 +814,122 @@ define pcodeop FloatVectorPairwiseMin; define pcodeop FloatVectorPairwiseMax; define pcodeop VectorPairwiseAddLong; define pcodeop VectorPairwiseAddAccumulateLong; +define pcodeop VectorGetElement; @if defined(SIMD) -:vacge.f32 Dd,Dn,Dm is $(AMODE) & cond=15 & c2327=6 & c2021=0 & Dn & Dd & c0811=14 & Q6=0 & c0404=1 & Dm +:vacge.f^fesize2021 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=6 & c2020=0 & c0811=14 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2020=0 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2021 & Dn & Dd & Dm { - Dd = FloatCompareGE(Dn,Dm,2:1,32:1); + Dd = FloatCompareGE(Dn,Dm,fesize2021); } -:vacge.f32 Qd,Qn,Qm is $(AMODE) & cond=15 & c2327=6 & c2021=0 & Qn & Qd & c0811=14 & Q6=1 & c0404=1 & Qm +:vacge.f^fesize2021 Qd,Qn,Qm is ( ( $(AMODE) & cond=15 & c2327=6 & c2020=0 & c0811=14 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2020=0 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2021 & Qn & Qd & Qm { - Qd = FloatCompareGE(Qn,Qm,2:1,32:1); + Qd = FloatCompareGE(Qn,Qm,fesize2021); } -:vacgt.f32 Dd,Dn,Dm is $(AMODE) & cond=15 & c2327=6 & c2021=2 & Dn & Dd & c0811=14 & Q6=0 & c0404=1 & Dm +:vacgt.f^fesize2021 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=6 & c2020=1 & c0811=14 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2020=1 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2021 & Dn & Dd & Dm { - Dd = FloatCompareGT(Dn,Dm,2:1,32:1); + Dd = FloatCompareGT(Dn,Dm,fesize2021); } -:vacgt.f32 Qd,Qn,Qm is $(AMODE) & cond=15 & c2327=6 & c2021=2 & Qn & Qd & c0811=14 & Q6=1 & c0404=1 & Qm +:vacgt.f^fesize2021 Qd,Qn,Qm is ( ( $(AMODE) & cond=15 & c2327=6 & c2020=1 & c0811=14 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2020=1 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2021 & Qn & Qd & Qm { - Qd = FloatCompareGT(Qn,Qm,2:1,32:1); + Qd = FloatCompareGT(Qn,Qm,fesize2021); } -:vadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=8 & Q6=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm +:vadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=8 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm { Dd = VectorAdd(Dn,Dm,esize2021); } -:vadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=8 & Q6=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0) ) & esize2021 & Qm & Qn & Qd +:vadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=8 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd { Qd = VectorAdd(Qn,Qm,esize2021); } -:vadd.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=0 & c0811=13 & Q6=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & Dm& Dn & Dd +:vadd.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { - Dd = FloatVectorAdd(Dn,Dm,2:1,32:1); + Dd = FloatVectorAdd(Dn,Dm,fesize2021); } -:vadd.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=0 & c0811=13 & Q6=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & Qn & Qd & Qm +:vadd.f^fesize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & fesize2021 & Qn & Qd & Qm { - Qd = FloatVectorAdd(Qn,Qm,2:1,32:1); + Qd = FloatVectorAdd(Qn,Qm,fesize2021); } - -:vpadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=11 & Q6=0 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=11 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm +:vpadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=11 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=11 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm { Dd = VectorPairwiseAdd(Dn,Dm,esize2021); } -:vpadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021<3 & c0811=11 & Q6=1 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=11 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +:vpadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021<3 & c0811=11 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=11 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd { Qd = VectorPairwiseAdd(Qn,Qm,esize2021); } -:vpadd.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=13 & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm& Dn & Dd +:vpadd.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=13 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm& Dn & Dd { Dd = FloatVectorPairwiseAdd(Dn,Dm,fesize2021:1); } -:vpmax.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0)) & udt & esize2021 & Dn & Dd & Dm +:vpmax.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0)) & udt & esize2021 & Dn & Dd & Dm { Dd = VectorPairwiseMax(Dn,Dm,esize2021,udt); } -:vpmax.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=15 & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd +:vpmax.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { Dd = FloatVectorPairwiseMax(Dn,Dm,fesize2021:1); } -:vpmin.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm +:vpmin.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm { Dd = VectorPairwiseMin(Dn,Dm,esize2021,udt); } -:vpmin.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=1 & c0811=15 & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=1 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd +:vpmin.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=1 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { - Dd = FloatVectorPairwiseMin(Dn,Dm,fesize2021:1); + Dd = FloatVectorPairwiseMin(Dn,Dm,fesize2021); } -:vpadal.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm +:vpadal.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm { Dd = VectorPairwiseAddAccumulateLong(Dm,esize1819); } -:vpadal.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm +:vpadal.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm { Qd = VectorPairwiseAddAccumulateLong(Qm,esize1819); } -:vpaddl.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm +:vpaddl.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm { Dd = VectorPairwiseAddLong(Dm,esize1819); } -:vpaddl.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm +:vpaddl.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm { Qd = VectorPairwiseAddLong(Qm,esize1819); } @@ -690,8 +938,19 @@ define pcodeop VectorPairwiseAddAccumulateLong; @if defined(VFPv2) || defined(VFPv3) -:vadd^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sd & Sn +:vadd^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn +{ + build COND; + build Sd; + build Sm; + build Sn; + local result:2 = Sn(0) f+ Sm(0); + Sd = zext(result); +} + +:vadd^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn { build COND; build Sd; @@ -700,8 +959,8 @@ define pcodeop VectorPairwiseAddAccumulateLong; Sd = Sn f+ Sm; } -:vadd^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & Dm & Dd & Dn +:vadd^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dd & Dn { build COND; build Dd; @@ -724,23 +983,26 @@ define pcodeop VectorCompareGreaterThan; define pcodeop FloatVectorCompareGreaterThan; define pcodeop VectorCountLeadingSignBits; define pcodeop VectorCountLeadingZeros; +define pcodeop VectorComplexAdd; +define pcodeop VectorComplexMultiplyAccumulate; +define pcodeop VectorComplexMultiplyAccumulateByElement; @if defined(SIMD) -:vaddhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=5 & c2021<3 & c0811=4 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & esize2021x2 & Qn & Dd & Qm +:vaddhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=5 & c2021<3 & c0811=4 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & esize2021x2 & Qn & Dd & Qm { Dd = VectorAddReturnHigh(Qn,Qm,esize2021x2); } -:vaddl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0 & c0606=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm +:vaddl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm { Qd = VectorAdd(Dn,Dm,esize2021,udt); } -:vaddw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=1 & c0606=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm +:vaddw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=1 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm { Qd = VectorAdd(Qn,Dm,esize2021,udt); } @@ -758,14 +1020,26 @@ define pcodeop VectorCountLeadingZeros; Qd = Qn & Qm; } -:vbic.i16 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=3 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8 +:vbic.i32 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8 { Dd = Dd & ~simdExpImm_8; } -:vbic.i32 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=7 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16 +:vbic.i32 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = Qd & ~simdExpImm_16; +} + +:vbic.i16 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = Dd & ~simdExpImm_8; +} + +:vbic.i16 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16 { Qd = Qd & ~simdExpImm_16; } @@ -818,220 +1092,272 @@ define pcodeop VectorCountLeadingZeros; Qd = VectorBitwiseSelect(Qd,Qn,Qm); } -:vceq.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=0 & c0404=1) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd +crot2424: "#"^90 is ($(AMODE) & c2424=0 ) | (TMode=1 & thv_c2424=0) { local tmp:4 = 90; export tmp; } +crot2424: "#"^270 is ($(AMODE) & c2424=1 ) | (TMode=1 & thv_c2424=1) { local tmp:4 = 270; export tmp; } + + +:vcadd.f^fesize2021 Dd,Dn,Dm,crot2424 is ( ($(AMODE) & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2121=0 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1)) & crot2424 & fesize2021 & Dm & Dn & Dd +{ + Dd = VectorComplexAdd(Dd,Dn,Dm,crot2424,fesize2021); +} + +:vcadd.f^fesize2021 Qd,Qn,Qm,crot2424 is ( ($(AMODE) & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=1 & c0404=1 )| + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2021=0 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1)) & crot2424 & fesize2021 & Qm & Qn & Qd +{ + Qd = VectorComplexAdd(Qd,Qn,Qm,crot2424,fesize2021); +} + + +:vceq.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd { Dd = VectorCompareEqual(Dn,Dm,esize2021); } -:vceq.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=1 & c0404=1) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +:vceq.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd { Qd = VectorCompareEqual(Qn,Qm,esize2021); } -:vceq.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=0 & c0811=14 & Q6=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Dd +:vceq.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { - Dd = FloatVectorCompareEqual(Dn,Dm,2:1,32:1); + Dd = FloatVectorCompareEqual(Dn,Dm,fesize2021); } -:vceq.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=0 & c0811=14 & Q6=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & Qm & Qn & Qd +:vceq.f^fesize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2021 & Qm & Qn & Qd { - Qd = FloatVectorCompareEqual(Qn,Qm,2:1,32:1); + Qd = FloatVectorCompareEqual(Qn,Qm,fesize2021); } -:vceq.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vceq.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero { Dd = VectorCompareEqual(Dm,zero,esize1819); } -:vceq.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vceq.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero { Qd = VectorCompareEqual(Qm,zero,esize1819); } -:vceq.f32 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=10 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=10 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vceq.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=10 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=10 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero { - Dd = FloatVectorCompareEqual(Dm,zero,2:1,32:1); + Dd = FloatVectorCompareEqual(Dm,zero,fesize1819); } -:vceq.f32 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=10 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=10 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vceq.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=10 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=10 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero { - Qd = FloatVectorCompareEqual(Qm,zero,2:1,32:1); + Qd = FloatVectorCompareEqual(Qm,zero,fesize1819); } -:vcge.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=1) ) & udt & esize2021 & Dm & Dn & Dd +:vcge.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=1) ) & udt & esize2021 & Dm & Dn & Dd { Dd = VectorCompareGreaterThanOrEqual(Dn,Dm,esize2021,udt); } -:vcge.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd +:vcge.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd { Qd = VectorCompareGreaterThanOrEqual(Qn,Qm,esize2021,udt); } -:vcge.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=14 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Dd +:vcge.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { Dd = FloatVectorCompareGreaterThanOrEqual(Dn,Dm,2:1,32:1); } -:vcge.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=14 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & Qm & Qn & Qd +:vcge.f^fesize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2021 & Qm & Qn & Qd { Qd = FloatVectorCompareGreaterThanOrEqual(Qn,Qm,2:1,32:1); } -:vcge.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vcge.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero { Dd = VectorCompareGreaterThanOrEqual(Dm,zero,esize1819); } -:vcge.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vcge.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero { Qd = VectorCompareGreaterThanOrEqual(Qm,zero,esize1819); } -:vcge.f32 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=9 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vcge.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero { - Dd = FloatVectorCompareGreaterThanOrEqual(Dm,zero,2:1,32:1); + Dd = FloatVectorCompareGreaterThanOrEqual(Dm,zero,fesize1819); } -:vcge.f32 Qd,Qm,zero is( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=9 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vcge.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero { - Qd = FloatVectorCompareGreaterThanOrEqual(Qm,zero,2:1,32:1); + Qd = FloatVectorCompareGreaterThanOrEqual(Qm,zero,fesize1819); } -:vcgt.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dm & Dn & Dd +:vcgt.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dm & Dn & Dd { Dd = VectorCompareGreaterThan(Dn,Dm,esize2021); } -:vcgt.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=0) ) & udt & esize2021 & Qm & Qn & Qd +:vcgt.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=0) ) & udt & esize2021 & Qm & Qn & Qd { Qd = VectorCompareGreaterThan(Qn,Qm,esize2021); } -:vcgt.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=2 & c0811=14 & Q6=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Dd +:vcgt.f^fesize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2021 & Dm & Dn & Dd { - Dd = FloatVectorCompareGreaterThan(Dn,Dm,2:1,32:1); + Dd = FloatVectorCompareGreaterThan(Dn,Dm,fesize2021); } -:vcgt.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=2 & c0811=14 & Q6=1 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & Qm & Qn & Qd +:vcgt.f^fesize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2021 & Qm & Qn & Qd { - Qd = FloatVectorCompareGreaterThan(Qn,Qm,2:1,32:1); + Qd = FloatVectorCompareGreaterThan(Qn,Qm,fesize2021); } -:vcgt.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=0 & thv_c0404=0 ) ) & esize1819 & Dd & Dm & zero +:vcgt.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=0 & thv_c0404=0 ) ) & esize1819 & Dd & Dm & zero { Dd = VectorCompareGreaterThan(Dm,zero,esize1819); } -:vcgt.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm & zero +:vcgt.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm & zero { Qd = VectorCompareGreaterThan(Qm,zero,esize1819); } -:vcgt.f32 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=8 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0 ) ) & esize1819 & Dd & Dm & zero +:vcgt.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0 ) ) & fesize1819 & Dd & Dm & zero { - Dd = FloatVectorCompareGreaterThan(Dm,zero,2:1,32:1); + Dd = FloatVectorCompareGreaterThan(Dm,zero,fesize1819); } -:vcgt.f32 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=8 & Q6=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm & zero +:vcgt.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm & zero { - Qd = FloatVectorCompareGreaterThan(Qm,zero,2:1,32:1); + Qd = FloatVectorCompareGreaterThan(Qm,zero,fesize1819); } -:vcle.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm & zero +:vcle.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm & zero { Dd = VectorCompareGreaterThanOrEqual(zero,Dm,esize1819); } -:vcle.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=1 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm & zero +:vcle.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm & zero { Qd = VectorCompareGreaterThanOrEqual(zero,Qm,esize1819); } -:vcle.f32 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0xb & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0xb & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm & zero +:vcle.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dd & Dm & zero { - Dd = FloatVectorCompareGreaterThanOrEqual(zero,Dm,2:1,32:1); + Dd = FloatVectorCompareGreaterThanOrEqual(zero,Dm,fesize1819); } -:vcle.f32 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0xb & Q6=1 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0xb & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm & zero +:vcle.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qd & Qm & zero { - Qd = FloatVectorCompareGreaterThanOrEqual(zero,Qm,2:1,32:1); + Qd = FloatVectorCompareGreaterThanOrEqual(zero,Qm,fesize1819); } -:vcls.s^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=0 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm +:vcls.s^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm { Dd = VectorCountLeadingSignBits(Dm,esize1819); } -:vcls.s^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=1 & c0404=0) | - ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm +:vcls.s^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm { Qd = VectorCountLeadingSignBits(Qm,esize1819); } -:vclt.s^esize1819 Dd,Dm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=0 & c0404=0) | - ( $(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vclt.s^esize1819 Dd,Dm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero { Dd = VectorCompareGreaterThan(zero,Dm,esize1819); } -:vclt.s^esize1819 Qd,Qm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=1 & c0404=0) | - ( $(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vclt.s^esize1819 Qd,Qm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero { Qd = VectorCompareGreaterThan(zero,Qm,esize1819); } -:vclt.f32 Dd,Dm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=12 & Q6=0 & c0404=0) | - ( $(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=12 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +:vclt.f^fesize1819 Dd,Dm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero { - Dd = FloatVectorCompareGreaterThan(zero,Dm,2:1,32:1); + Dd = FloatVectorCompareGreaterThan(zero,Dm,fesize1819); } -:vclt.f32 Qd,Qm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=12 & Q6=1 & c0404=0) | - ( $(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=12 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +:vclt.f^fesize1819 Qd,Qm,zero is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero { - Qd = FloatVectorCompareGreaterThan(zero,Qm,2:1,32:1); + Qd = FloatVectorCompareGreaterThan(zero,Qm,fesize1819); } -:vclz.i^esize1819 Dd,Dm is $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & esize1819 & c1617=0 & Dd & c0711=9 & Q6=0 & c0404=0 & Dm +:vclz.i^esize1819 Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm { Dd = VectorCountLeadingZeros(Dm,esize1819); } -:vclz.i^esize1819 Qd,Qm is $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & esize1819 & c1617=0 & Qd & c0711=9 & Q6=1 & c0404=0 & Qm +:vclz.i^esize1819 Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm { Qd = VectorCountLeadingZeros(Qm,esize1819); } +crot2324: "#"^0 is ($(AMODE) & c2324=0 ) | (TMode=1 & thv_c2324=0) { local tmp:4 = 0; export tmp; } +crot2324: "#"^90 is ($(AMODE) & c2324=1 ) | (TMode=1 & thv_c2324=1) { local tmp:4 = 90; export tmp; } +crot2324: "#"^180 is ($(AMODE) & c2324=2 ) | (TMode=1 & thv_c2324=2) { local tmp:4 = 180; export tmp; } +crot2324: "#"^270 is ($(AMODE) & c2324=3 ) | (TMode=1 & thv_c2324=3) { local tmp:4 = 270; export tmp; } +crot2021: "#"^0 is ($(AMODE) & c2021=0 ) | (TMode=1 & thv_c2021=0) { local tmp:4 = 0; export tmp; } +crot2021: "#"^90 is ($(AMODE) & c2021=1 ) | (TMode=1 & thv_c2021=1) { local tmp:4 = 90; export tmp; } +crot2021: "#"^180 is ($(AMODE) & c2021=2 ) | (TMode=1 & thv_c2021=2) { local tmp:4 = 180; export tmp; } +crot2021: "#"^270 is ($(AMODE) & c2021=3 ) | (TMode=1 & thv_c2021=3) { local tmp:4 = 270; export tmp; } + +:vcmla.f^fesize2021 Dd,Dn,Dm,crot2324 is ( ($(AMODE) & cond=15 & c2527=6 & c2323=1 & c2121=1 & c0811=8 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2121=1 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2324 & fesize2021 & Dm & Dn & Dd +{ + Dd = VectorComplexMultiplyAccumulate(Dd,Dn,Dm,crot2324,fesize2021); +} + +:vcmla.f^fesize2021 Qd,Qn,Qm,crot2324 is ( ($(AMODE) & cond=15 & c2527=6 & c2323=1 & c2121=1 & c0811=8 & Q6=1 & c0404=0 )| + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2021=1 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2324 & fesize2021 & Qm & Qn & Qd +{ + Qd = VectorComplexMultiplyAccumulate(Qd,Qn,Qm,crot2324,fesize2021); +} + +:vcmla.f^fesize2323 Dd,Dn,Dm,crot2021 is ( ($(AMODE) & cond=15 & c2527=7 & c2424=0 & c2121=1 & c0811=8 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c2121=1 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2021 & fesize2323 & Dm & Dn & Dd +{ + Dd = VectorComplexMultiplyAccumulateByElement(Dd,Dn,Dm,crot2021,fesize2323); +} + +:vcmla.f^fesize2323 Qd,Qn,Qm,crot2021 is ( ($(AMODE) & cond=15 & c2527=7 & c2424=0 & c2121=1 & c0811=8 & Q6=1 & c0404=0 )| + ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c2021=1 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2021 & fesize2323 & Qm & Qn & Qd +{ + Qd = VectorComplexMultiplyAccumulateByElement(Qd,Qn,Qm,crot2021,fesize2323); +} + @endif # SIMD # set float register flags correctly for comparison @@ -1049,8 +1375,20 @@ macro FloatVectorCompare(op1,op2,nanx) { nanx: "e" is c0707=1 { export 1:1; } nanx: is c0707=0 { export 0:1; } -:vcmp^nanx^COND^".f32" Sd,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1010 & c0606=1 & c0404=0) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1010 & thv_c0606=1 & thv_c0404=0) ) & Sd & nanx & Sm +:vcmp^nanx^COND^".f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1001 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1001 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm +{ + build COND; + build Sd; + build Sm; + local sm16:2 = Sm(0); + local sd16:2 = Sd(0); + + FloatVectorCompare(sd16,sm16,nanx); +} + +:vcmp^nanx^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1010 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1010 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm { build COND; build Sd; @@ -1059,8 +1397,8 @@ nanx: is c0707=0 { export 0:1; } FloatVectorCompare(Sd,Sm,nanx); } -:vcmp^nanx^COND^".f64" Dd,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1011 & c0606=1 & c0404=0) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1011 & thv_c0606=1 & thv_c0404=0) ) & Dd & nanx & Dm +:vcmp^nanx^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1011 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1011 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & nanx & Dm { build COND; build Dd; @@ -1068,8 +1406,19 @@ nanx: is c0707=0 { export 0:1; } FloatVectorCompare(Dd,Dm,nanx); } -:vcmp^nanx^COND^".f32" Sd,zero is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1010 & c0006=0b1000000 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1010 & thv_c0006=0b1000000 ) ) & Sd & nanx & zero +:vcmp^nanx^COND^".f16" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1001 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1001 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero +{ + build COND; + build Sd; + local Zero:2 = 0; + local sd16:2 = Sd(0); + + FloatVectorCompare(sd16,Zero,nanx); +} + +:vcmp^nanx^COND^".f32" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1010 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1010 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero { build COND; build Sd; @@ -1077,8 +1426,8 @@ nanx: is c0707=0 { export 0:1; } FloatVectorCompare(Sd,Zero,nanx); } -:vcmp^nanx^COND^".f64" Dd,zero is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1011 & c0006=0b1000000 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1011 & thv_c0006=0b1000000 ) ) & Dd & nanx & zero +:vcmp^nanx^COND^".f64" Dd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1011 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1011 & thv_c0006=0b1000000 ) ) & COND & Dd & nanx & zero { build COND; build Dd; @@ -1117,59 +1466,118 @@ define pcodeop VectorUnsignedToFloat; } @ifndef VERSION_8 -:vcvt.s32.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +:vcvt.s16.f16 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { Dd = VectorFloatToSigned(Dm,3:1); } -:vcvt.u32.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +:vcvt.u16.f16 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { - Dd = VectorFloatToUnsigned(Dm,3:1); + Dd = VectorFloatToUnsigned(Dm,0:1); } -:vcvt.f32.s32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +:vcvt.f16.s16 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { Dd = VectorSignedToFloat(Dm,0:1); } -:vcvt.f32.u32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +:vcvt.f16.u16 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { Dd = VectorUnsignedToFloat(Dm,0:1); } -:vcvt.s32.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +:vcvt.s32.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { - Qd = VectorFloatToSigned(Qm,3:1); + Dd = VectorFloatToSigned(Dm,3:1); } -:vcvt.u32.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +:vcvt.u32.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { - Qd = VectorFloatToUnsigned(Qm,3:1); + Dd = VectorFloatToUnsigned(Dm,3:1); } -:vcvt.f32.s32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm - +:vcvt.f32.s32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { - Qd = VectorSignedToFloat(Qm,0:1); + Dd = VectorSignedToFloat(Dm,0:1); } -:vcvt.f32.u32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +:vcvt.f32.u32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm { - Qd = VectorUnsignedToFloat(Qm,0:1); + Dd = VectorUnsignedToFloat(Dm,0:1); +} + + + + + +:vcvt.s16.f16 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToSigned(Qm,6:1); +} + +:vcvt.u16.f16 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToUnsigned(Qm,7:1); +} + +:vcvt.f16.s16 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorSignedToFloat(Qm,4:1); +} + +:vcvt.f16.u16 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorUnsignedToFloat(Qm,5:1); +} + +:vcvt.s32.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToSigned(Qm,10:1); +} + +:vcvt.u32.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToUnsigned(Qm,11:1); +} + +:vcvt.f32.s32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorSignedToFloat(Qm,8:1); +} + +:vcvt.f32.u32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorUnsignedToFloat(Qm,9:1); } @endif # ! VERSION_8 @@ -1187,18 +1595,29 @@ roundMode: is TMode=0 & c0707=1 { export 3:1; } # Round towards zero roundMode: "r" is TMode=1 & thv_c0707=0 { tmp:1 = $(FPSCR_RMODE); export tmp; } roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero -:vcvt^roundMode^COND^".s32.f32" Sd,Sm is COND & ( ($(AMODE) &ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1b & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sm & roundMode +:vcvt^roundMode^COND^".s32.f16" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode { build COND; build Sd; build Sm; build roundMode; - Sd = VectorFloatToSigned(Sm,roundMode); + local Sm16:2 = Sm(0); + Sd = trunc(Sm16);#VectorFloatToSigned(Sm16,roundMode); } -:vcvt^roundMode^COND^".s32.f64" Sd,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & Sd & roundMode & Dm +:vcvt^roundMode^COND^".s32.f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode +{ + build COND; + build Sd; + build Sm; + build roundMode; + Sd = trunc(Sm);#VectorFloatToSigned(Sm16,roundMode); +} + +:vcvt^roundMode^COND^".s32.f64" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & roundMode & Dm { build COND; build Sd; @@ -1207,8 +1626,19 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero Sd = VectorFloatToSigned(Dm,roundMode); } -:vcvt^roundMode^COND^".u32.f32" Sd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & roundMode & Sd & Sm +:vcvt^roundMode^COND^".u32.f16" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build roundMode; + local Sm16:2 = Sm(0); + Sd = VectorFloatToUnsigned(Sm16,roundMode); +} + +:vcvt^roundMode^COND^".u32.f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm { build COND; build Sd; @@ -1217,8 +1647,8 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero Sd = VectorFloatToUnsigned(Sm,roundMode); } -:vcvt^roundMode^COND^".u32.f64" Sd,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0)) & roundMode& Sd & Dm +:vcvt^roundMode^COND^".u32.f64" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0)) & COND & roundMode & Sd & Dm { build COND; build Sd; @@ -1227,18 +1657,30 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero Sd = VectorFloatToUnsigned(Dm,roundMode); } -:vcvt^COND^".f32.s32" Sd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sm +:vcvt^COND^".f16.s32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm { build COND; build Sd; build Sm; - mode:1 = $(FPSCR_RMODE); - Sd = VectorSignedToFloat(Sm,mode); + local mode:1 = $(FPSCR_RMODE); + local Sm16:2 = Sm(0); + Sd = VectorSignedToFloat(Sm16,mode); } -:vcvt^COND^".f64.s32" Dd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Dd & Sm +:vcvt^COND^".f16.u32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local mode:1 = $(FPSCR_RMODE); + local Sm16:2 = Sm(0); + Sd = VectorUnsignedToFloat(Sm16,mode); +} + +:vcvt^COND^".f64.s32" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm { build COND; build Dd; @@ -1247,8 +1689,18 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero Dd = VectorSignedToFloat(Sm,mode); } -:vcvt^COND^".f32.u32" Sd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sm +:vcvt^COND^".f32.s32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + mode:1 = $(FPSCR_RMODE); + Sd = VectorSignedToFloat(Sm,mode); +} + +:vcvt^COND^".f32.u32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm { build COND; build Sd; @@ -1257,8 +1709,8 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero Sd = VectorUnsignedToFloat(Sm,mode); } -:vcvt^COND^".f64.u32" Dd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) )& Dd & Sm +:vcvt^COND^".f64.u32" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm { build COND; build Dd; @@ -1266,6 +1718,7 @@ roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero mode:1 = $(FPSCR_RMODE); Dd = VectorUnsignedToFloat(Sm,mode); } + @endif # ! VERSION_8 @endif # VFPv2 || VFPv3 @@ -1280,46 +1733,92 @@ define pcodeop VectorUnsignedFixedToFloat; # VCVT (between floating-point and fixed-point, Advanced SIMD) # -fbits: "#"val is c1620 [ val = 32 - c1620; ] { tmp:1 = val; export tmp; } +fbits: "#"val is TMode=0 & c1621 [ val = 64 - c1621; ] { tmp:1 = val; export tmp; } +fbits: "#"val is TMode=1 & thv_c1621 [ val = 64 - thv_c1621; ] { tmp:1 = val; export tmp; } -:vcvt.s32.f32 Dd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & fbits & Dd & c0911=7 & c0808=1 & c0707=0 & Q6=0 & c0404=1 & Dm +:vcvt.s16.f16 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm { Dd = VectorFloatToSignedFixed(Dm,fbits); } -:vcvt.u32.f32 Dd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & fbits & Dd & c0911=7 & c0808=1 & c0707=0 & Q6=0 & c0404=1 & Dm +:vcvt.u16.f16 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm + { Dd = VectorFloatToUnsignedFixed(Dm,fbits); } -:vcvt.f32.s32 Dd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & fbits & Dd & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1 & Dm +:vcvt.f16.s16 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm { Dd = VectorSignedFixedToFloat(Dm,fbits); } -:vcvt.f32.u32 Dd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & fbits & Dd & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1 & Dm +:vcvt.f16.u16 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm { Dd = VectorUnsignedFixedToFloat(Dm,fbits); } -:vcvt.s32.f32 Qd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & fbits & Qd & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1 & Dm +:vcvt.s16.f16 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm { - Qd = VectorFloatToSignedFixed(Dm,fbits); + Qd = VectorFloatToSignedFixed(Qm,fbits); } -:vcvt.u32.f32 Qd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & fbits & Qd & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1 & Dm +:vcvt.u16.f16 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm { - Qd = VectorFloatToUnsignedFixed(Dm,fbits); + Qd = VectorFloatToUnsignedFixed(Qm,fbits); } -:vcvt.f32.s32 Qd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & fbits & Qd & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1 & Dm +:vcvt.f16.s16 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm { - Qd = VectorSignedFixedToFloat(Dm,fbits); + Qd = VectorSignedFixedToFloat(Qm,fbits); } -:vcvt.f32.u32 Qd,Dm,fbits is $(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & fbits & Qd & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1 & Dm +:vcvt.f16.u16 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm { - Qd = VectorUnsignedFixedToFloat(Dm,fbits); + Qd = VectorUnsignedFixedToFloat(Qm,fbits); +} + +:vcvt.f32.s32 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorSignedFixedToFloat(Dm,fbits); +} + +:vcvt.f32.u32 Dd,Dm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorUnsignedFixedToFloat(Dm,fbits); +} + +:vcvt.s32.f32 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToSignedFixed(Qm,fbits); +} + +:vcvt.u32.f32 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToUnsignedFixed(Qm,fbits); +} + +:vcvt.f32.s32 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorSignedFixedToFloat(Qm,fbits); +} + +:vcvt.f32.u32 Qd,Qm,fbits is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorUnsignedFixedToFloat(Qm,fbits); } @endif # ! VERSION_8 @@ -1334,13 +1833,13 @@ fbits: "#"val is c1620 [ val = 32 - c1620; ] { tmp:1 = val; export tmp; } # VCVT (between floating-point and fixed-point, VFP) # -fbits16: "#"^val is TMode=0 & c0505 & c0003 [ val = 16 - ((c0505 << 4) + c0003); ] { tmp:1 = val; export tmp; } -fbits32: "#"^val is TMode=0 & c0505 & c0003 [ val = 32 - ((c0505 << 4) + c0003); ] { tmp:1 = val; export tmp; } -fbits16: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 16 - ((thv_c0505 << 4) + thv_c0003); ] { tmp:1 = val; export tmp; } -fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << 4) + thv_c0003); ] { tmp:1 = val; export tmp; } +fbits16: "#"^val is TMode=0 & c0505 & c0003 [ val = 16 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; } +fbits32: "#"^val is TMode=0 & c0505 & c0003 [ val = 32 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; } +fbits16: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 16 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; } +fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; } -:vcvt^COND^".s16.f32" Sd,Sd2,fbits16 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & Sd & Sd2 & fbits16 +:vcvt^COND^".s16.f16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 { build COND; build Sd; @@ -1349,8 +1848,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Sd = VectorFloatToSignedFixed(Sd2,16:1,fbits16); } -:vcvt^COND^".u16.f32" Sd,Sd2,fbits16 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sd2 & fbits16 +:vcvt^COND^".u16.f16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 { build COND; build Sd; @@ -1359,8 +1858,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); } -:vcvt^COND^".s32.f32" Sd,Sd2,fbits32 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sd2 & fbits32 +:vcvt^COND^".s32.f16" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 { build COND; build Sd; @@ -1369,8 +1868,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Sd = VectorFloatToSignedFixed(Sd2,32:1,fbits32); } -:vcvt^COND^".u32.f32" Sd,Sd2,fbits32 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sd2 & fbits32 +:vcvt^COND^".u32.f16" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 { build COND; build Sd; @@ -1379,8 +1878,48 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); } -:vcvt^COND^".s16.f64" Dd,Dd2,fbits16 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & Dd & Dd2 & fbits16 +:vcvt^COND^".s16.f32" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToSignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".u16.f32" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".s32.f32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToSignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".u32.f32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".s16.f64" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 { build COND; build Dd; @@ -1389,8 +1928,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Dd = VectorFloatToSignedFixed(Dd2,16:1,fbits16); } -:vcvt^COND^".u16.f64" Dd,Dd2,fbits16 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & Dd & Dd2 & fbits16 +:vcvt^COND^".u16.f64" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 { build COND; build Dd; @@ -1399,8 +1938,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Dd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16); } -:vcvt^COND^".s32.f64" Dd,Dd2,fbits32 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Dd & Dd2 & fbits32 +:vcvt^COND^".s32.f64" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 { build COND; build Dd; @@ -1409,8 +1948,8 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Dd = VectorFloatToSignedFixed(Dd2,32:1,fbits32); } -:vcvt^COND^".u32.f64" Dd,Dd2,fbits32 is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & Dd & Dd2 & fbits32 +:vcvt^COND^".u32.f64" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 { build COND; build Dd; @@ -1419,25 +1958,28 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Dd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32); } -:vcvt^COND^".f32.s16" Sd,Sd2,fbits16 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & Sd & Sd2 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0 & fbits16 +:vcvt^COND^".f16.s16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 { build COND; build Sd; build Sd2; build fbits16; - Sd = VectorSignedFixedToFloat(Sd2,32:1,fbits16); + Sd = VectorSignedFixedToFloat(Sd2,16:1,fbits16); } -:vcvt^COND^".f32.u16" Sd,Sd2,fbits16 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & Sd & Sd2 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0 & fbits16 +:vcvt^COND^".f16.u16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 { build COND; build Sd; build Sd2; build fbits16; - Sd = VectorUnsignedFixedToFloat(Sd2,32:1,fbits16); + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); } -:vcvt^COND^".f32.s32" Sd,Sd2,fbits32 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & Sd & Sd2 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0 & fbits32 +:vcvt^COND^".f16.s32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 { build COND; build Sd; @@ -1446,49 +1988,94 @@ fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0505 << Sd = VectorSignedFixedToFloat(Sd2,32:1,fbits32); } -:vcvt^COND^".f32.u32" Sd,Sd2,fbits32 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & Sd & Sd2 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0 & fbits32 +:vcvt^COND^".f16.u32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 { build COND; build Sd; build Sd2; build fbits32; - Sd = VectorUnsignedFixedToFloat(Sd2,32:1,fbits32); + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); } -:vcvt^COND^".f64.s16" Dd,Dd2,fbits16 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & Dd & Dd2 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0 & fbits16 +:vcvt^COND^".f32.s16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorSignedFixedToFloat(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f32.u16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f32.s32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorSignedFixedToFloat(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f32.u32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f64.s16" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 { build COND; build Dd; build Dd2; build fbits16; - Dd = VectorSignedFixedToFloat(Dd2,64:1,fbits16); + Dd = VectorSignedFixedToFloat(Dd2,16:1,fbits16); } -:vcvt^COND^".f64.u16" Dd,Dd2,fbits16 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & Dd & Dd2 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0 & fbits16 +:vcvt^COND^".f64.u16" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 { build COND; build Dd; build Dd2; build fbits16; - Dd = VectorUnsignedFixedToFloat(Dd2,64:1,fbits16); + Dd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16); } -:vcvt^COND^".f64.s32" Dd,Dd2,fbits32 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & Dd & Dd2 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0 & fbits32 +:vcvt^COND^".f64.s32" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 { build COND; build Dd; build Dd2; build fbits32; - Dd = VectorSignedFixedToFloat(Dd2,64:1,fbits32); + Dd = VectorSignedFixedToFloat(Dd2,32:1,fbits32); } -:vcvt^COND^".f64.u32" Dd,Dd2,fbits32 is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & Dd & Dd2 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0 & fbits32 +:vcvt^COND^".f64.u32" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 { build COND; build Dd; build Dd2; build fbits32; - Dd = VectorUnsignedFixedToFloat(Dd2,64:1,fbits32); + Dd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32); } @endif # ! VERSION_8 @@ -1505,7 +2092,8 @@ define pcodeop VectorFloatSingleToDouble; # VCVT (between double-precision and single-precision) # -:vcvt^COND^".f32.f64" Sd,Dm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x37 & Sd & c0911=5 & c0808=1 & c0607=3 & c0404=0 & Dm +:vcvt^COND^".f32.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=1 & c0607=3 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=1 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Sd & Dm { build COND; build Sd; @@ -1513,7 +2101,8 @@ define pcodeop VectorFloatSingleToDouble; Sd = float2float(Dm); } -:vcvt^COND^".f64.f32" Dd,Sm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x37 & Dd & c0911=5 & c0808=0 & c0607=3 & c0404=0 & Sm +:vcvt^COND^".f64.f32" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=0 & c0607=3 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=0 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Dd & Sm { build COND; build Dd; @@ -1527,33 +2116,168 @@ define pcodeop VectorFloatSingleToDouble; @if defined(SIMD) @ifndef VERSION_8 + +define pcodeop VectorFloatSingleToBFloat16; +define pcodeop FloatSingleToBFloat16; + +####### +# VCVT (between single-precision and BFloat16) +# + +:vcvt.bf16.f32 Dd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & Dd & Qm + +{ + Dd = VectorFloatSingleToBFloat16(Qm, 4:1, 16:1); +} + +# VCVTB Convert Single-precision to BFloat16 in Bottom +:vcvtb^COND^".bf16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x25 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local w:2 = FloatSingleToBFloat16(Sm); + Sd[0,16] = w; +} + + +# VCVTT Convert Single-precision to BFloat16 in Top +:vcvtt^COND^".bf16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x27 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x27 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + w:2 = FloatSingleToBFloat16(Sm); + Sd[16,16] = w; +} + define pcodeop VectorFloatSingleToHalf; define pcodeop VectorFloatHalfToSingle; ####### # VCVT (between half-precision and single-precision) # -:vcvt.f16.f32 Dd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & Dd & Qm +:vcvt.f16.f32 Dd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & Dd & Qm { Dd = VectorFloatSingleToHalf(Qm, 4:1, 16:1); } -:vcvt.f16.f32 Qd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=1 & c0607=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & Qd & Dm +:vcvt.f16.f32 Qd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & Qd & Dm { Qd = VectorFloatHalfToSingle(Dm, 4:1, 16:1); } + +define pcodeop VectorFloatToSignedRound; +define pcodeop VectorFloatToUnsignedRound; + +# VCVTA/M/N/P Vector convert floating-point to integer with Rounding +:vcvt^roundType^".s16.f16" Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToSignedRound(Dm, 0:1, roundType); +} + +:vcvt^roundType^".u16.f16" Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToUnsignedRound(Dm, 0:1, roundType); +} + +:vcvt^roundType^".s32.f32" Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToSignedRound(Dm, 1:1, roundType); +} + +:vcvt^roundType^".u32.f32" Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToUnsignedRound(Dm, 1:1, roundType); +} + +:vcvt^roundType^".s16.f16" Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToSignedRound(Qm, 0:1, roundType); +} + +:vcvt^roundType^".u16.f16" Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToUnsignedRound(Qm, 0:1, roundType); +} + +:vcvt^roundType^".s32.f32" Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToSignedRound(Qm, 1:1, roundType); +} + +:vcvt^roundType^".u32.f32" Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToUnsignedRound(Qm, 1:1, roundType); +} @endif # ! VERSION_8 @endif # SIMD @if defined(VFPv3) @ifndef VERSION_8 -:vcvtb^COND^".f32.f16" Sd,Sm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x32 & Sd & c0611=0x29 & c0404=0 & Sm + +define pcodeop FloatToSignedRound; +define pcodeop FloatToUnsignedRound; + +# VCVTA/M/N/P Float convert floating-point to integer with Rounding + +:vcvt^roundType^".s32.f16" Sd,Sm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + local sm16:2 = Sm(0); + Sd = FloatToSignedRound(sm16, roundType); +} + +:vcvt^roundType^".u32.f16" Sd,Sm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + local sm16:2 = Sm(0); + Sd = FloatToUnsignedRound(sm16, roundType); +} + +:vcvt^roundType^".s32.f32" Sd,Sm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + Sd = FloatToSignedRound(Sm, roundType); +} +:vcvt^roundType^".u32.f32" Sd,Sm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + Sd = FloatToUnsignedRound(Sm, roundType); +} + +:vcvt^roundType^".s32.f64" Sd,Dm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Dm +{ + Sd = FloatToSignedRound(Dm, roundType); +} +:vcvt^roundType^".u32.f64" Sd,Dm is ( ( $(AMODE) & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Dm +{ + Sd = FloatToUnsignedRound(Dm, roundType); +} + +# VCVTB Convert Half-precision in Bottom to Single-precision + +:vcvtb^COND^".f32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm { build COND; build Sd; @@ -1561,16 +2285,39 @@ define pcodeop VectorFloatHalfToSingle; Sd = float2float(Sm:2); } -:vcvtb^COND^".f16.f32" Sd,Sm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x33 & Sd & c0611=0x29 & c0404=0 & Sm +:vcvtb^COND^".f16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm { build COND; build Sd; build Sm; - w:2 = float2float(Sm); + local w:2 = float2float(Sm); Sd[0,16] = w; } -:vcvtt^COND^".f32.f16" Sd,Sm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x32 & Sd & c0611=0x2b & c0404=0 & Sm +:vcvtb^COND^".f64.f16" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + Dd = float2float(Sm:2); +} + +:vcvtb^COND^".f16.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Sd & Dm +{ + build COND; + build Sd; + build Dm; + local w:2 = float2float(Dm); + Sd[0,16] = w; +} + +# VCVTT Convert Half-precision in Top to Single-precision + +:vcvtt^COND^".f32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm { build COND; build Sd; @@ -1579,7 +2326,8 @@ define pcodeop VectorFloatHalfToSingle; Sd = float2float(w); } -:vcvtt^COND^".f16.f32" Sd,Sm is $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x33 & Sd & c0611=0x2b & c0404=0 & Sm +:vcvtt^COND^".f16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm { build COND; build Sd; @@ -1587,14 +2335,47 @@ define pcodeop VectorFloatHalfToSingle; w:2 = float2float(Sm); Sd[16,16] = w; } + +:vcvtt^COND^".f64.f16" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + w:2 = Sm(2); + Dd = float2float(w); +} + +:vcvtt^COND^".f16.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Sd & Dm +{ + build COND; + build Sd; + build Dm; + w:2 = float2float(Dm); + Sd[16,16] = w; +} + @endif # ! VERSION_8 @endif # VFPv3 @if defined(VFPv2) || defined(VFPv3) -:vdiv^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0 ) ) & Sn & Sd & Sm +:vdiv^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=9 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build Sn; + local sm16:2 = Sm(0); + local sn16:2 = Sn(0); + Sd = zext(sn16 f/ sm16); +} + +:vdiv^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm { build COND; build Sd; @@ -1603,8 +2384,8 @@ define pcodeop VectorFloatHalfToSingle; Sd = Sn f/ Sm; } -:vdiv^COND^".f64" Dd,Dn,Dm is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0 ) ) & Dn & Dd & Dm +:vdiv^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Dn & Dd & Dm { build COND; build Dd; @@ -1619,9 +2400,46 @@ define pcodeop VectorHalvingAdd; define pcodeop VectorHalvingSubtract; define pcodeop VectorRoundHalvingAdd; define pcodeop VectorRoundAddAndNarrow; +define pcodeop VectorDotProduct; +define pcodeop vectorFusedMultiplyAccumulate; +define pcodeop BfloatMultiplyAccumulate; +define pcodeop VectorMultiplyAddLongVector; +define pcodeop VectorMultiplyAddLongScalar; + @if defined(SIMD) +# F6.1.79 VDOT (vector) page F6-8052 line 467006 +# xfc000d00/mask=xffb00f10 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=111111000.00........1101...0.... + +:vdot.bf16 Dd, Dn, Dm is ( ( $(AMODE) & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Dd +{ + Dd = VectorDotProduct(Dn,Dm); +} + +:vdot.bf16 Qd, Qn, Qm is ( ( $(AMODE) & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm & Qn & Qd +{ + Qd = VectorDotProduct(Qn,Qm); +} + +Mindex: "["^M5^"]" is TMode=0 & M5 { local idx:1 = M5:1; export idx; } +Mindex: "["^thv_M5^"]" is TMode=1 & thv_M5 { local idx:1 = thv_M5:1; export idx; } + +:vdot.bf16 Dd, Dn, Dm0^Mindex is ( ( $(AMODE) & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorDotProduct(Dn,Dm0,Mindex); +} + +:vdot.bf16 Qd, Qn, Qm0^Mindex is ( ( $(AMODE) & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorDotProduct(Qn,Qm0,Mindex); +} + ####### # VDUP (scalar) # @@ -1719,8 +2537,8 @@ vdupRd16: vdupRd8 is vdupRd8 export val; } -:vdup^COND^"."^vdupSize2 Dn,vdupRd8 is COND & (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2121=0 & c2020=0 & c0811=11 & c0606=0 & c0004=0x10) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & Dn & vdupSize2 & vdupRd8 +:vdup^COND^"."^vdupSize2 Dn,vdupRd8 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Dn & vdupSize2 & vdupRd8 { build COND; build vdupRd8; @@ -1728,8 +2546,8 @@ vdupRd16: vdupRd8 is vdupRd8 Dn = vdupRd8; } -:vdup^COND^"."^vdupSize2 Qn,vdupRd16 is COND & (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2121=1 & c2020=0 & c0811=11 & c0606=0 & c0004=0x10) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & Qn & vdupSize2 & vdupRd16 +:vdup^COND^"."^vdupSize2 Qn,vdupRd16 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Qn & vdupSize2 & vdupRd16 { build COND; build vdupRd16; @@ -1753,8 +2571,8 @@ vdupRd16: vdupRd8 is vdupRd8 extImm: "#"^c0811 is TMode=0 & c0811 { tmp:1 = c0811; export tmp; } extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } -:vext.8 Dd,Dn,Dm,extImm is ( ( $(AMODE) & cond=15 & c2327=5 & c2021=3 & c0606=0 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dn & Dm & extImm +:vext.8 Dd,Dn,Dm,extImm is ( ( $(AMODE) & cond=15 & c2327=5 & c2021=3 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dn & Dm & extImm { val:16 = (zext(Dm) << 64) | zext(Dn); local shift = extImm * 8; @@ -1762,8 +2580,8 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } Dd = val:8; } -:vext.8 Qd,Qn,Qm,extImm is ( ( $(AMODE) & cond=15 & c2327=5 & c2021=3 & c0606=1 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qn & Qm & extImm +:vext.8 Qd,Qn,Qm,extImm is ( ( $(AMODE) & cond=15 & c2327=5 & c2021=3 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qn & Qm & extImm { val:32 = (zext(Qm) << 128) | zext(Qn); local shift = extImm * 8; @@ -1771,6 +2589,76 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } Qd = val:16; } +:vfma.f^fesize2021 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=4 & c0811=0xc & c0606=0 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & fesize2021 & Dd & Dn & Dm +{ + Dd = vectorFusedMultiplyAccumulate(Dn, Dm, fesize2021); +} + +:vfma.f^fesize2021 Qd,Qn,Qm is ( ( $(AMODE) & cond=15 & c2327=4 & c0811=0xc & c0606=1 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & fesize2021 & Qd & Qn & Qm +{ + Qd = vectorFusedMultiplyAccumulate(Qn, Qm, fesize2021); +} + + +# Floating-point Multiply-Accumulate BFloat (vector) +:vfmab.BF16 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & Qm +{ + Qd = BfloatMultiplyAccumulate(Qn, Qm, 0:1); +} + +:vfmat.BF16 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & Qm +{ + Qd = BfloatMultiplyAccumulate(Qn, Qm, 1:1); +} + +vmfDm: Dm_3^"["^index^"]" is TMode=0 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } +vmfDm: thv_Dm_3^"["^index^"]" is TMode=1 & thv_Dm_3 & thv_M5 & thv_c0303 [ index = (thv_M5 << 1) + thv_c0303; ] { el:4 = VectorGetElement(thv_Dm_3, index:1, 2:1, 0:1); export el; } +vmfSm: Sm_3^"["^c0303^"]" is TMode=0 & c0404=1 & Sm_3 & M5 & c0303 { el:4 = VectorGetElement(Sm_3, M5:1, 4:1, 0:1); export el; } +vmfSm: Sm_3^"["^c0303^"]" is TMode=1 & thv_c0404=1 & Sm_3 & thv_M5 & c0303 { el:4 = VectorGetElement(Sm_3, thv_M5:1, 4:1, 0:1); export el; } + +:vfmab.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & vmfDm +{ + Qd = BfloatMultiplyAccumulate(Qn, vmfDm, 0:1); +} + +:vfmat.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & vmfDm +{ + Qd = BfloatMultiplyAccumulate(Qn, vmfDm, 1:1); +} + +:vfmal.F16 Dd,Sn,Sm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & Sm +{ + Dd = VectorMultiplyAddLongVector(Sn, Sm, 0:1); +} + +:vfmal.F16 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & Dm +{ + Qd = VectorMultiplyAddLongVector(Dn, Dm, 1:1); +} + +:vfmal.F16 Dd,Sn,vmfSm is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & vmfSm +{ + Dd = VectorMultiplyAddLongScalar(Sn, vmfSm, 0:1); +} + +:vfmal.F16 Qd,Dn,vmfDm is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & vmfDm +{ + Qd = VectorMultiplyAddLongScalar(Dn, vmfDm, 1:1); +} + + + + :vhadd.^udt^esize2021 Dd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=0 & Q6=0 & c0404=0) | ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=0 & thv_Q6=0 & thv_c0404=0) ) & udt & Dm & esize2021 & Dn & Dd { @@ -2554,16 +3442,16 @@ buildVldmDdList: Dreg,buildVldmDdList is Dreg & buildVldmDdList [ counter=counte vldmDdList: "{"^buildVldmDdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVldmDdList [ regNum=(D22<<4)+c1215 - 1; counter=c0007>>1; ] { } vldmDdList: "{"^buildVldmDdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmDdList [ regNum=(thv_D22<<4)+thv_c1215 - 1; counter=thv_c0007>>1; ] { } -:vldmia^COND vldmRn,vldmDdList is ( ($(AMODE) & COND & c2327=0x19 & c2121 & c2020=1 & c0811=11 & c0000=0) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & vldmRn & vldmDdList & vldmOffset & vldmUpdate +:vldmia^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x19 & c2121 & c2020=1 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & COND & vldmRn & vldmDdList & vldmOffset & vldmUpdate { mult_addr = vldmRn; build vldmDdList; build vldmUpdate; } -:vldmdb^COND vldmRn,vldmDdList is ( ($(AMODE) & COND & c2327=0x1a & c2121=1 & c2020=1 & c0811=11 & c0000=0) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0 ) ) & vldmRn & vldmDdList & vldmOffset +:vldmdb^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x1a & c2121=1 & c2020=1 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0 ) ) & COND & vldmRn & vldmDdList & vldmOffset { local start_addr = vldmRn - vldmOffset; mult_addr = start_addr; @@ -2575,56 +3463,218 @@ vldmDdList: "{"^buildVldmDdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 @if defined(VERSION_8) -fldmSet1: thv_Dd_1 is TMode=1 & thv_Rn & thv_Dd_1 { thv_Dd_1 = * thv_Rn; } -fldmSet2: thv_Dd_2 is TMode=1 & thv_Rn & thv_Dd_2 & fldmSet1 { build fldmSet1; thv_Dd_2 = *:8 (thv_Rn + 8:4); } -fldmSet3: thv_Dd_3 is TMode=1 & thv_Rn & thv_Dd_3 & fldmSet2 { build fldmSet2; thv_Dd_3 = *:8 (thv_Rn + 16:4); } -fldmSet4: thv_Dd_4 is TMode=1 & thv_Rn & thv_Dd_4 & fldmSet3 { build fldmSet3; thv_Dd_4 = *:8 (thv_Rn + 24:4); } -fldmSet5: thv_Dd_5 is TMode=1 & thv_Rn & thv_Dd_5 & fldmSet4 { build fldmSet4; thv_Dd_5 = *:8 (thv_Rn + 32:4); } -fldmSet6: thv_Dd_6 is TMode=1 & thv_Rn & thv_Dd_6 & fldmSet5 { build fldmSet5; thv_Dd_6 = *:8 (thv_Rn + 40:4); } -fldmSet7: thv_Dd_7 is TMode=1 & thv_Rn & thv_Dd_7 & fldmSet6 { build fldmSet6; thv_Dd_7 = *:8 (thv_Rn + 48:4); } -fldmSet8: thv_Dd_8 is TMode=1 & thv_Rn & thv_Dd_8 & fldmSet7 { build fldmSet7; thv_Dd_8 = *:8 (thv_Rn + 56:4); } -fldmSet9: thv_Dd_9 is TMode=1 & thv_Rn & thv_Dd_9 & fldmSet8 { build fldmSet8; thv_Dd_9 = *:8 (thv_Rn + 64:4); } -fldmSet10: thv_Dd_10 is TMode=1 & thv_Rn & thv_Dd_10 & fldmSet9 { build fldmSet9; thv_Dd_10 = *:8 (thv_Rn + 72:4); } -fldmSet11: thv_Dd_11 is TMode=1 & thv_Rn & thv_Dd_11 & fldmSet10 { build fldmSet10; thv_Dd_11 = *:8 (thv_Rn + 80:4); } -fldmSet12: thv_Dd_12 is TMode=1 & thv_Rn & thv_Dd_12 & fldmSet11 { build fldmSet11; thv_Dd_12 = *:8 (thv_Rn + 88:4); } -fldmSet13: thv_Dd_13 is TMode=1 & thv_Rn & thv_Dd_13 & fldmSet12 { build fldmSet12; thv_Dd_13 = *:8 (thv_Rn + 96:4); } -fldmSet14: thv_Dd_14 is TMode=1 & thv_Rn & thv_Dd_14 & fldmSet13 { build fldmSet13; thv_Dd_14 = *:8 (thv_Rn + 104:4); } -fldmSet15: thv_Dd_15 is TMode=1 & thv_Rn & thv_Dd_15 & fldmSet14 { build fldmSet14; thv_Dd_15 = *:8 (thv_Rn + 112:4); } -fldmSet16: thv_Dd_16 is TMode=1 & thv_Rn & thv_Dd_16 & fldmSet15 { build fldmSet15; thv_Dd_16 = *:8 (thv_Rn + 120:4); } +with : TMode=0 { +fldmSet1: Dd_1 is Rn & Dd_1 { Dd_1 = * Rn; } +fldmSet2: Dd_2 is Rn & Dd_2 & fldmSet1 { build fldmSet1; Dd_2 = *:8 (Rn + 8:4); } +fldmSet3: Dd_3 is Rn & Dd_3 & fldmSet2 { build fldmSet2; Dd_3 = *:8 (Rn + 16:4); } +fldmSet4: Dd_4 is Rn & Dd_4 & fldmSet3 { build fldmSet3; Dd_4 = *:8 (Rn + 24:4); } +fldmSet5: Dd_5 is Rn & Dd_5 & fldmSet4 { build fldmSet4; Dd_5 = *:8 (Rn + 32:4); } +fldmSet6: Dd_6 is Rn & Dd_6 & fldmSet5 { build fldmSet5; Dd_6 = *:8 (Rn + 40:4); } +fldmSet7: Dd_7 is Rn & Dd_7 & fldmSet6 { build fldmSet6; Dd_7 = *:8 (Rn + 48:4); } +fldmSet8: Dd_8 is Rn & Dd_8 & fldmSet7 { build fldmSet7; Dd_8 = *:8 (Rn + 56:4); } +fldmSet9: Dd_9 is Rn & Dd_9 & fldmSet8 { build fldmSet8; Dd_9 = *:8 (Rn + 64:4); } +fldmSet10: Dd_10 is Rn & Dd_10 & fldmSet9 { build fldmSet9; Dd_10 = *:8 (Rn + 72:4); } +fldmSet11: Dd_11 is Rn & Dd_11 & fldmSet10 { build fldmSet10; Dd_11 = *:8 (Rn + 80:4); } +fldmSet12: Dd_12 is Rn & Dd_12 & fldmSet11 { build fldmSet11; Dd_12 = *:8 (Rn + 88:4); } +fldmSet13: Dd_13 is Rn & Dd_13 & fldmSet12 { build fldmSet12; Dd_13 = *:8 (Rn + 96:4); } +fldmSet14: Dd_14 is Rn & Dd_14 & fldmSet13 { build fldmSet13; Dd_14 = *:8 (Rn + 104:4); } +fldmSet15: Dd_15 is Rn & Dd_15 & fldmSet14 { build fldmSet14; Dd_15 = *:8 (Rn + 112:4); } +fldmSet16: Dd_16 is Rn & Dd_16 & fldmSet15 { build fldmSet15; Dd_16 = *:8 (Rn + 120:4); } + +fldmSet: "{"^Dd_1^"}" is Dd_1 & c0007=3 & fldmSet1 { build fldmSet1; } +fldmSet: "{"^Dd_1^"-"^fldmSet2^"}" is Dd_1 & c0007=5 & fldmSet2 { build fldmSet2; } +fldmSet: "{"^Dd_1^"-"^fldmSet3^"}" is Dd_1 & c0007=7 & fldmSet3 { build fldmSet3; } +fldmSet: "{"^Dd_1^"-"^fldmSet4^"}" is Dd_1 & c0007=9 & fldmSet4 { build fldmSet4; } +fldmSet: "{"^Dd_1^"-"^fldmSet5^"}" is Dd_1 & c0007=11 & fldmSet5 { build fldmSet5; } +fldmSet: "{"^Dd_1^"-"^fldmSet6^"}" is Dd_1 & c0007=13 & fldmSet6 { build fldmSet6; } +fldmSet: "{"^Dd_1^"-"^fldmSet7^"}" is Dd_1 & c0007=15 & fldmSet7 { build fldmSet7; } +fldmSet: "{"^Dd_1^"-"^fldmSet8^"}" is Dd_1 & c0007=17 & fldmSet8 { build fldmSet8; } +fldmSet: "{"^Dd_1^"-"^fldmSet9^"}" is Dd_1 & c0007=19 & fldmSet9 { build fldmSet9; } +fldmSet: "{"^Dd_1^"-"^fldmSet10^"}" is Dd_1 & c0007=21 & fldmSet10 { build fldmSet10; } +fldmSet: "{"^Dd_1^"-"^fldmSet11^"}" is Dd_1 & c0007=23 & fldmSet11 { build fldmSet11; } +fldmSet: "{"^Dd_1^"-"^fldmSet12^"}" is Dd_1 & c0007=25 & fldmSet12 { build fldmSet12; } +fldmSet: "{"^Dd_1^"-"^fldmSet13^"}" is Dd_1 & c0007=27 & fldmSet13 { build fldmSet13; } +fldmSet: "{"^Dd_1^"-"^fldmSet14^"}" is Dd_1 & c0007=29 & fldmSet14 { build fldmSet14; } +fldmSet: "{"^Dd_1^"-"^fldmSet15^"}" is Dd_1 & c0007=31 & fldmSet15 { build fldmSet15; } +fldmSet: "{"^Dd_1^"-"^fldmSet16^"}" is Dd_1 & c0007=33 & fldmSet16 { build fldmSet16; } + + +fldmWback: Rn^"!" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); } +fldmWback: Rn^"!" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); } +fldmWback: Rn is c2121=0 & Rn { } +} + +with : TMode=1 { +fldmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { thv_Dd_1 = * thv_Rn; } +fldmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fldmSet1 { build fldmSet1; thv_Dd_2 = *:8 (thv_Rn + 8:4); } +fldmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fldmSet2 { build fldmSet2; thv_Dd_3 = *:8 (thv_Rn + 16:4); } +fldmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fldmSet3 { build fldmSet3; thv_Dd_4 = *:8 (thv_Rn + 24:4); } +fldmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fldmSet4 { build fldmSet4; thv_Dd_5 = *:8 (thv_Rn + 32:4); } +fldmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fldmSet5 { build fldmSet5; thv_Dd_6 = *:8 (thv_Rn + 40:4); } +fldmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fldmSet6 { build fldmSet6; thv_Dd_7 = *:8 (thv_Rn + 48:4); } +fldmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fldmSet7 { build fldmSet7; thv_Dd_8 = *:8 (thv_Rn + 56:4); } +fldmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fldmSet8 { build fldmSet8; thv_Dd_9 = *:8 (thv_Rn + 64:4); } +fldmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fldmSet9 { build fldmSet9; thv_Dd_10 = *:8 (thv_Rn + 72:4); } +fldmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fldmSet10 { build fldmSet10; thv_Dd_11 = *:8 (thv_Rn + 80:4); } +fldmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fldmSet11 { build fldmSet11; thv_Dd_12 = *:8 (thv_Rn + 88:4); } +fldmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fldmSet12 { build fldmSet12; thv_Dd_13 = *:8 (thv_Rn + 96:4); } +fldmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fldmSet13 { build fldmSet13; thv_Dd_14 = *:8 (thv_Rn + 104:4); } +fldmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fldmSet14 { build fldmSet14; thv_Dd_15 = *:8 (thv_Rn + 112:4); } +fldmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fldmSet15 { build fldmSet15; thv_Dd_16 = *:8 (thv_Rn + 120:4); } + +fldmSet: "{"^thv_Dd_1^"}" is thv_Dd_1 & thv_c0007=3 & fldmSet1 { build fldmSet1; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet2^"}" is thv_Dd_1 & thv_c0007=5 & fldmSet2 { build fldmSet2; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet3^"}" is thv_Dd_1 & thv_c0007=7 & fldmSet3 { build fldmSet3; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet4^"}" is thv_Dd_1 & thv_c0007=9 & fldmSet4 { build fldmSet4; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet5^"}" is thv_Dd_1 & thv_c0007=11 & fldmSet5 { build fldmSet5; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet6^"}" is thv_Dd_1 & thv_c0007=13 & fldmSet6 { build fldmSet6; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet7^"}" is thv_Dd_1 & thv_c0007=15 & fldmSet7 { build fldmSet7; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet8^"}" is thv_Dd_1 & thv_c0007=17 & fldmSet8 { build fldmSet8; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet9^"}" is thv_Dd_1 & thv_c0007=19 & fldmSet9 { build fldmSet9; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet10^"}" is thv_Dd_1 & thv_c0007=21 & fldmSet10 { build fldmSet10; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet11^"}" is thv_Dd_1 & thv_c0007=23 & fldmSet11 { build fldmSet11; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet12^"}" is thv_Dd_1 & thv_c0007=25 & fldmSet12 { build fldmSet12; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet13^"}" is thv_Dd_1 & thv_c0007=27 & fldmSet13 { build fldmSet13; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet14^"}" is thv_Dd_1 & thv_c0007=29 & fldmSet14 { build fldmSet14; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet15^"}" is thv_Dd_1 & thv_c0007=31 & fldmSet15 { build fldmSet15; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet16^"}" is thv_Dd_1 & thv_c0007=33 & fldmSet16 { build fldmSet16; } -fldmSet: "{"^thv_Dd_1^"}" is TMode=1 & thv_Dd_1 & thv_c0007=3 & fldmSet1 { build fldmSet1; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet2^"}" is TMode=1 & thv_Dd_1 & thv_c0007=5 & fldmSet2 { build fldmSet2; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet3^"}" is TMode=1 & thv_Dd_1 & thv_c0007=7 & fldmSet3 { build fldmSet3; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet4^"}" is TMode=1 & thv_Dd_1 & thv_c0007=9 & fldmSet4 { build fldmSet4; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet5^"}" is TMode=1 & thv_Dd_1 & thv_c0007=11 & fldmSet5 { build fldmSet5; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet6^"}" is TMode=1 & thv_Dd_1 & thv_c0007=13 & fldmSet6 { build fldmSet6; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet7^"}" is TMode=1 & thv_Dd_1 & thv_c0007=15 & fldmSet7 { build fldmSet7; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet8^"}" is TMode=1 & thv_Dd_1 & thv_c0007=17 & fldmSet8 { build fldmSet8; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet9^"}" is TMode=1 & thv_Dd_1 & thv_c0007=19 & fldmSet9 { build fldmSet9; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet10^"}" is TMode=1 & thv_Dd_1 & thv_c0007=21 & fldmSet10 { build fldmSet10; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet11^"}" is TMode=1 & thv_Dd_1 & thv_c0007=23 & fldmSet11 { build fldmSet11; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet12^"}" is TMode=1 & thv_Dd_1 & thv_c0007=25 & fldmSet12 { build fldmSet12; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet13^"}" is TMode=1 & thv_Dd_1 & thv_c0007=27 & fldmSet13 { build fldmSet13; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet14^"}" is TMode=1 & thv_Dd_1 & thv_c0007=29 & fldmSet14 { build fldmSet14; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet15^"}" is TMode=1 & thv_Dd_1 & thv_c0007=31 & fldmSet15 { build fldmSet15; } -fldmSet: "{"^thv_Dd_1^"-"^fldmSet16^"}" is TMode=1 & thv_Dd_1 & thv_c0007=33 & fldmSet16 { build fldmSet16; } fldmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); } fldmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); } fldmWback: thv_Rn is thv_bit21=0 & thv_Rn { } +} -:fldmdbx^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0b111011010 & thv_bit21=1 & thv_bit20=1 & thv_c0811=0b1011 & fldmWback & fldmSet +:fldmdbx^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=3 & c0811=0xb & c0000=1 & fldmWback & fldmSet { build fldmWback; build fldmSet; } -:fldmiax^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0b111011001 & thv_bit20=1 & thv_c0811=0b1011 & fldmWback & fldmSet +:fldmiax^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=0xb & c0000=1 & fldmWback & fldmSet { build fldmSet; build fldmWback; } +:fldmdbx^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=3 & thv_c0811=0xb & fldmWback & fldmSet +{ + build fldmWback; + build fldmSet; +} + +:fldmiax^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=1 & thv_c0811=0xb & fldmWback & fldmSet +{ + build fldmSet; + build fldmWback; +} + +with : TMode=0 { +fstmSet1: Dd_1 is Rn & Dd_1 { * Rn = Dd_1; } +fstmSet2: Dd_2 is Rn & Dd_2 & fstmSet1 { build fstmSet1; *:8 (Rn + 8:4) = Dd_2; } +fstmSet3: Dd_3 is Rn & Dd_3 & fstmSet2 { build fstmSet2; *:8 (Rn + 16:4) = Dd_3; } +fstmSet4: Dd_4 is Rn & Dd_4 & fstmSet3 { build fstmSet3; *:8 (Rn + 24:4) = Dd_4; } +fstmSet5: Dd_5 is Rn & Dd_5 & fstmSet4 { build fstmSet4; *:8 (Rn + 32:4) = Dd_5; } +fstmSet6: Dd_6 is Rn & Dd_6 & fstmSet5 { build fstmSet5; *:8 (Rn + 40:4) = Dd_6; } +fstmSet7: Dd_7 is Rn & Dd_7 & fstmSet6 { build fstmSet6; *:8 (Rn + 48:4) = Dd_7; } +fstmSet8: Dd_8 is Rn & Dd_8 & fstmSet7 { build fstmSet7; *:8 (Rn + 56:4) = Dd_8; } +fstmSet9: Dd_9 is Rn & Dd_9 & fstmSet8 { build fstmSet8; *:8 (Rn + 64:4) = Dd_9; } +fstmSet10: Dd_10 is Rn & Dd_10 & fstmSet9 { build fstmSet9; *:8 (Rn + 72:4) = Dd_10; } +fstmSet11: Dd_11 is Rn & Dd_11 & fstmSet10 { build fstmSet10; *:8 (Rn + 80:4) = Dd_11; } +fstmSet12: Dd_12 is Rn & Dd_12 & fstmSet11 { build fstmSet11; *:8 (Rn + 88:4) = Dd_12; } +fstmSet13: Dd_13 is Rn & Dd_13 & fstmSet12 { build fstmSet12; *:8 (Rn + 96:4) = Dd_13; } +fstmSet14: Dd_14 is Rn & Dd_14 & fstmSet13 { build fstmSet13; *:8 (Rn + 104:4) = Dd_14; } +fstmSet15: Dd_15 is Rn & Dd_15 & fstmSet14 { build fstmSet14; *:8 (Rn + 112:4) = Dd_15; } +fstmSet16: Dd_16 is Rn & Dd_16 & fstmSet15 { build fstmSet15; *:8 (Rn + 120:4) = Dd_16; } + +fstmSet: "{"^Dd_1^"}" is Dd_1 & c0007=3 & fstmSet1 { build fstmSet1; } +fstmSet: "{"^Dd_1^"-"^fstmSet2^"}" is Dd_1 & c0007=5 & fstmSet2 { build fstmSet2; } +fstmSet: "{"^Dd_1^"-"^fstmSet3^"}" is Dd_1 & c0007=7 & fstmSet3 { build fstmSet3; } +fstmSet: "{"^Dd_1^"-"^fstmSet4^"}" is Dd_1 & c0007=9 & fstmSet4 { build fstmSet4; } +fstmSet: "{"^Dd_1^"-"^fstmSet5^"}" is Dd_1 & c0007=11 & fstmSet5 { build fstmSet5; } +fstmSet: "{"^Dd_1^"-"^fstmSet6^"}" is Dd_1 & c0007=13 & fstmSet6 { build fstmSet6; } +fstmSet: "{"^Dd_1^"-"^fstmSet7^"}" is Dd_1 & c0007=15 & fstmSet7 { build fstmSet7; } +fstmSet: "{"^Dd_1^"-"^fstmSet8^"}" is Dd_1 & c0007=17 & fstmSet8 { build fstmSet8; } +fstmSet: "{"^Dd_1^"-"^fstmSet9^"}" is Dd_1 & c0007=19 & fstmSet9 { build fstmSet9; } +fstmSet: "{"^Dd_1^"-"^fstmSet10^"}" is Dd_1 & c0007=21 & fstmSet10 { build fstmSet10; } +fstmSet: "{"^Dd_1^"-"^fstmSet11^"}" is Dd_1 & c0007=23 & fstmSet11 { build fstmSet11; } +fstmSet: "{"^Dd_1^"-"^fstmSet12^"}" is Dd_1 & c0007=25 & fstmSet12 { build fstmSet12; } +fstmSet: "{"^Dd_1^"-"^fstmSet13^"}" is Dd_1 & c0007=27 & fstmSet13 { build fstmSet13; } +fstmSet: "{"^Dd_1^"-"^fstmSet14^"}" is Dd_1 & c0007=29 & fstmSet14 { build fstmSet14; } +fstmSet: "{"^Dd_1^"-"^fstmSet15^"}" is Dd_1 & c0007=31 & fstmSet15 { build fstmSet15; } +fstmSet: "{"^Dd_1^"-"^fstmSet16^"}" is Dd_1 & c0007=33 & fstmSet16 { build fstmSet16; } + + +fstmWback: Rn^"!" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); } +fstmWback: Rn^"!" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); } +fstmWback: Rn is c2121=0 & Rn { } +} + +with : TMode=1 { +fstmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { * thv_Rn = thv_Dd_1; } +fstmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fstmSet1 { build fstmSet1; *:8 (thv_Rn + 8:4) = thv_Dd_2; } +fstmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fstmSet2 { build fstmSet2; *:8 (thv_Rn + 16:4) = thv_Dd_3; } +fstmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fstmSet3 { build fstmSet3; *:8 (thv_Rn + 24:4) = thv_Dd_4; } +fstmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fstmSet4 { build fstmSet4; *:8 (thv_Rn + 32:4) = thv_Dd_5; } +fstmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fstmSet5 { build fstmSet5; *:8 (thv_Rn + 40:4) = thv_Dd_6; } +fstmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fstmSet6 { build fstmSet6; *:8 (thv_Rn + 48:4) = thv_Dd_7; } +fstmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fstmSet7 { build fstmSet7; *:8 (thv_Rn + 56:4) = thv_Dd_8; } +fstmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fstmSet8 { build fstmSet8; *:8 (thv_Rn + 64:4) = thv_Dd_9; } +fstmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fstmSet9 { build fstmSet9; *:8 (thv_Rn + 72:4) = thv_Dd_10; } +fstmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fstmSet10 { build fstmSet10; *:8 (thv_Rn + 80:4) = thv_Dd_11; } +fstmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fstmSet11 { build fstmSet11; *:8 (thv_Rn + 88:4) = thv_Dd_12; } +fstmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fstmSet12 { build fstmSet12; *:8 (thv_Rn + 96:4) = thv_Dd_13; } +fstmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fstmSet13 { build fstmSet13; *:8 (thv_Rn + 104:4) = thv_Dd_14; } +fstmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fstmSet14 { build fstmSet14; *:8 (thv_Rn + 112:4) = thv_Dd_15; } +fstmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fstmSet15 { build fstmSet15; *:8 (thv_Rn + 120:4) = thv_Dd_16; } + +fstmSet: "{"^thv_Dd_1^"}" is thv_Dd_1 & thv_c0007=3 & fstmSet1 { build fstmSet1; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet2^"}" is thv_Dd_1 & thv_c0007=5 & fstmSet2 { build fstmSet2; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet3^"}" is thv_Dd_1 & thv_c0007=7 & fstmSet3 { build fstmSet3; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet4^"}" is thv_Dd_1 & thv_c0007=9 & fstmSet4 { build fstmSet4; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet5^"}" is thv_Dd_1 & thv_c0007=11 & fstmSet5 { build fstmSet5; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet6^"}" is thv_Dd_1 & thv_c0007=13 & fstmSet6 { build fstmSet6; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet7^"}" is thv_Dd_1 & thv_c0007=15 & fstmSet7 { build fstmSet7; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet8^"}" is thv_Dd_1 & thv_c0007=17 & fstmSet8 { build fstmSet8; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet9^"}" is thv_Dd_1 & thv_c0007=19 & fstmSet9 { build fstmSet9; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet10^"}" is thv_Dd_1 & thv_c0007=21 & fstmSet10 { build fstmSet10; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet11^"}" is thv_Dd_1 & thv_c0007=23 & fstmSet11 { build fstmSet11; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet12^"}" is thv_Dd_1 & thv_c0007=25 & fstmSet12 { build fstmSet12; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet13^"}" is thv_Dd_1 & thv_c0007=27 & fstmSet13 { build fstmSet13; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet14^"}" is thv_Dd_1 & thv_c0007=29 & fstmSet14 { build fstmSet14; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet15^"}" is thv_Dd_1 & thv_c0007=31 & fstmSet15 { build fstmSet15; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet16^"}" is thv_Dd_1 & thv_c0007=33 & fstmSet16 { build fstmSet16; } + + +fstmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); } +fstmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); } +fstmWback: thv_Rn is thv_bit21=0 & thv_Rn { } +} + +:fstmdbx^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=2 & c0811=0xb & c0000=1 & fstmWback & fstmSet +{ + build fstmWback; + build fstmSet; +} + +:fstmiax^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=0 & c0811=0xb & c0000=1 & fstmWback & fstmSet +{ + build fstmSet; + build fstmWback; +} + +:fstmdbx^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=2 & thv_c0811=0xb & fstmWback & fstmSet +{ + build fstmWback; + build fstmSet; +} + +:fstmiax^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=0 & thv_c0811=0xb & fstmWback & fstmSet +{ + build fstmSet; + build fstmWback; +} + @endif @if defined(VFPv2) || defined(VFPv3) @@ -2649,16 +3699,16 @@ buildVldmSdList: Sreg,buildVldmSdList is Sreg & buildVldmSdList [ counter=counte vldmSdList: "{"^buildVldmSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVldmSdList [ regNum=(c1215<<1) + D22 - 1; counter=c0007; ] { } vldmSdList: "{"^buildVldmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmSdList [ regNum=(thv_c1215<<1) + thv_D22 - 1; counter=thv_c0007; ] { } -:vldmia^COND vldmRn,vldmSdList is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x19 & c2121 & c2020=1 & c0811=10 ) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=10 ) ) & vldmRn & vldmSdList & vldmOffset & vldmUpdate +:vldmia^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset & vldmUpdate { mult_addr = vldmRn; build vldmSdList; build vldmUpdate; } -:vldmdb^COND vldmRn,vldmSdList is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=1 & c0811=10 ) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=10 ) ) & vldmRn & vldmSdList & vldmOffset +:vldmdb^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=1 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset { local start_addr = vldmRn - vldmOffset; mult_addr = start_addr; @@ -2709,7 +3759,6 @@ define pcodeop VectorDoubleMultiplyAccumulateLong; define pcodeop VectorDoubleMultiplySubtractLong; define pcodeop FloatVectorMultiplyAccumulate; define pcodeop FloatVectorMultiplySubtract; -define pcodeop VectorGetElement; @if defined(SIMD) @@ -2827,26 +3876,26 @@ define pcodeop VectorGetElement; @if defined(VFPv2) || defined(VFPv3) -:vmla^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +:vmla^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & COND & Sm & Sn & Sd { Sd = Sd f+ (Sn f* Sm); } -:vmla^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd +:vmla^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & COND & Dm & Dn & Dd { Dd = Dd f+ (Dn f* Dm); } -:vmls^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +:vmls^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & COND & Sm & Sn & Sd { Sd = Sd f- (Sn f* Sm); } -:vmls^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=1 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd +:vmls^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & COND & Dm & Dn & Dd { Dd = Dd f- (Dn f* Dm); } @@ -2866,49 +3915,49 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 :vmla.i^esize2021 Dd,Dn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm { Dd = VectorMultiplyAccumulate(Dn,vmlDm,esize2021); } :vmla.i^esize2021 Qd,Qn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm { Qd = VectorMultiplyAccumulate(Qn,vmlDm,esize2021); } :vmla.f32 Dd,Dn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm { Dd = FloatVectorMultiplyAccumulate(Dn,vmlDm,2:4,32:1); } :vmla.f32 Qd,Qn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm { Qd = FloatVectorMultiplyAccumulate(Qn,vmlDm,2:4,32:1); } :vmls.i^esize2021 Dd,Dn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=4 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm { Dd = VectorMultiplySubtract(Dn,vmlDm,esize2021); } :vmls.i^esize2021 Qd,Qn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2)& c0811=4 & c0606=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm { Qd = VectorMultiplySubtract(Qn,vmlDm,esize2021); } :vmls.f32 Dd,Dn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm { Dd = FloatVectorMultiplySubtract(Dn,vmlDm,2:4,32:1); } :vmls.f32 Qd,Qn,vmlDm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm { Qd = FloatVectorMultiplySubtract(Qn,vmlDm,2:4,32:1); } @@ -2947,15 +3996,17 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 @if defined(VFPv3) -:vmov^COND^".f32" Sd,vfpExpImm_4 is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & Sd & vfpExpImm_4 +:vmov^COND^".f32" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & COND & Sd & vfpExpImm_4 { + build COND; Sd = vfpExpImm_4; } -:vmov^COND^".f64" Dd,vfpExpImm_8 is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & Dd & vfpExpImm_8 +:vmov^COND^".f64" Dd,vfpExpImm_8 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & COND & Dd & vfpExpImm_8 { + build COND; Dd = vfpExpImm_8; } @@ -2979,14 +4030,14 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 @if defined(VFPv2) || defined(VFPv3) -:vmov^COND^".f32" Sd,Sm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x29 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x29 & thv_c0404=0) ) & Sd & Sm +:vmov^COND^".f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x29 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x29 & thv_c0404=0) ) & COND & Sd & Sm { Sd = Sm; } -:vmov^COND^".f64" Dd,Dm is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2d & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2d & thv_c0404=0) ) & Dd & Dm +:vmov^COND^".f64" Dd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2d & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2d & thv_c0404=0) ) & COND & Dd & Dm { Dd = Dm; } @@ -2997,28 +4048,16 @@ define pcodeop VectorSetElement; @if defined(SIMD) -vmovSize: 8 is TMode=0 & c2222=1 { export 1:1; } -vmovSize: 16 is TMode=0 & c2222=0 & c0505=1 { export 2:1; } -vmovSize: 8 is TMode=1 & thv_c2222=1 { export 1:1; } -vmovSize: 16 is TMode=1 & thv_c2222=0 & thv_c0505=1 { export 2:1; } - -@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) - -vmovSize: 32 is TMode=0 & c2222=0 & c0506=0 { export 4:1; } -vmovSize: 32 is TMode=1 & thv_c2222=0 & thv_c0506=0 { export 4:1; } - -@endif # VFPv2 || VFPv3 || SIMD - vmovIndex: val is TMode=0 & c2222=1 & c2121 & c0506 [ val = (c2121 << 2) + c0506; ] { tmp:1 = val; export tmp; } -vmovIndex: val is TMode=0 & c2222=0 & c2121 & c0606 & c0505=1 [ val = (c2121 << 1) + c0606; ] { tmp:1 = val; export tmp; } +vmovIndex: val is TMode=0 & c2222=1 & c2121 & c0606 & c0505=1 [ val = (c2121 << 2) + c0606; ] { tmp:1 = val; export tmp; } vmovIndex: val is TMode=1 & thv_c2222=1 & thv_c2121 & thv_c0506 [ val = (thv_c2121 << 2) + thv_c0506; ] { tmp:1 = val; export tmp; } -vmovIndex: val is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0606 & thv_c0505=1 [ val = (thv_c2121 << 1) + thv_c0606; ] { tmp:1 = val; export tmp; } +vmovIndex: val is TMode=1 & thv_c2222=1 & thv_c2121 & thv_c0606 & thv_c0505=1 [ val = (thv_c2121 << 2) + thv_c0606; ] { tmp:1 = val; export tmp; } @if defined(VFPv2) || defined(VFPv3) || defined(SIMD) -vmovIndex: c2121 is TMode=0 & c2222=0 & c2121 & c0606=0 & c0506=0 { tmp:1 = c2121; export tmp; } -vmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0606=0 & thv_c0506=0 { tmp:1 = thv_c2121; export tmp; } +vmovIndex: c2121 is TMode=0 & c2222=0 & c2121 & c0506=0 { tmp:1 = c2121; export tmp; } +vmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0506=0 { tmp:1 = thv_c2121; export tmp; } @endif # VFPv2 || VFPv3 || SIMD @@ -3026,22 +4065,87 @@ vmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0606=0 & thv_c0 dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } -:vmov^COND^"."^vmovSize dNvmovIndex,VRd is ( ($(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2020=0 & c0811=11 & c0404=1 & c0003=0 ) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2020=0 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & Dn & VRd & vmovSize & vmovIndex & dNvmovIndex +:vmov^COND^".8" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=0 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=0 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex { - VectorSetElement(VRd,Dn,vmovIndex,vmovSize); + el:1 = VRd(0); + vmask:8 = 0xf << (vmovIndex*8); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex); } -:vmov^COND^".u"^vmovSize VRd,dNvmovIndex is ( ($(AMODE) & COND & ARMcond=1 & c2327=0x1d & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & Dn & VRd & vmovSize & vmovIndex & dNvmovIndex +:vmov^COND^".16" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex { - VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); + el:2 = VRd(0); + vmask:8 = 0xff << (vmovIndex*16); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex,vmovSize); } -:vmov^COND^".s"^vmovSize VRd,dNvmovIndex is ( ( $(AMODE) & COND & ARMcond=1 & c2327=0x1c & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & Dn & VRd & vmovSize & vmovIndex & dNvmovIndex + +:vmov^COND^".32" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex { - VRd = VectorGetElement(Dn,vmovIndex,vmovSize,1:1); + el:4 = VRd; + vmask:8 = 0xffff << (vmovIndex*32); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex,vmovSize); +} + + +:vmov^COND^".u8" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*8); + result:1 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".u16" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*16); + result:2 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".u32" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*32); + result:4 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s8" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*8); + result:1 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s16" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*16); + result:2 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s32" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*32); + result:4 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); } @endif # SIMD @@ -3049,27 +4153,27 @@ dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } @if defined(VFPv2) || defined(VFPv3) -:vmov^COND Sn,VRd is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=0 & c0811=10 & c0006=0x10) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=0 & thv_c0811=10 & thv_c0006=0x10) ) & Sn & VRd +:vmov^COND Sn,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=0 & c0811=10 & c0006=0x10) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=0 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd { Sn = VRd; } -:vmov^COND VRd,Sn is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=1 & c0811=10 & c0006=0x10) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=1 & thv_c0811=10 & thv_c0006=0x10) ) & Sn & VRd +:vmov^COND VRd,Sn is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=1 & c0811=10 & c0006=0x10) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=1 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd { VRd = Sn; } -:vmov^COND Sm,SmNext,VRd,VRn is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x28 & c0404=1) | - ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x28 & thv_c0404=1) ) & VRn & VRd & Sm & SmNext +:vmov^COND Sm,SmNext,VRd,VRn is ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x28 & c0404=1) | + ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext { Sm = VRd; SmNext = VRn; } -:vmov^COND VRd,VRn,Sm,SmNext is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x28 & c0404=1) | - ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x28 & thv_c0404=1) ) & VRn & VRd & Sm & SmNext +:vmov^COND VRd,VRn,Sm,SmNext is ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x28 & c0404=1) | + ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext { VRd = Sm; VRn = SmNext; @@ -3097,29 +4201,40 @@ define pcodeop VectorCopyNarrow; @if defined(SIMD) -:vmovl.^udt^esize2021 Qd,Dm is $(AMODE) & cond=15 & c2527=1 & udt & c2323=1 & (c1921=1 | c1921=2 | c1921=4) & esize2021 & c1618=0 & Qd & c0611=0x28 & c0404=1 & Dm +:vmovl.^udt^esize2021 Qd,Dm is (($(AMODE) & cond=15 & c2527=1 & c2323=1 & (c1921=1 | c1921=2 | c1921=4) & c1618=0 & c0611=0x28 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1921=1 | thv_c1921=2 | thv_c1921=4) & thv_c1618=0 & thv_c0611=0x28 & thv_c0404=1) ) & esize2021 & udt & Qd & Dm { Qd = VectorCopyLong(Dm,esize2021,udt); } -:vmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=8 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=8 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +:vmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=8 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=8 & thv_c0404=0) ) & esize1819x2 & Dd & Qm { Dd = VectorCopyNarrow(Qm,esize1819x2); } +:vmovx.F16 Sd,Sm is (($(AMODE) & cond=15 & c2327=0x1d & c1921=0x6 & c1618=0 & c0611=0x29 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1d & thv_c1921=0x6 & thv_c1618=0 & thv_c0611=0x29 & thv_c0404=0) ) & Sd & Sm +{ + local SmUpper:2 = Sm(2); + Sd = zext(SmUpper); +} + @endif # SIMD @if defined(VFPv2) || defined(VFPv3) || defined(SIMD) -:vmrs^COND VRd,fpscr is COND & ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c0011=0xa10) | ($(TMODE_E) & thv_c1627=0xef1 & thv_c0011=0xa10)) & fpscr & VRd +:vmrs^COND VRd,fpscr is COND & ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xef1 & thv_c0011=0xa10)) & fpscr & VRd { VRd = fpscr; } apsr: "apsr" is epsilon {} -:vmrs^COND apsr,fpscr is COND & apsr & ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c1215=15 & c0011=0xa10) | ($(TMODE_E) & thv_c1627=0xef1 & thv_c1215=15 & thv_c0011=0xa10) ) & fpscr +:vmrs^COND apsr,fpscr is ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c1215=15 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xef1 & thv_c1215=15 & thv_c0011=0xa10) +) & COND & apsr & fpscr { NG = $(FPSCR_N); ZR = $(FPSCR_Z); @@ -3127,7 +4242,9 @@ apsr: "apsr" is epsilon {} OV = $(FPSCR_V); } -:vmsr^COND fpscr,VRd is COND & ( ($(AMODE) & ARMcond=1 & c1627=0xee1 & c0011=0xa10) | ($(TMODE_E) & thv_c1627=0xee1 & thv_c0011=0xa10) ) & VRd & fpscr +:vmsr^COND fpscr,VRd is ( ($(AMODE) & ARMcond=1 & c1627=0xee1 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xee1 & thv_c0011=0xa10) +) & COND & VRd & fpscr { fpscr = VRd; } @@ -3144,91 +4261,97 @@ define pcodeop FloatVectorMult; define pcodeop VectorMultiply; define pcodeop PolynomialMultiply; -:vmul.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=13 & Q6=0 & c0404=1) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +:vmul.f32 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm { Dd = FloatVectorMult(Dn,Dm,2:1,32:1); } -:vmul.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=13 & Q6=1 & c0404=1) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +:vmul.f32 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd { Qd = FloatVectorMult(Qn,Qm,2:1,32:1); } -:vmul.f16 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=0 & c0404=1) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +:vmul.f16 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm { Dd = FloatVectorMult(Dn,Dm,4:1,16:1); } -:vmul.f16 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=1 & c0404=1) | - ($(TMODE_F) &thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +:vmul.f16 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd { Qd = FloatVectorMult(Qn,Qm,4:1,16:1); } -:vmul^COND^".f64" Dd,Dn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +:vmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd { Dd = Dn f* Dm; } -:vmul^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sn & Sd +:vmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd { Sd = Sn f* Sm; } -:vmul^COND^".f16" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sn & Sd +:vmul^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd { product:2 = Sn:2 f* Sm:2; Sd = zext(product); } -:vmul.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=9 & Q6=0 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm +### +# VMUL (Integer and polynomial) +# + +:vmul.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=9 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm { Dd = VectorMultiply(Dn,Dm,esize2021); } -:vmul.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=9 & Q6=1 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=1 & thv_c0404=1)) & esize2021 & Qm & Qn & Qd +:vmul.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c0811=9 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=1 & thv_c0404=1)) & esize2021 & Qm & Qn & Qd { Qd = VectorMultiply(Qn,Qm,esize2021); } -:vmul.p8 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=0 & c0404=1) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=0 & thv_c0404=1) ) & Dn & Dd & Dm +:vmul.p8 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=0 & thv_c0404=1) ) & Dn & Dd & Dm { Dd = PolynomialMultiply(Dn,Dm,1:1); } -:vmul.p8 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=1 & c0404=1) | - ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +:vmul.p8 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd { Qd = PolynomialMultiply(Qn,Qm,1:1); } -:vmull.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0xc & Q6=0 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xc & thv_Q6=0 & thv_c0404=0) ) & esize2021 & Dm & Dn & Qd & udt +:vmull.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0xc & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xc & thv_Q6=0 & thv_c0404=0) ) & esize2021 & Dm & Dn & Qd & udt { Qd = VectorMultiply(Dn,Dm,esize2021,udt); } -:vmull.p8 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=0 & c0811=0xe & Q6=0 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd +:vmull.p8 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x5 & c2021=0 & c0811=0xe & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd { Qd = PolynomialMultiply(Dn,Dm,1:1); } -:vmull.p64 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=0xe & Q6=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd +:vmull.p64 Qd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x5 & c2021=2 & c0811=0xe & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd { Qd = PolynomialMultiply(Dn,Dm,8:1); } +# The below is confusing but these sub-constructors are used in a combination of F6.1.148 VMUL (by scalar) and F6.1.150 VMULL (by Scalar) + etype: "I" is TMode=0 & c0909=0 & c0808=0 {} etype: "F" is TMode=0 & c0909=0 & c0808=1 {} etype: "S" is TMode=0 & c0909=1 & c2424=0 {} @@ -3243,71 +4366,109 @@ vmlDmA: Dm_4^"["^M5^"]" is TMode=0 & c2021=2 & Dm_4 & M5 { el:4 = V vmlDmA: Dm_3^"["^index^"]" is TMode=1 & thv_c2021=1 & Dm_3 & thv_M5 & c0303 [ index = (thv_M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } vmlDmA: Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & Dm_4 & thv_M5 { el:4 = VectorGetElement(Dm_4, thv_M5:1, 4:1, 0:1); export el; } -:vmul.^etype^esize2021 Qd,Qn,vmlDmA is ( ($(AMODE) & cond=15 & c2424=1 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | - ($(TMODE_F) & thv_c2828=1 & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Qn & Qd & vmlDmA +:vmul.^etype^esize2021 Qd,Qn,vmlDmA is ( ($(AMODE) & cond=15 & c2327=0x07 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Qn & Qd & vmlDmA { Qd = VectorMultiply(Qn,vmlDmA,esize2021); } -:vmul.^etype^esize2021 Dd,Dn,vmlDmA is ( ($(AMODE) & cond=15 & c2424=0 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2828=0 & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Dn & Dd & vmlDmA +:vmul.^etype^esize2021 Dd,Dn,vmlDmA is ( ($(AMODE) & cond=15 & c2327=0x5 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Dn & Dd & vmlDmA { Dd = VectorMultiply(Dn,vmlDmA,esize2021); } -:vmull.^etype^esize2021 Qd,Dn,vmlDmA is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=10 & c0606=1 & c0404=0) | - ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=10 & thv_c0606=1 & thv_c0404=0 ) ) & Dd & Dm & esize1819 & etype & esize2021 & Dn & Qd & vmlDmA +:vmull.^etype^esize2021 Qd,Dn,vmlDmA is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=10 & thv_c0606=1 & thv_c0404=0 ) ) & Dd & Dm & esize1819 & etype & esize2021 & Dn & Qd & vmlDmA { Qd = VectorMultiply(Dn,vmlDmA,esize2021); } -:vmvn Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & Dd & Dm +### +# VMVN (immediate) +# + +:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +:vmvn.i16 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i16 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +### +# VMVN (register) +# + +:vmvn Dd,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & Dd & Dm { Dd = ~Dm; } -:vmvn Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & Qd & Qm +:vmvn Qd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & Qd & Qm { tmp1:8 = Qm:8; tmp2:8 = Qm(8); tmp1 = ~ tmp1; tmp2 = ~ tmp2; - Qd = (zext(tmp1) << 8) | zext(tmp2); + Qd = (zext(tmp1) << 8) | zext(tmp2); } -@endif # SIMD - - - define pcodeop FloatVectorNeg; -@if defined(SIMD) -:vneg.s^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +:vneg.s^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 { - Dd = FloatVectorNeg(Dm,esize1819); + Dd = FloatVectorNeg(Dm,1:1,esize1819); } -:vneg.s^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +:vneg.s^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 { - Qd = FloatVectorNeg(Qm,esize1819); + Qd = FloatVectorNeg(Qm,1:1,esize1819); } - -:vneg.f32 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xf & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dd +:vneg.f^fesize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=0xf & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=0 & thv_c0404=0 ) ) & fesize1819 & Dm & Dd { - Dd = FloatVectorNeg(Dm,2:1,32:1); + Dd = FloatVectorNeg(Dm,2:1,fesize1819); } -:vneg.f32 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xf & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +:vneg.f^fesize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xf & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm { - Qd = FloatVectorNeg(Qm,2:1,32:1); + Qd = FloatVectorNeg(Qm,2:1,fesize1819); } @endif # SIMD @@ -3315,88 +4476,98 @@ define pcodeop FloatVectorNeg; @if defined(VFPv2) || defined(VFPv3) -:vnmla^COND^".f64" Dd,Dn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd +:vnmla^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd { product:8 = Dn f* Dm; - Dd = (0 f- Dd) f+ (0 f- product); + Dd = (f- Dd) f+ (f- product); } -:vnmla^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmla^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd { product:4 = Sn f* Sm; - Sd = (0 f- Sd) f+ (0 f- product); + Sd = (f- Sd) f+ (f- product); } -:vnmla.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=1 & c0811=9 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmla.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=1 & c0811=9 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd { product:2 = Sn:2 f* Sm:2; - product = (0:2 f- Sd:2) f+ (0:2 f- product); + product = (f- Sd:2) f+ (f- product); Sd = zext(product); } -:vnmls^COND^".f64" Dd,Dn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +:vnmls^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd { product:8 = Dn f* Dm; Dd = product f- Dd; } -:vnmls^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmls^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd { product:4 = Sn f* Sm; Sd = product f- Sd; } -:vnmls.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=1 & c0811=9 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmls.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=1 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & Sm & Sn & Sd { product:2 = Sn:2 f* Sm:2; product = product f- Sd:2; Sd = zext(product); } -:vnmul^COND^".f64" Dd,Dn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd +:vnmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd { product:8 = Dn f* Dm; - Dd = 0 f- product; + Dd = f- product; } -:vnmul^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd { product:4 = Sn f* Sm; - Sd = 0 f- product; + Sd = f- product; } -:vnmul.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd +:vnmul.f16 Sd,Sn,Sm is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd { product:2 = Sn:2 f* Sm:2; - product = 0 f- product; + product = f- product; Sd = zext(product); } -:vneg^COND^".f32" Sd,Sm is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x29 & c0404=0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x29 & thv_c0404=0 ) ) & Sm & Sd +:vneg^COND^".f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x25 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sm & Sd { build COND; build Sd; build Sm; - Sd = 0 f- Sm; + local tmp:2 = Sm(0); + Sd = zext(f- tmp); } -:vneg^COND^".f64" Dd,Dm is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x2d & c0404=0 ) | - ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x2d & thv_c0404=0 ) ) & Dd & Dm +:vneg^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sm & Sd +{ + build COND; + build Sd; + build Sm; + Sd = f- Sm; +} + +:vneg^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Dm { build COND; build Dd; build Dm; - Dd = 0 f- Dm; + Dd = f- Dm; } @endif # VFPv2 || VFPv3 @@ -3404,7 +4575,7 @@ define pcodeop FloatVectorNeg; @if defined(SIMD) #F6.1.141 VORR (register) 64-bit SIMD vector variant (A1 and T1) -:vorr Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=0 & c0404=1) | +:vorr Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=0 & c0404=1) | ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm { @@ -3412,37 +4583,37 @@ define pcodeop FloatVectorNeg; } #F6.1.141 VORR (register) 128-bit SIMD vector variant (A1 and T1) -:vorr Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=1 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm +:vorr Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm { Qd = Qn | Qm; } #F6.1.140 VORR and F6.1.138 VORN (immediate) 64-bit SIMD vector variant -:vorr Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=1 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=1) ) & Dd & simdExpImm_8 +:vorr Dd,simdExpImm_8 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=1 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=1) ) & Dd & simdExpImm_8 { Dd = Dd | simdExpImm_8; } #F6.1.140 VORR and F6.1.138 VORN (immediate) 128-bit SIMD vector variant -:vorr Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=5 ) | - ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=5) ) & Qd & simdExpImm_16 +:vorr Qd,simdExpImm_16 is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=5 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=5) ) & Qd & simdExpImm_16 { Qd = Qd | simdExpImm_16; } #F6.1.139 VORN (register) 64-bit SIMD vector variant (A1 and T1) -:vorn Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=0 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +:vorn Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm { Dd = Dn | ~Dm; } #F6.1.139 VORN (register) 128-bit SIMD vector variant (A1 and T1) -:vorn Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=1 & c0404=1) | - ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm +:vorn Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm { Qd = Qn | ~Qm; } @@ -3469,14 +4640,14 @@ vpushSd64List: "{"^buildVpushSd64List^"}" is TMode=0 & D22 & c1215 & c0007 & bui vpushSd64List: "{"^buildVpushSd64List^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpushSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ] { sp = sp - thv_c0007 * 4; mult_addr = sp; build buildVpushSd64List; } -:vpush^COND vpushSd64List is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2121=1 & c2020=0 & c0811=11) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2121=1 & thv_c2020=0 & thv_c0811=11) ) & vpushSd64List +:vpush^COND vpushSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=11 & thv_c0000=0) ) & COND & vpushSd64List { build vpushSd64List; } -:vpush^COND vpushSdList is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2121=1 & c2020=0 & c0811=10) | - ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2121=1 & thv_c2020=0 & thv_c0811=10) ) & vpushSdList +:vpush^COND vpushSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=10) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=10) ) & COND & vpushSdList { build vpushSdList; } @@ -3501,14 +4672,14 @@ vpopSd64List: "{"^buildVpopSd64List^"}" is TMode=0 & D22 & c1215 & c0007 & build vpopSd64List: "{"^buildVpopSd64List^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpopSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ] { mult_addr = sp; sp = sp + thv_c0007 * 4; build buildVpopSd64List; } -:vpop^COND vpopSd64List is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2121=1 & c2020=1 & c0811=11 & c0000=0) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & vpopSd64List +:vpop^COND vpopSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=11 & thv_c0000=0) ) & COND & vpopSd64List { build vpopSd64List; } -:vpop^COND vpopSdList is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2121=1 & c2020=1 & c0811=10) | - ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2121=1 & thv_c2020=1 & thv_c0811=10) ) & vpopSdList +:vpop^COND vpopSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=10) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=10) ) & COND & vpopSdList { build vpopSdList; } @@ -3520,44 +4691,58 @@ vpopSd64List: "{"^buildVpopSd64List^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c define pcodeop SatQ; define pcodeop SignedSatQ; -:vqadd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=0 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=0 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm +:vqabs^".s"^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=7 & c0811=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm +{ + Dd = VectorAbs(Dn,Dm,esize2021); + Dd = SatQ(Dd, esize2021, 0:1); +} + +:vqabs^".s"^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c0811=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorAbs(Qn,Qm,esize2021); + Qd = SatQ(Qd, esize2021, 0:1); +} + +:vqadd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm { Dd = VectorAdd(Dn,Dm,esize2021,udt); Dd = SatQ(Dd, esize2021, udt); } -:vqadd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=1 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=0 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd +:vqadd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd { Qd = VectorAdd(Qn,Qm,esize2021,udt); Qd = SatQ(Qd, esize2021, udt); } -:vqmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=5 & c0606 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=5 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +:vqmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=5 & c0606 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=5 & thv_c0404=0) ) & esize1819x2 & Dd & Qm { Dd = VectorCopyNarrow(Qm,esize1819x2,c0606:1); Dd = SatQ(Dd, esize1819x2,0:1); } -:vqmovun.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=9 & c0404=0) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=9 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +:vqmovun.i^esize1819x2 Dd,Qm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=9 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=9 & thv_c0404=0) ) & esize1819x2 & Dd & Qm { Dd = VectorCopyNarrow(Qm,esize1819x2,0:1); Dd = SatQ(Dd, esize1819x2,0:1); } -:vqdmlal.S^esize2021 Qd, Dn, Dm is ( ( $(AMODE) & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x9 & c0606=0 & c0404=0 ) | - ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x9 & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd +:vqdmlal.S^esize2021 Qd,Dn,Dm is ( ( $(AMODE) & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x9 & c0606=0 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x9 & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd { Qd = VectorDoubleMultiplyAccumulateLong(Dn,Dm,esize2021,0:1); Qd = SatQ(Qd, esize2021,0:1); } -:vqdmlal.S^esize2021 Qd, Dn, vmlDmA is ( ( $(AMODE) & cond=15 & c2327=5 & (c2021=1 | c2021=2)& c0811=0x3 & c0606=1 & c0404=0) | - ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x3 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd +:vqdmlal.S^esize2021 Qd,Dn,vmlDmA is ( ( $(AMODE) & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x3 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x3 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd { Qd = VectorDoubleMultiplyAccumulateLong(Dn,vmlDmA,esize2021,0:1); @@ -3675,10 +4860,6 @@ define pcodeop SignedSatQ; Qd = SatQ(Qd, esize2021, udt); } -####### -# TODO: lots of missing stuff -# - ####### # VRECPE define pcodeop VectorReciprocalEstimate; @@ -3796,15 +4977,28 @@ ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_c2021=1 & thv_L7=0 & thv_c1621 [ sh ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_c2121=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 32; ] { export *[const]:8 shift_amt; } ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_L7=1 & thv_c1621 [ shift_amt = thv_c1621 - 0; ] { export *[const]:8 shift_amt; } -:vqshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x24 & c0404=1) | - ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x24 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm +:vqrshl.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorRoundShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt); +} + +:vqrshl.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorRoundShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt); +} + + +:vqshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x24 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x24 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm { Dd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); Dd = SatQ(Dd,esize2021,udt); } -:vqshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x20 & c0404=1) | - ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x20 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm +:vqshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & cond=15 & c2327=7 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x20 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x20 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm { Dd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); Dd = SatQ(Dd,esize2021,udt); @@ -3956,6 +5150,43 @@ define pcodeop VectorShiftLongLeft; Qd = VectorShiftLeftInsert(Qd, Qm,ShiftImmLLI); } +define pcodeop VectorWidenMultipyAccumulate; +:vsmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,0:1); +} + +:vsmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,0:1); +} + +:vummla.u8 Dd, Dm, Dn is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,1:1); +} + +:vummla.u8 Qd, Qm, Qn is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,1:1); +} + +:vusmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,2:1); +} + +:vusmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,2:1); +} + :vsqrt^COND^".f32" Sd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=1 & c0811=10 & c0607=3 & c0404=0) | ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sd { @@ -4754,6 +5985,96 @@ define pcodeop VectorTranspose; Qd = VectorTranspose(Qm,esize1819); } +##### +# V[SU]DOT +define pcodeop VectorSignedDotProduct; +define pcodeop VectorUnsignedDotProduct; +define pcodeop VectorSignedUnsignedDotProduct; +define pcodeop VectorUnsignedSignedDotProduct; + +:vsdot.s8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorSignedDotProduct(Dn,Dm0,Mindex); +} + +:vsdot.s8 Qd,Qn,Qm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorSignedDotProduct(Qn,Qm0,Mindex); +} + +:vsdot.s8 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +{ + Dd = VectorSignedDotProduct(Dn,Dm); +} + +:vsdot.s8 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd +{ + Qd = VectorSignedDotProduct(Qn,Qm); +} + +:vudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorUnsignedDotProduct(Dn,Dm0,Mindex); +} + +:vudot.u8 Qd,Qn,Qm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorUnsignedDotProduct(Qn,Qm0,Mindex); +} + +:vudot.u8 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm & Dn & Dd +{ + Dd = VectorUnsignedDotProduct(Dn,Dm); +} + +:vudot.u8 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = VectorUnsignedDotProduct(Qn,Qm); +} + +:vsudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorSignedUnsignedDotProduct(Dn,Dm0,Mindex); +} + +:vsudot.u8 Qd,Qn,Qm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorSignedUnsignedDotProduct(Qn,Qm0,Mindex); +} + +:vusdot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorUnsignedSignedDotProduct(Dn,Dm0,Mindex); +} + +:vusdot.u8 Qd,Qn,Qm0^Mindex is ( ($(AMODE) & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorUnsignedSignedDotProduct(Qn,Qm0,Mindex); +} + +:vusdot.u8 Dd,Dn,Dm is ( ($(AMODE) & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +{ + Dd = VectorUnsignedSignedDotProduct(Dn,Dm); +} + +:vusdot.u8 Qd,Qn,Qm is ( ($(AMODE) & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd +{ + Qd = VectorUnsignedSignedDotProduct(Qn,Qm); +} ####### # VUZP @@ -4761,14 +6082,14 @@ define pcodeop VectorTranspose; define pcodeop VectorUnzip; -:vuzp^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=0 & c0404=0 ) | - ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +:vuzp^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 { Dd = VectorUnzip(Dm,esize1819); } -:vuzp^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=1 & c0404=0 ) | - ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +:vuzp^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 { Qd = VectorUnzip(Qm,esize1819); } @@ -4780,14 +6101,14 @@ define pcodeop VectorUnzip; define pcodeop VectorZip; -:vuzp^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=0 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +:vzip^esize1819 Dd,Dm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 { Dd = VectorZip(Dm,esize1819); } -:vuzp^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=1 & c0404=0 ) | - ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +:vzip^esize1819 Qd,Qm is ( ( $(AMODE) & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 { Qd = VectorZip(Qm,esize1819); } diff --git a/Ghidra/Processors/ARM/data/languages/ARMv8.sinc b/Ghidra/Processors/ARM/data/languages/ARMv8.sinc index ce4511de43..b2ff9796cb 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMv8.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMv8.sinc @@ -14,19 +14,19 @@ crc32_type: "w" is TMode=1 & thv_c0405=0b10 { } define pcodeop Crc32Calc; -# F5.1.39,40 p2650,2653 CRC32,CRC32C A1 +# F5.1.39,40 p7226,7229 CRC32,CRC32C A1 :crc32^crc32_type Rd,Rn,Rm is TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0 & crc32_type & Rn & Rd & Rm { Rd = Crc32Calc(Rn,Rm); } -# F5.1.39 p2650 CRC32 T1 +# F5.1.39 p7226 CRC32 T1 :crc32^crc32_type thv_Rt2,thv_Rn,thv_Rm is TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10 & crc32_type & thv_Rn & thv_Rt2 & thv_Rm { thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); } -# F5.1.40 p2653 CRC32C T1 +# F5.1.40 p7229 CRC32C T1 :crc32c^crc32_type thv_Rt2,thv_Rn,thv_Rm is TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10 & crc32_type & thv_Rn & thv_Rt2 & thv_Rm @@ -38,12 +38,12 @@ dcps_lev:1 is TMode=1 & thv_c0001=0b01 { export 1:1; } dcps_lev:2 is TMode=1 & thv_c0001=0b10 { export 2:1; } dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } -# F5.1.42 p2657 DCPS1,DCPS2,DCPS3 DSPS1 variant +# F5.1.43 p7235 DCPS1,DCPS2,DCPS3 DSPS1 variant :dcps^dcps_lev is TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev { DCPSInstruction(dcps_lev:1); } -# F5.1.53 p2683 LDA +# F5.1.57 p7268 LDA :lda^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f { @@ -51,7 +51,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = *Rn; } -# F5.1.53 p2683 LDA +# F5.1.57 p7268 LDA :lda thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010 & ItCond & thv_Rn & thv_Rt @@ -60,7 +60,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = *thv_Rn; } -# F5.1.54 p2684 LDAB +# F5.1.58 p7270 LDAB :ldab^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f { @@ -69,7 +69,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = zext(val); } -# F5.1.54 p2684 LDAB +# F5.1.58 p7270 LDAB :ldab thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000 & ItCond & thv_Rt & thv_Rn @@ -79,7 +79,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = zext(val); } -# F5.1.55 p2685 LDAEX +# F5.1.59 p7272 LDAEX :ldaex^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f { @@ -87,7 +87,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = *Rn; } -# F5.1.55 p2685 LDAEX +# F5.1.59 p7272 LDAEX :ldaex thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110 & ItCond & thv_Rt & thv_Rn @@ -96,7 +96,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = *thv_Rn; } -# F5.1.56 p2687 LDAEXB +# F5.1.60 p7274 LDAEXB :ldaexb^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f { @@ -105,7 +105,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = zext(val); } -# F5.1.56 p2687 LDAEXB +# F5.1.60 p7274 LDAEXB :ldaexb thv_Rt,thv_Rn is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100 & ItCond & thv_Rt & thv_Rn @@ -115,7 +115,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = zext(val); } -# F5.1.57 p2689 LDAEXD +# F5.1.61 p7274 LDAEXD :ldaexd^COND Rd,Rd2,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f { @@ -129,7 +129,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } @endif # ENDIAN == "little" } -# F5.1.57 p2689 LDAEXD +# F5.1.61 p7274 LDAEXD :ldaexd thv_Rt,thv_Rt2,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111 & ItCond & thv_Rt & thv_Rt2 & thv_Rn @@ -144,7 +144,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } @endif # ENDIAN == "little" } -# F5.1.58 p2691 LDAEXH +# F5.1.62 p7278 LDAEXH :ldaexh^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f { @@ -153,7 +153,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = zext(val); } -# F5.1.58 p2691 LDAEXH +# F5.1.62 p7278 LDAEXH :ldaexh thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101 & ItCond & thv_Rt & thv_Rn @@ -163,7 +163,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = zext(val); } -# F5.1.59 p2693 LDAH +# F5.1.63 p7280 LDAH :ldah^COND Rd,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f { @@ -172,7 +172,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = zext(val); } -# F5.1.59 p2693 LDAH +# F5.1.63 p7280 LDAH :ldah thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001 & ItCond & thv_Rt & thv_Rn @@ -182,7 +182,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rt = zext(val); } -# F5.1.178 p2969 SEVL A1 variant +# F5.1.185 p7573 SEVL A1 variant :sevl^COND is TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101 { @@ -190,7 +190,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } SendEvent(); } -# F5.1.178 p2969 SEVL T2 variant +# F5.1.185 p7573 SEVL T2 variant :sevl.w is TMode=1 & thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101 & ItCond @@ -199,7 +199,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } SendEvent(); } -# F5.1.209 p3035 STL +# F5.1.217 p7642 STL :stl^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm { @@ -207,7 +207,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } *Rn = Rm; } -# F5.1.209 p3035 STL +# F5.1.217 p7642 STL :stl thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010 & ItCond & thv_Rt & thv_Rn @@ -216,7 +216,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } *thv_Rn = thv_Rt; } -# F5.1.210 p3036 STLB +# F5.1.218 p7644 STLB :stlb^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm { @@ -224,7 +224,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } *:1 Rn = Rm[0,8]; } -# F5.1.210 p3036 STLB +# F5.1.218 p7644 STLB :stlb thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000 & ItCond & thv_Rt & thv_Rn @@ -233,7 +233,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } *:1 thv_Rn = thv_Rt[0,8]; } -# F5.1.211 p3037 STLEX +# F5.1.219 p7646 STLEX :stlex^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm { @@ -242,7 +242,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = 0; } -# F5.1.211 p3037 STLEX +# F5.1.219 p7646 STLEX :stlex thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110 & ItCond & thv_Rm & thv_Rt & thv_Rn @@ -252,7 +252,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rm = 0; } -# F5.1.212 p3040 STLEXB +# F5.1.220 p7649 STLEXB :stlexb^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm { @@ -261,7 +261,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = 0; } -# F5.1.212 p3040 STLEXB +# F5.1.220 p7649 STLEXB :stlexb thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100 & ItCond & thv_Rm & thv_Rt & thv_Rn @@ -271,7 +271,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rm = 0; } -# F5.1.213 p3042 STLEXD +# F5.1.221 p7651 STLEXD :stlexd^COND Rd,Rm,Rm2,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2 { @@ -286,7 +286,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = 0; } -# F5.1.213 p3042 STLEXD +# F5.1.221 p7651 STLEXD :stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1111 & ItCond & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn @@ -302,7 +302,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rm = 0; } -# F5.1.214 p3045 STLEXH +# F5.1.222 p7654 STLEXH :stlexh^COND Rd,Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm { @@ -311,7 +311,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } Rd = 0; } -# F5.1.214 p3045 STLEXH +# F5.1.222 p7654 STLEXH :stlexh thv_Rm,thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1101 & ItCond & thv_Rm & thv_Rt & thv_Rn @@ -321,7 +321,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } thv_Rm = 0; } -# F5.1.215 p3048 STLH +# F5.1.223 p7657 STLH :stlh^COND Rm,[Rn] is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm { @@ -329,7 +329,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } *:2 Rn = Rm[0,16]; } -# F5.1.215 p3048 STLH +# F5.1.223 p7657 STLH :stlh thv_Rt,[thv_Rn] is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1001 & ItCond & thv_Rt & thv_Rn @@ -363,11 +363,7 @@ dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } ####### # pcodeop declarations -# CryptOp(val) -# Various crypto algorithms, too numerous for explication at -# this time -define pcodeop CryptOp; # FixedToFP(fp, M, N, fbits, unsigned, rounding) # Convert M-bit fixed point with fbits fractional bits to N-bit @@ -416,165 +412,27 @@ define pcodeop FPRoundInt; define pcodeop PolynomialMult; -####### -# AESD single round decryption -# F6.1.1 p3235 A1/T1 -:aesd.8 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001101 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001101 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qd | Qm); } - -####### -# AESE single round encryption - -# F6.1.2 p3237 A1/T1 -:aese.8 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001100 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001100 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qd | Qm); } - -####### -# AESIMC inverse mix columns - -# F6.1.3 p3239 A1/T1 -:aesimc.8 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001111 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001111 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qm); } - -####### -# AESMC mix columns - -# F6.1.4 p3240 A1/T1 -:aesmc.8 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001110 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001110 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qm); } - -####### -# SHA1C SHA1 hash update (choose) - -# F6.1.7 p3248 A1/T1 -:sha1c.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA1H SHA1 fixed rotate - -# F6.1.8 p3250 A1/T1 -:sha1h.32 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b01 & c0611=0b001011 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b01 & thv_c0611=0b001011 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qm); } - -####### -# SHA1M SHA1 hash update (majority) - -# F6.1.9 p3251 A1/T1 -:sha1m.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA1P SHA1 hash update (parity) - -# F6.1.10 p3253 A1/T1 -:sha1p.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA1SU0 SHA1 schedule update 0 - -# F6.1.11 p3255 A1/T1 -:sha1su0.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b11 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA1SU1 SHA1 schedule update 1 - -# F6.1.12 p3257 A1/T1 -:sha1su1.32 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001110 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001110 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qd,Qm); } - -####### -# SHA256H SHA256 hash update part 1 - -# F6.1.13 p3259 A1/T1 -:sha256h.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA256H2 SHA256 hash update part 2 - -# F6.1.14 p3260 A1/T1 -:sha256h2.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } - -####### -# SHA256SU0 SHA256 schedule update 0 - -# F6.1.15 p3261 A1/T1 -:sha256su0.32 Qd,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001111 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001111 & thv_c0404=0)) - & Qd & Qm - { Qd = CryptOp(Qd,Qm); } - -####### -# SHA256SU1 SHA256 schedule update 1 - -# F6.1.16 p3263 A1/T1 -:sha256su1.32 Qd,Qn,Qm - is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) - | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) - & Qn & Qd & Qm - { Qd = CryptOp(Qd,Qn,Qm); } ####### # The VCVT instructions are a large family for converting between # floating point numbers and integers, of all sizes and combinations -# F6.1.54 p3350 A1 cases size = 10 (c0809) +# F6.1.58 p7998 A1 cases size = 10 (c0809) :vcvt^COND^".f64.f32" Dd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & COND & Dd & Sm { build COND; Dd = float2float(Sm); } -# F6.1.54 p3350 A1 cases size = 11 (c0809) +# F6.1.58 p7998 A1 cases size = 11 (c0809) :vcvt^COND^".f32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) & COND & Sd & Dm { build COND; Sd = float2float(Dm); } -# F6.1.55 p3352 A1 op == 1 (c0808) +# F6.1.59 p8000 A1 op == 1 (c0808) :vcvt.f32.f16 Qd,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1)) @@ -583,7 +441,7 @@ define pcodeop PolynomialMult; Qd = float2float(Dm:2); } -# F6.1.55 p3352 A1 op == 0 (c0808) +# F6.1.59 p8000 A1 op == 0 (c0808) :vcvt.f16.f32 Dd,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0)) @@ -632,47 +490,47 @@ vcvt_56_128_dt: ".u32.f32" & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } -# F6.1.56 p3354 A1 Q == 0 (c0606) +# F6.1.60 p8002 A1 Q == 0 (c0606) :vcvt^vcvt_56_64_dt Dd,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0)) & vcvt_56_64_dt & Dd & Dm { } -# F6.1.56 p3354 A1 Q == 1 (c0606) +# F6.1.60 p8002 A1 Q == 1 (c0606) :vcvt^vcvt_56_128_dt Qd,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1)) & vcvt_56_128_dt & Qd & Qm { } -# F6.1.57 p3356 A1 opc2==100 && size==10 (c1618, c0809) +# F6.1.61 p8005 A1 opc2==100 && size==10 (c1618, c0809) :vcvt^COND^".u32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) & COND & Sd & Sm - { build COND; Sd = trunc(Sm); } + { build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); } -# F6.1.57 p3356 A1 opc2==101 && size==10 (c1618, c0809) +# F6.1.61 p8005 A1 opc2==101 && size==10 (c1618, c0809) :vcvt^COND^".s32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) & COND & Sd & Sm - { build COND; Sd = trunc(Sm); } + { build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); } -# F6.1.57 p3356 A1 opc2==100 && size==11 (c1618, c0809) +# F6.1.61 p8005 A1 opc2==100 && size==11 (c1618, c0809) :vcvt^COND^".u32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) & COND & Sd & Dm - { build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; } + { build COND; local tmp:8 = zext(Dm f> 0) * (trunc(Dm)); Sd = tmp:4; } -# F6.1.57 p3356 A1 opc2==101 && size==11 (c1618, c0809) +# F6.1.61 p8005 A1 opc2==101 && size==11 (c1618, c0809) :vcvt^COND^".s32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) & COND & Sd & Dm - { build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; } + { build COND; local tmp:8 = zext(Dm f> 0:8) * (trunc(Dm)); Sd = tmp:4; } # The rounding mode depends on c0707=0 => FPSCR else ZERO @@ -698,14 +556,14 @@ vcvt_58_6432_dt: ".f64.s32" & Dd & Sm { local tmp:8 = sext(Sm); Dd = int2float(tmp); } -# F6.1.58 p3359 A1 size == 10 (c0809) +# F6.1.62 p8009 A1 size == 10 (c0809) :vcvt^COND^vcvt_58_3232_dt Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & COND & vcvt_58_3232_dt & Sd & Sm { build COND; build vcvt_58_3232_dt; } -# F6.1.58 p3359 A1 size == 11 (c0809) +# F6.1.62 p8009 A1 size == 11 (c0809) :vcvt^COND^vcvt_58_6432_dt Dd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) @@ -762,14 +620,14 @@ vcvt_59_64_dt: ".u32.f32" # Should add rounding here, if dt2 is s32 or u32 then rounding is # FPRounding_ZERO otherwise FPROunding_TIEEVEN -# F6.1.59 p3361 A1 Q = 0 (c0606) +# F6.1.63 p8012 A1 Q = 0 (c0606) :vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=0) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0)) & vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm { } -# F6.1.59 p3361 A1 Q = 1 (c0606) +# F6.1.63 p8012 A1 Q = 1 (c0606) :vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=1) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1)) @@ -867,14 +725,14 @@ vcvt_60_64_dt: ".u32.f64" & Dd & Dd2 & vcvt_60_fbits_built { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } -# F6.1.60 p3364 A1 op=0/1 sf=10 (c1818, c0809) +# F6.1.63 p8012 A1 op=0/1 sf=10 (c1818, c0809) :vcvt^COND^vcvt_60_32_dt Sd,Sd2,vcvt_60_fbits is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b10)) & COND & vcvt_60_fbits & vcvt_60_32_dt & Sd & Sd2 { build COND; build vcvt_60_32_dt; } -# F6.1.60 p3364 A1 op=0/1 sf=11 (c1818, c0809) +# F6.1.63 p8012 A1 op=0/1 sf=11 (c1818, c0809) :vcvt^COND^vcvt_60_64_dt Dd,Dd2,vcvt_60_fbits is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b11)) @@ -911,14 +769,14 @@ vcvt_amnp_simd_128_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_s vcvt_amnp_simd_128_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } -# F6.1.61,64,66,68 p3367,3374,3378,3384 A1 64-bit SIMD vector variant Q = 0 (c0606) +# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606) :vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0)) & vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm { } -# F6.1.61,64,66,68 p3367,3374,3378,3384 A1 128-bit SIMD vector variant Q = 1(c0606) +# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606) :vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1)) @@ -952,14 +810,14 @@ vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } -# F6.1.62,65,67,69 p3369,3376,3380,3384 Single-precision scalar variant size = 11 (c0809) +# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809) :vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm { } -# F6.1.62,65,67,69 p3369,3376,3380,3384 Double-precision scalar variant size = 10 (c0809) +# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 10 (c0809) :vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) @@ -1012,32 +870,32 @@ vcvt_bt1664_op: "t" & Sd & Dm { tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } -# F6.1.63 p3371 A1 cases op:sz = 00 (c1616, c0808) -# F6.1.71 p3389 A1 cases op:sz = 00 (c1616, c0808) +# F6.1.67 p8023 A1 cases op:sz = 00 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 00 (c1616, c0808) :vcvt^vcvt_bt3216_op^COND^".f32.f16" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=0)) & COND & vcvt_bt3216_op & Sd & Sm { build COND; build vcvt_bt3216_op; } -# F6.1.63 p3371 A1 cases op:sz = 01 (c1616, c0808) -# F6.1.71 p3389 A1 cases op:sz = 01 (c1616, c0808) +# F6.1.67 p8023 A1 cases op:sz = 01 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 01 (c1616, c0808) :vcvt^vcvt_bt6416_op^COND^".f64.f16" Dd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=1)) & COND & vcvt_bt6416_op & Dd & Sm { build COND; build vcvt_bt6416_op; } -# F6.1.63 p3371 A1 cases op:sz = 10 (c1616, c0808) -# F6.1.71 p3389 A1 cases op:sz = 10 (c1616, c0808) +# F6.1.67 p8023 A1 cases op:sz = 10 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 10 (c1616, c0808) :vcvt^vcvt_bt1632_op^COND^".f16.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=0)) & COND & vcvt_bt1632_op & Sd & Sm { build COND; build vcvt_bt1632_op; } -# F6.1.63 p3371 A1 cases op:sz = 11 (c1616, c0808) -# F6.1.71 p3389 A1 cases op:sz = 11 (c1616, c0808) +# F6.1.67 p8023 A1 cases op:sz = 11 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 11 (c1616, c0808) :vcvt^vcvt_bt1664_op^COND^".f16.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=1)) @@ -1046,28 +904,28 @@ vcvt_bt1664_op: "t" # vcvtr -# F6.1.70 p3386 A1 case opc2=100 size=10 (c1618, c0809) +# F6.1.75 p8040 A1 case opc2=100 size=10 (c1618, c0809) :vcvtr^COND^".u32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) & COND & Sd & Sm { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } -# F6.1.70 p3386 A1 case opc2=101 size=10 +# F6.1.75 p8040 A1 case opc2=101 size=10 :vcvtr^COND^".s32.f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) & COND & Sd & Sm { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); } -# F6.1.70 p3386 A1 case opc2=100 size=11 +# F6.1.75 p8040 A1 case opc2=100 size=11 :vcvtr^COND^".u32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) & COND & Sd & Dm { build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } -# F6.1.70 p3386 A1 case opc2=101 size=11 +# F6.1.75 p8040 A1 case opc2=101 size=11 :vcvtr^COND^".s32.f64" Sd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) @@ -1090,98 +948,98 @@ define pcodeop FPMaxNum; define pcodeop FPMinNum; -# F6.1.101 p3471 A1/T1 Q = 0 (c0606) +# F6.1.117 p8178 A1/T1 Q = 0 (c0606) :vmaxnm^".f32" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } -# F6.1.101 p3471 A1/T1 Q = 1 (c0606) +# F6.1.117 p8178 A1/T1 Q = 1 (c0606) :vmaxnm^".f32" Qd,Qn,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMaxNum(Qn, Qm); } -# F6.1.101 p3471 A1/T1 Q = 0 (c0606) +# F6.1.117 p8178 A1/T1 Q = 0 (c0606) :vmaxnm^".f16" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } -# F6.1.101 p3471 A1/T1 Q = 1 (c0606) +# F6.1.117 p8178 A1/T1 Q = 1 (c0606) :vmaxnm^".f16" Qd,Qn,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMaxNum(Qn, Qm); } -# F6.1.101 p3471 A2/T2 size = 01 (c0809) +# F6.1.117 p8178 A2/T2 size = 01 (c0809) :vmaxnm^".f16" Sd,Sn,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01)) & Sd & Sn & Sm { Sd = FPMaxNum(Sn, Sm); } -# F6.1.101 p3471 A2/T2 size = 10 (c0809) +# F6.1.117 p8178 A2/T2 size = 10 (c0809) :vmaxnm^".f32" Sd,Sn,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) & Sd & Sn & Sm { Sd = FPMaxNum(Sn, Sm); } -# F6.1.101 p3471 A2/T2 size = 11 (c0809) +# F6.1.117 p8178 A2/T2 size = 11 (c0809) :vmaxnm^".f64" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) & Dd & Dn & Dm { Dd = FPMaxNum(Dn, Dm); } -# F6.1.104 p3478 A1/T1 Q = 0 (c0606) +# F6.1.120 p8178 A1/T1 Q = 0 (c0606) :vminnm^".f32" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMinNum(Dn, Dm); } -# F6.1.104 p3478 A1/T1 Q = 1 (c0606) +# F6.1.120 p8178 A1/T1 Q = 1 (c0606) :vminnm^".f32" Qd,Qn,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMinNum(Qn, Qm); } -# F6.1.104 p3478 A1/T1 Q = 0 (c0606) +# F6.1.120 p8178 A1/T1 Q = 0 (c0606) :vminnm^".f16" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) & Dd & Dn & Dm { Dd = FPMinNum(Dn, Dm); } -# F6.1.104 p3478 A1/T1 Q = 1 (c0606) +# F6.1.120 p8178 A1/T1 Q = 1 (c0606) :vminnm^".f16" Qd,Qn,Qm is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) & Qd & Qn & Qm { Qd = FPMinNum(Qn, Qm); } -# F6.1.104 p3478 A2/T2 size = 01 (c0809) +# F6.1.120 p8178 A2/T2 size = 01 (c0809) :vminnm^".f16" Sd,Sn,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) & Sd & Sn & Sm { Sd = FPMinNum(Sn, Sm); } -# F6.1.104 p3478 A2/T2 size = 10 (c0809) +# F6.1.120 p8178 A2/T2 size = 10 (c0809) :vminnm^".f32" Sd,Sn,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) & Sd & Sn & Sm { Sd = FPMinNum(Sn, Sm); } -# F6.1.104 p3478 A2/T2 size = 11 (c0809) +# F6.1.120 p8178 A2/T2 size = 11 (c0809) :vminnm^".f64" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) @@ -1231,14 +1089,14 @@ vmull_dt: ".p64" | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10)) { } -# F6.1.130 p3537 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01) +# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01) :vmull^vmull_dt Qd,Dn,Dm is ((TMode=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1) | (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1)) & vmull_dt & Qd & Dn & Dm { Qd = PolynomialMult(Dn, Dm); } -# F6.1.130 p3537 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11) +# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11) :vmull^vmull_dt Qd,Dn,Dm is ((TMode=0 & c2531=0b1111001 & c2424 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0) | (TMode=1 & thv_c2931=0b111 & thv_c2828 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0)) @@ -1307,14 +1165,14 @@ vrint_simd_ixf: { } -# F6.1.178,180,182,184,187,189 p3646,3650,3654,3658,3664,3668 Q = 0 (c0606) +# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 0 (c0606) :vrint^vrint_simd_RM^".f32" Dd,Dm is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0) | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & ((thv_c0707=0 & thv_c0909=0) | (thv_c0707=1 & thv_c0909=1) | (thv_c0707=1 & thv_c0909=0)) & thv_c0404=0 & thv_c0606=0)) & vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Dd & Dm { Dd = FPRoundInt(Dm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; } -# F6.1.178,180,182,184,187,189 p3646,3650,3654,3658,3664,3668 Q = 1 (c0606) +# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 1 (c0606) :vrint^vrint_simd_RM^".f32" Qd,Qm is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1) | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & thv_c0404=0 & thv_c0606=1)) @@ -1341,14 +1199,14 @@ vrint_fp_RM: "p" | (TMode=1 & thv_c1617=0b10)) { export $(FPRounding_POSINF); } -# F6.1.179,181,183,185 p3648,3652,3656,3660 size = 10 (c0809) +# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809) :vrint^vrint_fp_RM^".f32" Sd,Sm is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10)) & vrint_fp_RM & Sd & Sm { Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); } -# F6.1.179,181,183,185 p3648,3652,3656,3660 size = 11 (c0809) +# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809) :vrint^vrint_fp_RM^".f64" Dd,Dm is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11)) @@ -1392,14 +1250,14 @@ vrint_rxz_ixf: | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) { } -# F6.1.186,188,190 p3662,3666,3670 A1 size = 10 (c0809) +# F6.1.207,209,211 p8412,8416,8420 A1 size = 10 (c0809) :vrint^vrint_rxz_RM^COND^".f32" Sd,Sm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b10)) & vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Sd & Sm { build COND; Sd = FPRoundInt(Sm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; } -# F6.1.186,188,190 p3662,3666,3670 A1 size = 11 (c0809) +# F6.1.207,209,211 p8412,8416,8420 A1 size = 11 (c0809) :vrint^vrint_rxz_RM^COND^".f64" Dd,Dm is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11) | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b11)) @@ -1426,14 +1284,14 @@ vselcond: "vs" | (TMode=1 & thv_c2021=0b01)) { tmp:1 = OV; export tmp; } -# F6.1.200 p3690 A1/T1 size = 11 doubleprec (c0809) +# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809) :vsel^vselcond^".f64" Dd,Dn,Dm is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) & vselcond & Dn & Dd & Dm { Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; } -# F6.1.200 p3690 A1/T1 size = 10 singleprec (c0809) +# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809) :vsel^vselcond".f32" Sd,Sn,Sm is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) diff --git a/Ghidra/Processors/ARM/data/manuals/ARM.idx b/Ghidra/Processors/ARM/data/manuals/ARM.idx index f898a8bda6..851c426c53 100644 --- a/Ghidra/Processors/ARM/data/manuals/ARM.idx +++ b/Ghidra/Processors/ARM/data/manuals/ARM.idx @@ -1,6461 +1,404 @@ -@Armv7AR_errata.pdf[ARM Architecture Reference Manual - ARMv7A and ARMv7-R edition Errata markup, July, 2011 (ARM DDI 0406B_errata_2011_Q2)] +@DDI0487H_a_a-profile_architecture_reference_manual.pdf[ARM Architecture Reference Manual - ARM A-profile architecture, December 2021 (ARM DDI 0487H.a)] -adc, 326 -adceq, 326 -adcne, 326 -adcmi, 326 -adcpl, 326 -adcvs, 326 -adcvc, 326 -adchi, 326 -adcls, 326 -adcge, 326 -adclt, 326 -adcgt, 326 -adcle, 326 -adcal, 326 -adclo, 326 -adccc, 326 -adchs, 326 -adccs, 326 -adcnv, 326 -adcs, 326 -adceqs, 326 -adcnes, 326 -adcmis, 326 -adcpls, 326 -adcvss, 326 -adcvcs, 326 -adchis, 326 -adclss, 326 -adcges, 326 -adclts, 326 -adcgts, 326 -adcles, 326 -adcals, 326 -adclos, 326 -adcccs, 326 -adchss, 326 -adccss, 326 -adcnvs, 326 -adcseq, 326 -adcsne, 326 -adcsmi, 326 -adcspl, 326 -adcsvs, 326 -adcsvc, 326 -adcshi, 326 -adcsls, 326 -adcsge, 326 -adcslt, 326 -adcsgt, 326 -adcsle, 326 -adcsal, 326 -adcslo, 326 -adcscc, 326 -adcshs, 326 -adcscs, 326 -adcsnv, 326 -add, 332 -addeq, 332 -addne, 332 -addmi, 332 -addpl, 332 -addvs, 332 -addvc, 332 -addhi, 332 -addls, 332 -addge, 332 -addlt, 332 -addgt, 332 -addle, 332 -addal, 332 -addlo, 332 -addcc, 332 -addhs, 332 -addcs, 332 -addnv, 332 -adds, 332 -addeqs, 332 -addnes, 332 -addmis, 332 -addpls, 332 -addvss, 332 -addvcs, 332 -addhis, 332 -addlss, 332 -addges, 332 -addlts, 332 -addgts, 332 -addles, 332 -addals, 332 -addlos, 332 -addccs, 332 -addhss, 332 -addcss, 332 -addnvs, 332 -addseq, 332 -addsne, 332 -addsmi, 332 -addspl, 332 -addsvs, 332 -addsvc, 332 -addshi, 332 -addsls, 332 -addsge, 332 -addslt, 332 -addsgt, 332 -addsle, 332 -addsal, 332 -addslo, 332 -addscc, 332 -addshs, 332 -addscs, 332 -addsnv, 332 -addw, 332 -addeq, 332 -addne, 332 -addmi, 332 -addpl, 332 -addvs, 332 -addvc, 332 -addhi, 332 -addls, 332 -addge, 332 -addlt, 332 -addgt, 332 -addle, 332 -addal, 332 -addlo, 332 -addcc, 332 -addhs, 332 -addcs, 332 -addnv, 332 -adr, 344 -adreq, 344 -adrne, 344 -adrmi, 344 -adrpl, 344 -adrvs, 344 -adrvc, 344 -adrhi, 344 -adrls, 344 -adrge, 344 -adrlt, 344 -adrgt, 344 -adrle, 344 -adral, 344 -adrlo, 344 -adrcc, 344 -adrhs, 344 -adrcs, 344 -adrnv, 344 -and, 346 -andeq, 346 -andne, 346 -andmi, 346 -andpl, 346 -andvs, 346 -andvc, 346 -andhi, 346 -andls, 346 -andge, 346 -andlt, 346 -andgt, 346 -andle, 346 -andal, 346 -andlo, 346 -andcc, 346 -andhs, 346 -andcs, 346 -andnv, 346 -ands, 346 -andeqs, 346 -andnes, 346 -andmis, 346 -andpls, 346 -andvss, 346 -andvcs, 346 -andhis, 346 -andlss, 346 -andges, 346 -andlts, 346 -andgts, 346 -andles, 346 -andals, 346 -andlos, 346 -andccs, 346 -andhss, 346 -andcss, 346 -andnvs, 346 -andseq, 346 -andsne, 346 -andsmi, 346 -andspl, 346 -andsvs, 346 -andsvc, 346 -andshi, 346 -andsls, 346 -andsge, 346 -andslt, 346 -andsgt, 346 -andsle, 346 -andsal, 346 -andslo, 346 -andscc, 346 -andshs, 346 -andscs, 346 -andsnv, 346 -asr, 352 -asreq, 352 -asrne, 352 -asrmi, 352 -asrpl, 352 -asrvs, 352 -asrvc, 352 -asrhi, 352 -asrls, 352 -asrge, 352 -asrlt, 352 -asrgt, 352 -asrle, 352 -asral, 352 -asrlo, 352 -asrcc, 352 -asrhs, 352 -asrcs, 352 -asrnv, 352 -b, 356 -beq, 356 -bne, 356 -bmi, 356 -bpl, 356 -bvs, 356 -bvc, 356 -bhi, 356 -bls, 356 -bge, 356 -blt, 356 -bgt, 356 -ble, 356 -bal, 356 -blo, 356 -bcc, 356 -bhs, 356 -bcs, 356 -bnv, 356 -bfc, 358 -bfceq, 358 -bfcne, 358 -bfcmi, 358 -bfcpl, 358 -bfcvs, 358 -bfcvc, 358 -bfchi, 358 -bfcls, 358 -bfcge, 358 -bfclt, 358 -bfcgt, 358 -bfcle, 358 -bfcal, 358 -bfclo, 358 -bfccc, 358 -bfchs, 358 -bfccs, 358 -bfcnv, 358 -bfi, 360 -bfieq, 360 -bfine, 360 -bfimi, 360 -bfipl, 360 -bfivs, 360 -bfivc, 360 -bfihi, 360 -bfils, 360 -bfige, 360 -bfilt, 360 -bfigt, 360 -bfile, 360 -bfial, 360 -bfilo, 360 -bficc, 360 -bfihs, 360 -bfics, 360 -bfinv, 360 -bic, 362 -biceq, 362 -bicne, 362 -bicmi, 362 -bicpl, 362 -bicvs, 362 -bicvc, 362 -bichi, 362 -bicls, 362 -bicge, 362 -biclt, 362 -bicgt, 362 -bicle, 362 -bical, 362 -biclo, 362 -biccc, 362 -bichs, 362 -biccs, 362 -bicnv, 362 -bics, 362 -biceqs, 362 -bicnes, 362 -bicmis, 362 -bicpls, 362 -bicvss, 362 -bicvcs, 362 -bichis, 362 -biclss, 362 -bicges, 362 -biclts, 362 -bicgts, 362 -bicles, 362 -bicals, 362 -biclos, 362 -bicccs, 362 -bichss, 362 -biccss, 362 -bicnvs, 362 -bicseq, 362 -bicsne, 362 -bicsmi, 362 -bicspl, 362 -bicsvs, 362 -bicsvc, 362 -bicshi, 362 -bicsls, 362 -bicsge, 362 -bicslt, 362 -bicsgt, 362 -bicsle, 362 -bicsal, 362 -bicslo, 362 -bicscc, 362 -bicshs, 362 -bicscs, 362 -bicsnv, 362 -bkpt, 368 -bl, 370 -bleq, 370 -blne, 370 -blmi, 370 -blpl, 370 -blvs, 370 -blvc, 370 -blhi, 370 -blls, 370 -blge, 370 -bllt, 370 -blgt, 370 -blle, 370 -blal, 370 -bllo, 370 -blcc, 370 -blhs, 370 -blcs, 370 -blnv, 370 -blx, 370 -blxeq, 370 -blxne, 370 -blxmi, 370 -blxpl, 370 -blxvs, 370 -blxvc, 370 -blxhi, 370 -blxls, 370 -blxge, 370 -blxlt, 370 -blxgt, 370 -blxle, 370 -blxal, 370 -blxlo, 370 -blxcc, 370 -blxhs, 370 -blxcs, 370 -blxnv, 370 -bx, 374 -bxeq, 374 -bxne, 374 -bxmi, 374 -bxpl, 374 -bxvs, 374 -bxvc, 374 -bxhi, 374 -bxls, 374 -bxge, 374 -bxlt, 374 -bxgt, 374 -bxle, 374 -bxal, 374 -bxlo, 374 -bxcc, 374 -bxhs, 374 -bxcs, 374 -bxnv, 374 -bxj, 376 -bxjeq, 376 -bxjne, 376 -bxjmi, 376 -bxjpl, 376 -bxjvs, 376 -bxjvc, 376 -bxjhi, 376 -bxjls, 376 -bxjge, 376 -bxjlt, 376 -bxjgt, 376 -bxjle, 376 -bxjal, 376 -bxjlo, 376 -bxjcc, 376 -bxjhs, 376 -bxjcs, 376 -bxjnv, 376 -cbnz, 378 -cbz, 378 -cdp, 380 -cdpeq, 380 -cdpne, 380 -cdpmi, 380 -cdppl, 380 -cdpvs, 380 -cdpvc, 380 -cdphi, 380 -cdpls, 380 -cdpge, 380 -cdplt, 380 -cdpgt, 380 -cdple, 380 -cdpal, 380 -cdplo, 380 -cdpcc, 380 -cdphs, 380 -cdpcs, 380 -cdpnv, 380 -cdp2, 380 -cdp2eq, 380 -cdp2ne, 380 -cdp2mi, 380 -cdp2pl, 380 -cdp2vs, 380 -cdp2vc, 380 -cdp2hi, 380 -cdp2ls, 380 -cdp2ge, 380 -cdp2lt, 380 -cdp2gt, 380 -cdp2le, 380 -cdp2al, 380 -cdp2lo, 380 -cdp2cc, 380 -cdp2hs, 380 -cdp2cs, 380 -cdp2nv, 380 -chka, 1141 -clrex, 382 -clrexeq, 382 -clrexne, 382 -clrexmi, 382 -clrexpl, 382 -clrexvs, 382 -clrexvc, 382 -clrexhi, 382 -clrexls, 382 -clrexge, 382 -clrexlt, 382 -clrexgt, 382 -clrexle, 382 -clrexal, 382 -clrexlo, 382 -clrexcc, 382 -clrexhs, 382 -clrexcs, 382 -clrexnv, 382 -clz, 384 -clzeq, 384 -clzne, 384 -clzmi, 384 -clzpl, 384 -clzvs, 384 -clzvc, 384 -clzhi, 384 -clzls, 384 -clzge, 384 -clzlt, 384 -clzgt, 384 -clzle, 384 -clzal, 384 -clzlo, 384 -clzcc, 384 -clzhs, 384 -clzcs, 384 -clznv, 384 -cmn, 386 -cmneq, 386 -cmnne, 386 -cmnmi, 386 -cmnpl, 386 -cmnvs, 386 -cmnvc, 386 -cmnhi, 386 -cmnls, 386 -cmnge, 386 -cmnlt, 386 -cmngt, 386 -cmnle, 386 -cmnal, 386 -cmnlo, 386 -cmncc, 386 -cmnhs, 386 -cmncs, 386 -cmnnv, 386 -cmp, 392 -cmpeq, 392 -cmpne, 392 -cmpmi, 392 -cmppl, 392 -cmpvs, 392 -cmpvc, 392 -cmphi, 392 -cmpls, 392 -cmpge, 392 -cmplt, 392 -cmpgt, 392 -cmple, 392 -cmpal, 392 -cmplo, 392 -cmpcc, 392 -cmphs, 392 -cmpcs, 392 -cmpnv, 392 -cps, 1561 -cpy, 398 -dbg, 400 -dbgeq, 400 -dbgne, 400 -dbgmi, 400 -dbgpl, 400 -dbgvs, 400 -dbgvc, 400 -dbghi, 400 -dbgls, 400 -dbgge, 400 -dbglt, 400 -dbggt, 400 -dbgle, 400 -dbgal, 400 -dbglo, 400 -dbgcc, 400 -dbghs, 400 -dbgcs, 400 -dbgnv, 400 -dmb, 402 -dmbeq, 402 -dmbne, 402 -dmbmi, 402 -dmbpl, 402 -dmbvs, 402 -dmbvc, 402 -dmbhi, 402 -dmbls, 402 -dmbge, 402 -dmblt, 402 -dmbgt, 402 -dmble, 402 -dmbal, 402 -dmblo, 402 -dmbcc, 402 -dmbhs, 402 -dmbcs, 402 -dmbnv, 402 -dsb, 404 -dsbeq, 404 -dsbne, 404 -dsbmi, 404 -dsbpl, 404 -dsbvs, 404 -dsbvc, 404 -dsbhi, 404 -dsbls, 404 -dsbge, 404 -dsblt, 404 -dsbgt, 404 -dsble, 404 -dsbal, 404 -dsblo, 404 -dsbcc, 404 -dsbhs, 404 -dsbcs, 404 -dsbnv, 404 -enterx, 1133 -eor, 406 -eoreq, 406 -eorne, 406 -eormi, 406 -eorpl, 406 -eorvs, 406 -eorvc, 406 -eorhi, 406 -eorls, 406 -eorge, 406 -eorlt, 406 -eorgt, 406 -eorle, 406 -eoral, 406 -eorlo, 406 -eorcc, 406 -eorhs, 406 -eorcs, 406 -eornv, 406 -eors, 406 -eoreqs, 406 -eornes, 406 -eormis, 406 -eorpls, 406 -eorvss, 406 -eorvcs, 406 -eorhis, 406 -eorlss, 406 -eorges, 406 -eorlts, 406 -eorgts, 406 -eorles, 406 -eorals, 406 -eorlos, 406 -eorccs, 406 -eorhss, 406 -eorcss, 406 -eornvs, 406 -eorseq, 406 -eorsne, 406 -eorsmi, 406 -eorspl, 406 -eorsvs, 406 -eorsvc, 406 -eorshi, 406 -eorsls, 406 -eorsge, 406 -eorslt, 406 -eorsgt, 406 -eorsle, 406 -eorsal, 406 -eorslo, 406 -eorscc, 406 -eorshs, 406 -eorscs, 406 -eorsnv, 406 -hb, 1142 -hbeq, 1142 -hbne, 1142 -hbmi, 1142 -hbpl, 1142 -hbvs, 1142 -hbvc, 1142 -hbhi, 1142 -hbls, 1142 -hbge, 1142 -hblt, 1142 -hbgt, 1142 -hble, 1142 -hbal, 1142 -hblo, 1142 -hbcc, 1142 -hbhs, 1142 -hbcs, 1142 -hbnv, 1142 -hbl, 1142 -hbleq, 1142 -hblne, 1142 -hblmi, 1142 -hblpl, 1142 -hblvs, 1142 -hblvc, 1142 -hblhi, 1142 -hblls, 1142 -hblge, 1142 -hbllt, 1142 -hblgt, 1142 -hblle, 1142 -hblal, 1142 -hbllo, 1142 -hblcc, 1142 -hblhs, 1142 -hblcs, 1142 -hblnv, 1142 -hblp, 1143 -hblpeq, 1143 -hblpne, 1143 -hblpmi, 1143 -hblppl, 1143 -hblpvs, 1143 -hblpvc, 1143 -hblphi, 1143 -hblpls, 1143 -hblpge, 1143 -hblplt, 1143 -hblpgt, 1143 -hblple, 1143 -hblpal, 1143 -hblplo, 1143 -hblpcc, 1143 -hblphs, 1143 -hblpcs, 1143 -hblpnv, 1143 -hbp, 1144 -hbpeq, 1144 -hbpne, 1144 -hbpmi, 1144 -hbppl, 1144 -hbpvs, 1144 -hbpvc, 1144 -hbphi, 1144 -hbpls, 1144 -hbpge, 1144 -hbplt, 1144 -hbpgt, 1144 -hbple, 1144 -hbpal, 1144 -hbplo, 1144 -hbpcc, 1144 -hbphs, 1144 -hbpcs, 1144 -hbpnv, 1144 -isb, 414 -isbeq, 414 -isbne, 414 -isbmi, 414 -isbpl, 414 -isbvs, 414 -isbvc, 414 -isbhi, 414 -isbls, 414 -isbge, 414 -isblt, 414 -isbgt, 414 -isble, 414 -isbal, 414 -isblo, 414 -isbcc, 414 -isbhs, 414 -isbcs, 414 -isbnv, 414 -it, 416 -itT, 416 -itE, 416 -itTT, 416 -itET, 416 -itTE, 416 -itEE, 416 -itTTT, 416 -itETT, 416 -itTET, 416 -itEET, 416 -itTTE, 416 -itETE, 416 -itTEE, 416 -itEEE, 416 -ldc, 418 -ldceq, 418 -ldcne, 418 -ldcmi, 418 -ldcpl, 418 -ldcvs, 418 -ldcvc, 418 -ldchi, 418 -ldcls, 418 -ldcge, 418 -ldclt, 418 -ldcgt, 418 -ldcle, 418 -ldcal, 418 -ldclo, 418 -ldccc, 418 -ldchs, 418 -ldccs, 418 -ldcnv, 418 -ldcl, 418 -ldceql, 418 -ldcnel, 418 -ldcmil, 418 -ldcpll, 418 -ldcvsl, 418 -ldcvcl, 418 -ldchil, 418 -ldclsl, 418 -ldcgel, 418 -ldcltl, 418 -ldcgtl, 418 -ldclel, 418 -ldcall, 418 -ldclol, 418 -ldcccl, 418 -ldchsl, 418 -ldccsl, 418 -ldcnvl, 418 -ldcleq, 418 -ldclne, 418 -ldclmi, 418 -ldclpl, 418 -ldclvs, 418 -ldclvc, 418 -ldclhi, 418 -ldclls, 418 -ldclge, 418 -ldcllt, 418 -ldclgt, 418 -ldclle, 418 -ldclal, 418 -ldcllo, 418 -ldclcc, 418 -ldclhs, 418 -ldclcs, 418 -ldclnv, 418 -ldc2, 418 -ldc2eq, 418 -ldc2ne, 418 -ldc2mi, 418 -ldc2pl, 418 -ldc2vs, 418 -ldc2vc, 418 -ldc2hi, 418 -ldc2ls, 418 -ldc2ge, 418 -ldc2lt, 418 -ldc2gt, 418 -ldc2le, 418 -ldc2al, 418 -ldc2lo, 418 -ldc2cc, 418 -ldc2hs, 418 -ldc2cs, 418 -ldc2nv, 418 -ldc2l, 418 -ldc2leq, 418 -ldc2lne, 418 -ldc2lmi, 418 -ldc2lpl, 418 -ldc2lvs, 418 -ldc2lvc, 418 -ldc2lhi, 418 -ldc2lls, 418 -ldc2lge, 418 -ldc2llt, 418 -ldc2lgt, 418 -ldc2lle, 418 -ldc2lal, 418 -ldc2llo, 418 -ldc2lcc, 418 -ldc2lhs, 418 -ldc2lcs, 418 -ldc2lnv, 418 -ldm, 422 -ldmeq, 422 -ldmne, 422 -ldmmi, 422 -ldmpl, 422 -ldmvs, 422 -ldmvc, 422 -ldmhi, 422 -ldmls, 422 -ldmge, 422 -ldmlt, 422 -ldmgt, 422 -ldmle, 422 -ldmal, 422 -ldmlo, 422 -ldmcc, 422 -ldmhs, 422 -ldmcs, 422 -ldmnv, 422 -ldmia, 422 -ldmeqia, 422 -ldmneia, 422 -ldmmiia, 422 -ldmplia, 422 -ldmvsia, 422 -ldmvcia, 422 -ldmhiia, 422 -ldmlsia, 422 -ldmgeia, 422 -ldmltia, 422 -ldmgtia, 422 -ldmleia, 422 -ldmalia, 422 -ldmloia, 422 -ldmccia, 422 -ldmhsia, 422 -ldmcsia, 422 -ldmnvia, 422 -ldmfd, 422 -ldmeqfd, 422 -ldmnefd, 422 -ldmmifd, 422 -ldmplfd, 422 -ldmvsfd, 422 -ldmvcfd, 422 -ldmhifd, 422 -ldmlsfd, 422 -ldmgefd, 422 -ldmltfd, 422 -ldmgtfd, 422 -ldmlefd, 422 -ldmalfd, 422 -ldmlofd, 422 -ldmccfd, 422 -ldmhsfd, 422 -ldmcsfd, 422 -ldmnvfd, 422 -ldmda, 424 -ldmdaeq, 424 -ldmdane, 424 -ldmdami, 424 -ldmdapl, 424 -ldmdavs, 424 -ldmdavc, 424 -ldmdahi, 424 -ldmdals, 424 -ldmdage, 424 -ldmdalt, 424 -ldmdagt, 424 -ldmdale, 424 -ldmdaal, 424 -ldmdalo, 424 -ldmdacc, 424 -ldmdahs, 424 -ldmdacs, 424 -ldmdanv, 424 -ldmeqda,424 -ldmneda, 424 -ldmmida, 424 -ldmplda, 424 -ldmvsda, 424 -ldmvcda, 424 -ldmhida, 424 -ldmlsda, 424 -ldmgeda, 424 -ldmltda, 424 -ldmgtda, 424 -ldmleda, 424 -ldmalda, 424 -ldmloda, 424 -ldmccda, 424 -ldmhsda, 424 -ldmcsda, 424 -ldmnvda, 424 -ldmeqfa,424 -ldmnefa, 424 -ldmmifa, 424 -ldmplfa, 424 -ldmvsfa, 424 -ldmvcfa, 424 -ldmhifa, 424 -ldmlsfa, 424 -ldmgefa, 424 -ldmltfa, 424 -ldmgtfa, 424 -ldmlefa, 424 -ldmalfa, 424 -ldmlofa, 424 -ldmccfa, 424 -ldmhsfa, 424 -ldmcsfa, 424 -ldmnvfa, 424 -ldmdb, 426 -ldmdbeq, 426 -ldmdbne, 426 -ldmdbmi, 426 -ldmdbpl, 426 -ldmdbvs, 426 -ldmdbvc, 426 -ldmdbhi, 426 -ldmdbls, 426 -ldmdbge, 426 -ldmdblt, 426 -ldmdbgt, 426 -ldmdble, 426 -ldmdbal, 426 -ldmdblo, 426 -ldmdbcc, 426 -ldmdbhs, 426 -ldmdbcs, 426 -ldmdbnv, 426 -ldmeqdb,426 -ldmnedb, 426 -ldmmidb, 426 -ldmpldb, 426 -ldmvsdb, 426 -ldmvcdb, 426 -ldmhidb, 426 -ldmlsdb, 426 -ldmgedb, 426 -ldmltdb, 426 -ldmgtdb, 426 -ldmledb, 426 -ldmaldb, 426 -ldmlodb, 426 -ldmccdb, 426 -ldmhsdb, 426 -ldmcsdb, 426 -ldmnvdb, 426 -ldmeqea,426 -ldmneea, 426 -ldmmiea, 426 -ldmplea, 426 -ldmvsea, 426 -ldmvcea, 426 -ldmhiea, 426 -ldmlsea, 426 -ldmgeea, 426 -ldmltea, 426 -ldmgtea, 426 -ldmleea, 426 -ldmalea, 426 -ldmloea, 426 -ldmccea, 426 -ldmhsea, 426 -ldmcsea, 426 -ldmnvea, 426 -ldmib, 428 -ldmibeq, 428 -ldmibne, 428 -ldmibmi, 428 -ldmibpl, 428 -ldmibvs, 428 -ldmibvc, 428 -ldmibhi, 428 -ldmibls, 428 -ldmibge, 428 -ldmiblt, 428 -ldmibgt, 428 -ldmible, 428 -ldmibal, 428 -ldmiblo, 428 -ldmibcc, 428 -ldmibhs, 428 -ldmibcs, 428 -ldmibnv, 428 -ldmeqib,428 -ldmneib, 428 -ldmmiib, 428 -ldmplib, 428 -ldmvsib, 428 -ldmvcib, 428 -ldmhiib, 428 -ldmlsib, 428 -ldmgeib, 428 -ldmltib, 428 -ldmgtib, 428 -ldmleib, 428 -ldmalib, 428 -ldmloib, 428 -ldmccib, 428 -ldmhsib, 428 -ldmcsib, 428 -ldmnvib, 428 -ldmeqed,428 -ldmneed, 428 -ldmmied, 428 -ldmpled, 428 -ldmvsed, 428 -ldmvced, 428 -ldmhied, 428 -ldmlsed, 428 -ldmgeed, 428 -ldmlted, 428 -ldmgted, 428 -ldmleed, 428 -ldmaled, 428 -ldmloed, 428 -ldmcced, 428 -ldmhsed, 428 -ldmcsed, 428 -ldmnved, 428 -ldr, 430 -ldreq, 430 -ldrne, 430 -ldrmi, 430 -ldrpl, 430 -ldrvs, 430 -ldrvc, 430 -ldrhi, 430 -ldrls, 430 -ldrge, 430 -ldrlt, 430 -ldrgt, 430 -ldrle, 430 -ldral, 430 -ldrlo, 430 -ldrcc, 430 -ldrhs, 430 -ldrcs, 430 -ldrnv, 430 -ldreqb, 430 -ldrneb, 430 -ldrmib, 430 -ldrplb, 430 -ldrvsb, 430 -ldrvcb, 430 -ldrhib, 430 -ldrlsb, 430 -ldrgeb, 430 -ldrltb, 430 -ldrgtb, 430 -ldrleb, 430 -ldralb, 430 -ldrlob, 430 -ldrccb, 430 -ldrhsb, 430 -ldrcsb, 430 -ldrnvb, 430 -ldrb, 438 -ldrbeq, 438 -ldrbne, 438 -ldrbmi, 438 -ldrbpl, 438 -ldrbvs, 438 -ldrbvc, 438 -ldrbhi, 438 -ldrbls, 438 -ldrbge, 438 -ldrblt, 438 -ldrbgt, 438 -ldrble, 438 -ldrbal, 438 -ldrblo, 438 -ldrbcc, 438 -ldrbhs, 438 -ldrbcs, 438 -ldrbnv, 438 -ldrbt, 446 -ldreqbt, 446 -ldrnebt, 446 -ldrmibt, 446 -ldrplbt, 446 -ldrvsbt, 446 -ldrvcbt, 446 -ldrhibt, 446 -ldrlsbt, 446 -ldrgebt, 446 -ldrltbt, 446 -ldrgtbt, 446 -ldrlebt, 446 -ldralbt, 446 -ldrlobt, 446 -ldrccbt, 446 -ldrhsbt, 446 -ldrcsbt, 446 -ldrnvbt, 446 -ldrbteq,446 -ldrbtne, 446 -ldrbtmi, 446 -ldrbtpl, 446 -ldrbtvs, 446 -ldrbtvc, 446 -ldrbthi, 446 -ldrbtls, 446 -ldrbtge, 446 -ldrbtlt, 446 -ldrbtgt, 446 -ldrbtle, 446 -ldrbtal, 446 -ldrbtlo, 446 -ldrbtcc, 446 -ldrbths, 446 -ldrbtcs, 446 -ldrbtnv, 446 -ldrd, 448 -ldreqd, 448 -ldrned, 448 -ldrmid, 448 -ldrpld, 448 -ldrvsd, 448 -ldrvcd, 448 -ldrhid, 448 -ldrlsd, 448 -ldrged, 448 -ldrltd, 448 -ldrgtd, 448 -ldrled, 448 -ldrald, 448 -ldrlod, 448 -ldrccd, 448 -ldrhsd, 448 -ldrcsd, 448 -ldrnvd, 448 -ldrdeq, 448 -ldrdne, 448 -ldrdmi, 448 -ldrdpl, 448 -ldrdvs, 448 -ldrdvc, 448 -ldrdhi, 448 -ldrdls, 448 -ldrdge, 448 -ldrdlt, 448 -ldrdgt, 448 -ldrdle, 448 -ldrdal, 448 -ldrdlo, 448 -ldrdcc, 448 -ldrdhs, 448 -ldrdcs, 448 -ldrdnv, 448 -ldrex, 454 -ldrexeq, 454 -ldrexne, 454 -ldrexmi, 454 -ldrexpl, 454 -ldrexvs, 454 -ldrexvc, 454 -ldrexhi, 454 -ldrexls, 454 -ldrexge, 454 -ldrexlt, 454 -ldrexgt, 454 -ldrexle, 454 -ldrexal, 454 -ldrexlo, 454 -ldrexcc, 454 -ldrexhs, 454 -ldrexcs, 454 -ldrexnv, 454 -ldrexb, 456 -ldrexbeq, 456 -ldrexbne, 456 -ldrexbmi, 456 -ldrexbpl, 456 -ldrexbvs, 456 -ldrexbvc, 456 -ldrexbhi, 456 -ldrexbls, 456 -ldrexbge, 456 -ldrexblt, 456 -ldrexbgt, 456 -ldrexble, 456 -ldrexbal, 456 -ldrexblo, 456 -ldrexbcc, 456 -ldrexbhs, 456 -ldrexbcs, 456 -ldrexbnv, 456 -ldrexd, 458 -ldrexdeq, 458 -ldrexdne, 458 -ldrexdmi, 458 -ldrexdpl, 458 -ldrexdvs, 458 -ldrexdvc, 458 -ldrexdhi, 458 -ldrexdls, 458 -ldrexdge, 458 -ldrexdlt, 458 -ldrexdgt, 458 -ldrexdle, 458 -ldrexdal, 458 -ldrexdlo, 458 -ldrexdcc, 458 -ldrexdhs, 458 -ldrexdcs, 458 -ldrexdnv, 458 -ldrexh, 460 -ldrexheq, 460 -ldrexhne, 460 -ldrexhmi, 460 -ldrexhpl, 460 -ldrexhvs, 460 -ldrexhvc, 460 -ldrexhhi, 460 -ldrexhls, 460 -ldrexhge, 460 -ldrexhlt, 460 -ldrexhgt, 460 -ldrexhle, 460 -ldrexhal, 460 -ldrexhlo, 460 -ldrexhcc, 460 -ldrexhhs, 460 -ldrexhcs, 460 -ldrexhnv, 460 -ldrh, 462 -ldreqh, 462 -ldrneh, 462 -ldrmih, 462 -ldrplh, 462 -ldrvsh, 462 -ldrvch, 462 -ldrhih, 462 -ldrlsh, 462 -ldrgeh, 462 -ldrlth, 462 -ldrgth, 462 -ldrleh, 462 -ldralh, 462 -ldrloh, 462 -ldrcch, 462 -ldrhsh, 462 -ldrcsh, 462 -ldrnvh, 462 -ldrheq, 462 -ldrhne, 462 -ldrhmi, 462 -ldrhpl, 462 -ldrhvs, 462 -ldrhvc, 462 -ldrhhi, 462 -ldrhls, 462 -ldrhge, 462 -ldrhlt, 462 -ldrhgt, 462 -ldrhle, 462 -ldrhal, 462 -ldrhlo, 462 -ldrhcc, 462 -ldrhhs, 462 -ldrhcs, 462 -ldrhnv, 462 -ldrht, 470 -ldrhteq, 470 -ldrhtne, 470 -ldrhtmi, 470 -ldrhtpl, 470 -ldrhtvs, 470 -ldrhtvc, 470 -ldrhthi, 470 -ldrhtls, 470 -ldrhtge, 470 -ldrhtlt, 470 -ldrhtgt, 470 -ldrhtle, 470 -ldrhtal, 470 -ldrhtlo, 470 -ldrhtcc, 470 -ldrhths, 470 -ldrhtcs, 470 -ldrhtnv, 470 -ldrsb, 472 -ldreqsb, 472 -ldrnesb, 472 -ldrmisb, 472 -ldrplsb, 472 -ldrvssb, 472 -ldrvcsb, 472 -ldrhisb, 472 -ldrlssb, 472 -ldrgesb, 472 -ldrltsb, 472 -ldrgtsb, 472 -ldrlesb, 472 -ldralsb, 472 -ldrlosb, 472 -ldrccsb, 472 -ldrhssb, 472 -ldrcssb, 472 -ldrnvsb, 472 -ldrsbeq,472 -ldrsbne, 472 -ldrsbmi, 472 -ldrsbpl, 472 -ldrsbvs, 472 -ldrsbvc, 472 -ldrsbhi, 472 -ldrsbls, 472 -ldrsbge, 472 -ldrsblt, 472 -ldrsbgt, 472 -ldrsble, 472 -ldrsbal, 472 -ldrsblo, 472 -ldrsbcc, 472 -ldrsbhs, 472 -ldrsbcs, 472 -ldrsbnv, 472 -ldrsbt, 478 -ldrsbteq, 478 -ldrsbne, 478 -ldrsbmi, 478 -ldrsbpl, 478 -ldrsbvs, 478 -ldrsbvc, 478 -ldrsbhi, 478 -ldrsbls, 478 -ldrsbge, 478 -ldrsblt, 478 -ldrsbgt, 478 -ldrsble, 478 -ldrsbal, 478 -ldrsblo, 478 -ldrsbcc, 478 -ldrsbhs, 478 -ldrsbcs, 478 -ldrsbnv, 478 -ldrsh, 480 -ldreqsh, 480 -ldrnesh, 480 -ldrmish, 480 -ldrplsh, 480 -ldrvssh, 480 -ldrvcsh, 480 -ldrhish, 480 -ldrlssh, 480 -ldrgesh, 480 -ldrltsh, 480 -ldrgtsh, 480 -ldrlesh, 480 -ldralsh, 480 -ldrlosh, 480 -ldrccsh, 480 -ldrhssh, 480 -ldrcshs, 480 -ldrnvsh, 480 -ldrsheq,480 -ldrshne, 480 -ldrshmi, 480 -ldrshpl, 480 -ldrshvs, 480 -ldrshvc, 480 -ldrshhi, 480 -ldrshls, 480 -ldrshge, 480 -ldrshlt, 480 -ldrshgt, 480 -ldrshle, 480 -ldrshal, 480 -ldrshlo, 480 -ldrshcc, 480 -ldrshhs, 480 -ldrshcs, 480 -ldrshnv, 480 -ldrsht, 486 -ldrshteq, 486 -ldrshtne, 486 -ldrshtmi, 486 -ldrshtpl, 486 -ldrshtvs, 486 -ldrshtvc, 486 -ldrshthi, 486 -ldrshtls, 486 -ldrshtge, 486 -ldrshtlt, 486 -ldrshtgt, 486 -ldrshtle, 486 -ldrshtal, 486 -ldrshtlo, 486 -ldrshtcc, 486 -ldrshths, 486 -ldrshtcs, 486 -ldrshtnv, 486 -ldrt, 488 -ldreqt, 488 -ldrnet, 488 -ldrmit, 488 -ldrplt, 488 -ldrvst, 488 -ldrvct, 488 -ldrhit, 488 -ldrlst, 488 -ldrget, 488 -ldrltt, 488 -ldrgtt, 488 -ldrlet, 488 -ldralt, 488 -ldrlot, 488 -ldrcct, 488 -ldrhst, 488 -ldrcst, 488 -ldrnvt, 488 -ldrteq, 488 -ldrtne, 488 -ldrtmi, 488 -ldrtpl, 488 -ldrtvs, 488 -ldrtvc, 488 -ldrthi, 488 -ldrtls, 488 -ldrtge, 488 -ldrtlt, 488 -ldrtgt, 488 -ldrtle, 488 -ldrtal, 488 -ldrtlo, 488 -ldrtcc, 488 -ldrths, 488 -ldrtcs, 488 -ldrtnv, 488 -leavex, 1133 -lsl, 490 -lsleq, 490 -lslne, 490 -lslmi, 490 -lslpl, 490 -lslvs, 490 -lslvc, 490 -lslhi, 490 -lslls, 490 -lslge, 490 -lsllt, 490 -lslgt, 490 -lslle, 490 -lslal, 490 -lsllo, 490 -lslcc, 490 -lslhs, 490 -lslcs, 490 -lslnv, 490 -lsls, 490 -lsleqs, 490 -lslnes, 490 -lslmis, 490 -lslpls, 490 -lslvss, 490 -lslvcs, 490 -lslhis, 490 -lsllss, 490 -lslges, 490 -lsllts, 490 -lslgts, 490 -lslles, 490 -lslals, 490 -lsllos, 490 -lslccs, 490 -lslhss, 490 -lslcss, 490 -lslnvs, 490 -lsr, 494 -lsreq, 494 -lsrne, 494 -lsrmi, 494 -lsrpl, 494 -lsrvs, 494 -lsrvc, 494 -lsrhi, 494 -lsrls, 494 -lsrge, 494 -lsrlt, 494 -lsrgt, 494 -lsrle, 494 -lsral, 494 -lsrlo, 494 -lsrcc, 494 -lsrhs, 494 -lsrcs, 494 -lsrnv, 494 -lsrs, 494 -lsreqs, 494 -lsrnes, 494 -lsrmis, 494 -lsrpls, 494 -lsrvss, 494 -lsrvcs, 494 -lsrhis, 494 -lsrlss, 494 -lsrges, 494 -lsrlts, 494 -lsrgts, 494 -lsrles, 494 -lsrals, 494 -lsrlos, 494 -lsrccs, 494 -lsrhss, 494 -lsrcss, 494 -lsrnvs, 494 -mcr, 498 -mcreq, 498 -mcrne, 498 -mcrmi, 498 -mcrpl, 498 -mcrvs, 498 -mcrvc, 498 -mcrhi, 498 -mcrls, 498 -mcrge, 498 -mcrlt, 498 -mcrgt, 498 -mcrle, 498 -mcral, 498 -mcrlo, 498 -mcrcc, 498 -mcrhs, 498 -mcrcs, 498 -mcrnv, 498 -mcr2, 498 -mcr2eq, 498 -mcr2ne, 498 -mcr2mi, 498 -mcr2pl, 498 -mcr2vs, 498 -mcr2vc, 498 -mcr2hi, 498 -mcr2ls, 498 -mcr2ge, 498 -mcr2lt, 498 -mcr2gt, 498 -mcr2le, 498 -mcr2al, 498 -mcr2lo, 498 -mcr2cc, 498 -mcr2hs, 498 -mcr2cs, 498 -mcr2nv, 498 -mcrr, 500 -mcrreq, 500 -mcrrne, 500 -mcrrmi, 500 -mcrrpl, 500 -mcrrvs, 500 -mcrrvc, 500 -mcrrhi, 500 -mcrrls, 500 -mcrrge, 500 -mcrrlt, 500 -mcrrgt, 500 -mcrrle, 500 -mcrral, 500 -mcrrlo, 500 -mcrrcc, 500 -mcrrhs, 500 -mcrrcs, 500 -mcrrnv, 500 -mcrr2, 500 -mcrr2eq, 500 -mcrr2ne, 500 -mcrr2mi, 500 -mcrr2pl, 500 -mcrr2vs, 500 -mcrr2vc, 500 -mcrr2hi, 500 -mcrr2ls, 500 -mcrr2ge, 500 -mcrr2lt, 500 -mcrr2gt, 500 -mcrr2le, 500 -mcrr2al, 500 -mcrr2lo, 500 -mcrr2cc, 500 -mcrr2hs, 500 -mcrr2cs, 500 -mcrr2nv, 500 -mla, 502 -mlaeq, 502 -mlane, 502 -mlami, 502 -mlapl, 502 -mlavs, 502 -mlavc, 502 -mlahi, 502 -mlals, 502 -mlage, 502 -mlalt, 502 -mlagt, 502 -mlale, 502 -mlaal, 502 -mlalo, 502 -mlacc, 502 -mlahs, 502 -mlacs, 502 -mlanv, 502 -mlas, 502 -mlaeqs, 502 -mlanes, 502 -mlamis, 502 -mlapls, 502 -mlavss, 502 -mlavcs, 502 -mlahis, 502 -mlalss, 502 -mlages, 502 -mlalts, 502 -mlagts, 502 -mlales, 502 -mlaals, 502 -mlalos, 502 -mlaccs, 502 -mlahss, 502 -mlacss, 502 -mlanvs, 502 -mlaseq, 502 -mlasne, 502 -mlasmi, 502 -mlaspl, 502 -mlasvs, 502 -mlasvc, 502 -mlashi, 502 -mlasls, 502 -mlasge, 502 -mlaslt, 502 -mlasgt, 502 -mlasle, 502 -mlasal, 502 -mlaslo, 502 -mlascc, 502 -mlashs, 502 -mlascs, 502 -mlasnv, 502 -mls, 504 -mlseq, 504 -mlsne, 504 -mlsmi, 504 -mlspl, 504 -mlsvs, 504 -mlsvc, 504 -mlshi, 504 -mlsls, 504 -mlsge, 504 -mlslt, 504 -mlsgt, 504 -mlsle, 504 -mlsal, 504 -mlslo, 504 -mlscc, 504 -mlshs, 504 -mlscs, 504 -mlsnv, 504 -mov, 506 -moveq, 506 -movne, 506 -movmi, 506 -movpl, 506 -movvs, 506 -movvc, 506 -movhi, 506 -movls, 506 -movge, 506 -movlt, 506 -movgt, 506 -movle, 506 -moval, 506 -movlo, 506 -movcc, 506 -movhs, 506 -movcs, 506 -movnv, 506 -movs, 506 -moveqs, 506 -movnes, 506 -movmis, 506 -movpls, 506 -movvss, 506 -movvcs, 506 -movhis, 506 -movlss, 506 -movges, 506 -movlts, 506 -movgts, 506 -movles, 506 -movals, 506 -movlos, 506 -movccs, 506 -movhss, 506 -movcss, 506 -movnvs, 506 -movseq, 506 -movsne, 506 -movsmi, 506 -movspl, 506 -movsvs, 506 -movsvc, 506 -movshi, 506 -movsls, 506 -movsge, 506 -movslt, 506 -movsgt, 506 -movsle, 506 -movsal, 506 -movslo, 506 -movscc, 506 -movshs, 506 -movscs, 506 -movsnv, 506 -movw, 506 -movweq, 506 -movwne, 506 -movwmi, 506 -movwpl, 506 -movwvs, 506 -movwvc, 506 -movwhi, 506 -movwls, 506 -movwge, 506 -movwlt, 506 -movwgt, 506 -movwle, 506 -movwal, 506 -movwlo, 506 -movwcc, 506 -movwhs, 506 -movwcs, 506 -movwnv, 506 -movt, 512 -moveqt, 512 -movnet, 512 -movmit, 512 -movplt, 512 -movvst, 512 -movvct, 512 -movhit, 512 -movlst, 512 -movget, 512 -movltt, 512 -movgtt, 512 -movlet, 512 -movalt, 512 -movlot, 512 -movcct, 512 -movhst, 512 -movcst, 512 -movnvt, 512 -mrc, 514 -mrceq, 514 -mrcne, 514 -mrcmi, 514 -mrcpl, 514 -mrcvs, 514 -mrcvc, 514 -mrchi, 514 -mrcls, 514 -mrcge, 514 -mrclt, 514 -mrcgt, 514 -mrcle, 514 -mrcal, 514 -mrclo, 514 -mrccc, 514 -mrchs, 514 -mrccs, 514 -mrcnv, 514 -mrc2, 514 -mrc2eq, 514 -mrc2ne, 514 -mrc2mi, 514 -mrc2pl, 514 -mrc2vs, 514 -mrc2vc, 514 -mrc2hi, 514 -mrc2ls, 514 -mrc2ge, 514 -mrc2lt, 514 -mrc2gt, 514 -mrc2le, 514 -mrc2al, 514 -mrc2lo, 514 -mrc2cc, 514 -mrc2hs, 514 -mrc2cs, 514 -mrc2nv, 514 -mrrc, 516 -mrrceq, 516 -mrrcne, 516 -mrrcmi, 516 -mrrcpl, 516 -mrrcvs, 516 -mrrcvc, 516 -mrrchi, 516 -mrrcls, 516 -mrrcge, 516 -mrrclt, 516 -mrrcgt, 516 -mrrcle, 516 -mrrcal, 516 -mrrclo, 516 -mrrccc, 516 -mrrchs, 516 -mrrccs, 516 -mrrcnv, 516 -mrrc2, 516 -mrrc2eq, 516 -mrrc2ne, 516 -mrrc2mi, 516 -mrrc2pl, 516 -mrrc2vs, 516 -mrrc2vc, 516 -mrrc2hi, 516 -mrrc2ls, 516 -mrrc2ge, 516 -mrrc2lt, 516 -mrrc2gt, 516 -mrrc2le, 516 -mrrc2al, 516 -mrrc2lo, 516 -mrrc2cc, 516 -mrrc2hs, 516 -mrrc2cs, 516 -mrrc2nv, 516 -mrs, 518 -mrseq, 518 -mrsne, 518 -mrsmi, 518 -mrspl, 518 -mrsvs, 518 -mrsvc, 518 -mrshi, 518 -mrsls, 518 -mrsge, 518 -mrslt, 518 -mrsgt, 518 -mrsle, 518 -mrsal, 518 -mrslo, 518 -mrscc, 518 -mrshs, 518 -mrscs, 518 -mrsnv, 518 -msr, 520 -msreq, 520 -msrne, 520 -msrmi, 520 -msrpl, 520 -msrvs, 520 -msrvc, 520 -msrhi, 520 -msrls, 520 -msrge, 520 -msrlt, 520 -msrgt, 520 -msrle, 520 -msral, 520 -msrlo, 520 -msrcc, 520 -msrhs, 520 -msrcs, 520 -msrnv, 520 -mul, 524 -muleq, 524 -mulne, 524 -mulmi, 524 -mulpl, 524 -mulvs, 524 -mulvc, 524 -mulhi, 524 -mulls, 524 -mulge, 524 -mullt, 524 -mulgt, 524 -mulle, 524 -mulal, 524 -mullo, 524 -mulcc, 524 -mulhs, 524 -mulcs, 524 -mulnv, 524 -muls, 524 -muleqs, 524 -mulnes, 524 -mulmis, 524 -mulpls, 524 -mulvss, 524 -mulvcs, 524 -mulhis, 524 -mullss, 524 -mulges, 524 -mullts, 524 -mulgts, 524 -mulles, 524 -mulals, 524 -mullos, 524 -mulccs, 524 -mulhss, 524 -mulcss, 524 -mulnvs, 524 -mvn, 526 -mvneq, 526 -mvnne, 526 -mvnmi, 526 -mvnpl, 526 -mvnvs, 526 -mvnvc, 526 -mvnhi, 526 -mvnls, 526 -mvnge, 526 -mvnlt, 526 -mvngt, 526 -mvnle, 526 -mvnal, 526 -mvnlo, 526 -mvncc, 526 -mvnhs, 526 -mvncs, 526 -mvnnv, 526 -mvns, 526 -mvneqs, 526 -mvnnes, 526 -mvnmis, 526 -mvnpls, 526 -mvnvss, 526 -mvnvcs, 526 -mvnhis, 526 -mvnlss, 526 -mvnges, 526 -mvnlts, 526 -mvngts, 526 -mvnles, 526 -mvnals, 526 -mvnlos, 526 -mvnccs, 526 -mvnhss, 526 -mvncss, 526 -mvnnvs, 526 -mvnseq, 526 -mvnsne, 526 -mvnsmi, 526 -mvnspl, 526 -mvnsvs, 526 -mvnsvc, 526 -mvnshi, 526 -mvnsls, 526 -mvnsge, 526 -mvnslt, 526 -mvnsgt, 526 -mvnsle, 526 -mvnsal, 526 -mvnslo, 526 -mvnscc, 526 -mvnshs, 526 -mvnscs, 526 -mvnsnv, 526 -neg, 532 -nop, 534 -orn, 536 -orneq, 536 -ornne, 536 -ornmi, 536 -ornpl, 536 -ornvs, 536 -ornvc, 536 -ornhi, 536 -ornls, 536 -ornge, 536 -ornlt, 536 -orngt, 536 -ornle, 536 -ornal, 536 -ornlo, 536 -orncc, 536 -ornhs, 536 -orncs, 536 -ornnv, 536 -orns, 536 -orneqs, 536 -ornnes, 536 -ornmis, 536 -ornpls, 536 -ornvss, 536 -ornvcs, 536 -ornhis, 536 -ornlss, 536 -ornges, 536 -ornlts, 536 -orngts, 536 -ornles, 536 -ornals, 536 -ornlos, 536 -ornccs, 536 -ornhss, 536 -orncss, 536 -ornnvs, 536 -orr, 540 -orreq, 540 -orrne, 540 -orrmi, 540 -orrpl, 540 -orrvs, 540 -orrvc, 540 -orrhi, 540 -orrls, 540 -orrge, 540 -orrlt, 540 -orrgt, 540 -orrle, 540 -orral, 540 -orrlo, 540 -orrcc, 540 -orrhs, 540 -orrcs, 540 -orrnv, 540 -orrs, 540 -orreqs, 540 -orrnes, 540 -orrmis, 540 -orrpls, 540 -orrvss, 540 -orrvcs, 540 -orrhis, 540 -orrlss, 540 -orrges, 540 -orrlts, 540 -orrgts, 540 -orrles, 540 -orrals, 540 -orrlos, 540 -orrccs, 540 -orrhss, 540 -orrcss, 540 -orrnvs, 540 -orrseq, 540 -orrsne, 540 -orrsmi, 540 -orrspl, 540 -orrsvs, 540 -orrsvc, 540 -orrshi, 540 -orrsls, 540 -orrsge, 540 -orrslt, 540 -orrsgt, 540 -orrsle, 540 -orrsal, 540 -orrslo, 540 -orrscc, 540 -orrshs, 540 -orrscs, 540 -orrsnv, 540 -pkhbt, 546 -pkhbteq, 546 -pkhbtne, 546 -pkhbtmi, 546 -pkhbtpl, 546 -pkhbtvs, 546 -pkhbtvc, 546 -pkhbthi, 546 -pkhbtls, 546 -pkhbtge, 546 -pkhbtlt, 546 -pkhbtgt, 546 -pkhbtle, 546 -pkhbtal, 546 -pkhbtlo, 546 -pkhbtcc, 546 -pkhbths, 546 -pkhbtcs, 546 -pkhbtnv, 546 -pkhtb, 546 -pkhtbeq, 546 -pkhtbne, 546 -pkhtbmi, 546 -pkhtbpl, 546 -pkhtbvs, 546 -pkhtbvc, 546 -pkhtbhi, 546 -pkhtbls, 546 -pkhtbge, 546 -pkhtblt, 546 -pkhtbgt, 546 -pkhtble, 546 -pkhtbal, 546 -pkhtblo, 546 -pkhtbcc, 546 -pkhtbhs, 546 -pkhtbcs, 546 -pkhtbnv, 546 -pld, 548 -pldeq, 548 -pldne, 548 -pldmi, 548 -pldpl, 548 -pldvs, 548 -pldvc, 548 -pldhi, 548 -pldls, 548 -pldge, 548 -pldlt, 548 -pldgt, 548 -pldle, 548 -pldal, 548 -pldlo, 548 -pldcc, 548 -pldhs, 548 -pldcs, 548 -pldnv, 548 -pldw, 548 -pldweq, 548 -pldwne, 548 -pldwmi, 548 -pldwpl, 548 -pldwvs, 548 -pldwvc, 548 -pldwhi, 548 -pldwls, 548 -pldwge, 548 -pldwlt, 548 -pldwgt, 548 -pldwle, 548 -pldwal, 548 -pldwlo, 548 -pldwcc, 548 -pldwhs, 548 -pldwcs, 548 -pldwnv, 548 -pli, 554 -plieq, 554 -pline, 554 -plimi, 554 -plipl, 554 -plivs, 554 -plivc, 554 -plihi, 554 -plils, 554 -plige, 554 -plilt, 554 -pligt, 554 -plile, 554 -plial, 554 -plilo, 554 -plicc, 554 -plihs, 554 -plics, 554 -plinv, 554 -pop, 558 -popeq, 558 -popne, 558 -popmi, 558 -poppl, 558 -popvs, 558 -popvc, 558 -pophi, 558 -popls, 558 -popge, 558 -poplt, 558 -popgt, 558 -pople, 558 -popal, 558 -poplo, 558 -popcc, 558 -pophs, 558 -popcs, 558 -popnv, 558 -push, 560 -pusheq, 560 -pushne, 560 -pushmi, 560 -pushpl, 560 -pushvs, 560 -pushvc, 560 -pushhi, 560 -pushls, 560 -pushge, 560 -pushlt, 560 -pushgt, 560 -pushle, 560 -pushal, 560 -pushlo, 560 -pushcc, 560 -pushhs, 560 -pushcs, 560 -pushnv, 560 -qadd, 562 -qaddeq, 562 -qaddne, 562 -qaddmi, 562 -qaddpl, 562 -qaddvs, 562 -qaddvc, 562 -qaddhi, 562 -qaddls, 562 -qaddge, 562 -qaddlt, 562 -qaddgt, 562 -qaddle, 562 -qaddal, 562 -qaddlo, 562 -qaddcc, 562 -qaddhs, 562 -qaddcs, 562 -qaddnv, 562 -qadd16, 564 -qadd16eq, 564 -qadd16ne, 564 -qadd16mi, 564 -qadd16pl, 564 -qadd16vs, 564 -qadd16vc, 564 -qadd16hi, 564 -qadd16ls, 564 -qadd16ge, 564 -qadd16lt, 564 -qadd16gt, 564 -qadd16le, 564 -qadd16al, 564 -qadd16lo, 564 -qadd16cc, 564 -qadd16hs, 564 -qadd16cs, 564 -qadd16nv, 564 -qadd8, 566 -qadd8eq, 566 -qadd8ne, 566 -qadd8mi, 566 -qadd8pl, 566 -qadd8vs, 566 -qadd8vc, 566 -qadd8hi, 566 -qadd8ls, 566 -qadd8ge, 566 -qadd8lt, 566 -qadd8gt, 566 -qadd8le, 566 -qadd8al, 566 -qadd8lo, 566 -qadd8cc, 566 -qadd8hs, 566 -qadd8cs, 566 -qadd8nv, 566 -qaddsubx,568 -qaddsubxeq, 568 -qaddsubxne, 568 -qaddsubxmi, 568 -qaddsubxpl, 568 -qaddsubxvs, 568 -qaddsubxvc, 568 -qaddsubxhi, 568 -qaddsubxls, 568 -qaddsubxge, 568 -qaddsubxlt, 568 -qaddsubxgt, 568 -qaddsubxle, 568 -qaddsubxal, 568 -qaddsubxlo, 568 -qaddsubxcc, 568 -qaddsubxhs, 568 -qaddsubxcs, 568 -qaddsubxnv, 568 -qasx, 568 -qasxeq, 568 -qasxne, 568 -qasxmi, 568 -qasxpl, 568 -qasxvs, 568 -qasxvc, 568 -qasxhi, 568 -qasxls, 568 -qasxge, 568 -qasxlt, 568 -qasxgt, 568 -qasxle, 568 -qasxal, 568 -qasxlo, 568 -qasxcc, 568 -qasxhs, 568 -qasxcs, 568 -qasxnv, 568 -qdadd, 570 -qdaddeq, 570 -qdaddne, 570 -qdaddmi, 570 -qdaddpl, 570 -qdaddvs, 570 -qdaddvc, 570 -qdaddhi, 570 -qdaddls, 570 -qdaddge, 570 -qdaddlt, 570 -qdaddgt, 570 -qdaddle, 570 -qdaddal, 570 -qdaddlo, 570 -qdaddcc, 570 -qdaddhs, 570 -qdaddcs, 570 -qdaddnv, 570 -qdsub, 572 -qdsubeq, 572 -qdsubne, 572 -qdsubmi, 572 -qdsubpl, 572 -qdsubvs, 572 -qdsubvc, 572 -qdsubhi, 572 -qdsubls, 572 -qdsubge, 572 -qdsublt, 572 -qdsubgt, 572 -qdsuble, 572 -qdsubal, 572 -qdsublo, 572 -qdsubcc, 572 -qdsubhs, 572 -qdsubcs, 572 -qdsubnv, 572 -qsubaddx,574 -qsubaddxeq, 574 -qsubaddxne, 574 -qsubaddxmi, 574 -qsubaddxpl, 574 -qsubaddxvs, 574 -qsubaddxvc, 574 -qsubaddxhi, 574 -qsubaddxls, 574 -qsubaddxge, 574 -qsubaddxlt, 574 -qsubaddxgt, 574 -qsubaddxle, 574 -qsubaddxal, 574 -qsubaddxlo, 574 -qsubaddxcc, 574 -qsubaddxhs, 574 -qsubaddxcs, 574 -qsubaddxnv, 574 -qsax, 574 -qsaxeq, 574 -qsaxne, 574 -qsaxmi, 574 -qsaxpl, 574 -qsaxvs, 574 -qsaxvc, 574 -qsaxhi, 574 -qsaxls, 574 -qsaxge, 574 -qsaxlt, 574 -qsaxgt, 574 -qsaxle, 574 -qsaxal, 574 -qsaxlo, 574 -qsaxcc, 574 -qsaxhs, 574 -qsaxcs, 574 -qsaxnv, 574 -qsub, 576 -qsubeq, 576 -qsubne, 576 -qsubmi, 576 -qsubpl, 576 -qsubvs, 576 -qsubvc, 576 -qsubhi, 576 -qsubls, 576 -qsubge, 576 -qsublt, 576 -qsubgt, 576 -qsuble, 576 -qsubal, 576 -qsublo, 576 -qsubcc, 576 -qsubhs, 576 -qsubcs, 576 -qsubnv, 576 -qsub16, 578 -qsub16eq, 578 -qsub16ne, 578 -qsub16mi, 578 -qsub16pl, 578 -qsub16vs, 578 -qsub16vc, 578 -qsub16hi, 578 -qsub16ls, 578 -qsub16ge, 578 -qsub16lt, 578 -qsub16gt, 578 -qsub16le, 578 -qsub16al, 578 -qsub16lo, 578 -qsub16cc, 578 -qsub16hs, 578 -qsub16cs, 578 -qsub16nv, 578 -qsub8, 580 -qsub8eq, 580 -qsub8ne, 580 -qsub8mi, 580 -qsub8pl, 580 -qsub8vs, 580 -qsub8vc, 580 -qsub8hi, 580 -qsub8ls, 580 -qsub8ge, 580 -qsub8lt, 580 -qsub8gt, 580 -qsub8le, 580 -qsub8al, 580 -qsub8lo, 580 -qsub8cc, 580 -qsub8hs, 580 -qsub8cs, 580 -qsub8nv, 580 -rbit, 582 -rbiteq, 582 -rbitne, 582 -rbitmi, 582 -rbitpl, 582 -rbitvs, 582 -rbitvc, 582 -rbithi, 582 -rbitls, 582 -rbitge, 582 -rbitlt, 582 -rbitgt, 582 -rbitle, 582 -rbital, 582 -rbitlo, 582 -rbitcc, 582 -rbiths, 582 -rbitcs, 582 -rbitnv, 582 -rev, 584 -reveq, 584 -revne, 584 -revmi, 584 -revpl, 584 -revvs, 584 -revvc, 584 -revhi, 584 -revls, 584 -revge, 584 -revlt, 584 -revgt, 584 -revle, 584 -reval, 584 -revlo, 584 -revcc, 584 -revhs, 584 -revcs, 584 -revnv, 584 -rev16, 586 -rev16eq, 586 -rev16ne, 586 -rev16mi, 586 -rev16pl, 586 -rev16vs, 586 -rev16vc, 586 -rev16hi, 586 -rev16ls, 586 -rev16ge, 586 -rev16lt, 586 -rev16gt, 586 -rev16le, 586 -rev16al, 586 -rev16lo, 586 -rev16cc, 586 -rev16hs, 586 -rev16cs, 586 -rev16nv, 586 -revsh, 588 -revsheq, 588 -revshne, 588 -revshmi, 588 -revshpl, 588 -revshvs, 588 -revshvc, 588 -revshhi, 588 -revshls, 588 -revshge, 588 -revshlt, 588 -revshgt, 588 -revshle, 588 -revshal, 588 -revshlo, 588 -revshcc, 588 -revshhs, 588 -revshcs, 588 -revshnv, 588 -rfeda, `1574 -rfedaeq, 1574 -rfedane, 1574 -rfedami, 1574 -rfedapl, 1574 -rfedavs, 1574 -rfedavc, 1574 -rfedahi, 1574 -rfedals, 1574 -rfedage, 1574 -rfedalt, 1574 -rfedagt, 1574 -rfedale, 1574 -rfedaal, 1574 -rfedalo, 1574 -rfedacc, 1574 -rfedahs, 1574 -rfedacs, 1574 -rfedanv, 1574 -rfedb, 1574 -rfedbeq, 1574 -rfedbne, 1574 -rfedbmi, 1574 -rfedbpl, 1574 -rfedbvs, 1574 -rfedbvc, 1574 -rfedbhi, 1574 -rfedbls, 1574 -rfedbge, 1574 -rfedblt, 1574 -rfedbgt, 1574 -rfedble, 1574 -rfedbal, 1574 -rfedblo, 1574 -rfedbcc, 1574 -rfedbhs, 1574 -rfedbcs, 1574 -rfedbnv, 1574 -rfeia, 1574 -rfeiaeq, 1574 -rfeiane, 1574 -rfeiami, 1574 -rfeiapl, 1574 -rfeiavs, 1574 -rfeiavc, 1574 -rfeiahi, 1574 -rfeials, 1574 -rfeiage, 1574 -rfeialt, 1574 -rfeiagt, 1574 -rfeiale, 1574 -rfeiaal, 1574 -rfeialo, 1574 -rfeiacc, 1574 -rfeiahs, 1574 -rfeiacs, 1574 -rfeianv, 1574 -rfeib, 1574 -rfeibeq, 1574 -rfeibne, 1574 -rfeibmi, 1574 -rfeibpl, 1574 -rfeibvs, 1574 -rfeibvc, 1574 -rfeibhi, 1574 -rfeibls, 1574 -rfeibge, 1574 -rfeiblt, 1574 -rfeibgt, 1574 -rfeible, 1574 -rfeibal, 1574 -rfeiblo, 1574 -rfeibcc, 1574 -rfeibhs, 1574 -rfeibcs, 1574 -rfeibnv, 1574 -ror, 590 -roreq, 590 -rorne, 590 -rormi, 590 -rorpl, 590 -rorvs, 590 -rorvc, 590 -rorhi, 590 -rorls, 590 -rorge, 590 -rorlt, 590 -rorgt, 590 -rorle, 590 -roral, 590 -rorlo, 590 -rorcc, 590 -rorhs, 590 -rorcs, 590 -rornv, 590 -rors, 590 -roreqs, 590 -rornes, 590 -rormis, 590 -rorpls, 590 -rorvss, 590 -rorvcs, 590 -rorhis, 590 -rorlss, 590 -rorges, 590 -rorlts, 590 -rorgts, 590 -rorles, 590 -rorals, 590 -rorlos, 590 -rorccs, 590 -rorhss, 590 -rorcss, 590 -rornvs, 590 -rrx, 594 -rrxeq, 594 -rrxne, 594 -rrxmi, 594 -rrxpl, 594 -rrxvs, 594 -rrxvc, 594 -rrxhi, 594 -rrxls, 594 -rrxge, 594 -rrxlt, 594 -rrxgt, 594 -rrxle, 594 -rrxal, 594 -rrxlo, 594 -rrxcc, 594 -rrxhs, 594 -rrxcs, 594 -rrxnv, 594 -rrxs, 594 -rrxeqs, 594 -rrxnes, 594 -rrxmis, 594 -rrxpls, 594 -rrxvss, 594 -rrxvcs, 594 -rrxhis, 594 -rrxlss, 594 -rrxges, 594 -rrxlts, 594 -rrxgts, 594 -rrxles, 594 -rrxals, 594 -rrxlos, 594 -rrxccs, 594 -rrxhss, 594 -rrxcss, 594 -rrxnvs, 594 -rsb, 596 -rsbeq, 596 -rsbne, 596 -rsbmi, 596 -rsbpl, 596 -rsbvs, 596 -rsbvc, 596 -rsbhi, 596 -rsbls, 596 -rsbge, 596 -rsblt, 596 -rsbgt, 596 -rsble, 596 -rsbal, 596 -rsblo, 596 -rsbcc, 596 -rsbhs, 596 -rsbcs, 596 -rsbnv, 596 -rsbs, 596 -rsbeqs, 596 -rsbnes, 596 -rsbmis, 596 -rsbpls, 596 -rsbvss, 596 -rsbvcs, 596 -rsbhis, 596 -rsblss, 596 -rsbges, 596 -rsblts, 596 -rsbgts, 596 -rsbles, 596 -rsbals, 596 -rsblos, 596 -rsbccs, 596 -rsbhss, 596 -rsbcss, 596 -rsbnvs, 596 -rsbseq, 596 -rsbsne, 596 -rsbsmi, 596 -rsbspl, 596 -rsbsvs, 596 -rsbsvc, 596 -rsbshi, 596 -rsbsls, 596 -rsbsge, 596 -rsbslt, 596 -rsbsgt, 596 -rsbsle, 596 -rsbsal, 596 -rsbslo, 596 -rsbscc, 596 -rsbshs, 596 -rsbscs, 596 -rsbsnv, 596 -rsc, 602 -rsceq, 602 -rscne, 602 -rscmi, 602 -rscpl, 602 -rscvs, 602 -rscvc, 602 -rschi, 602 -rscls, 602 -rscge, 602 -rsclt, 602 -rscgt, 602 -rscle, 602 -rscal, 602 -rsclo, 602 -rsccc, 602 -rschs, 602 -rsccs, 602 -rscnv, 602 -rscs, 602 -rsceqs, 602 -rscnes, 602 -rscmis, 602 -rscpls, 602 -rscvss, 602 -rscvcs, 602 -rschis, 602 -rsclss, 602 -rscges, 602 -rsclts, 602 -rscgts, 602 -rscles, 602 -rscals, 602 -rsclos, 602 -rscccs, 602 -rschss, 602 -rsccss, 602 -rscnvs, 602 -rscseq, 602 -rscsne, 602 -rscsmi, 602 -rscspl, 602 -rscsvs, 602 -rscsvc, 602 -rscshi, 602 -rscsls, 602 -rscsge, 602 -rscslt, 602 -rscsgt, 602 -rscsle, 602 -rscsal, 602 -rscslo, 602 -rscscc, 602 -rscshs, 602 -rscscs, 602 -rscsnv, 602 -sadd16, 608 -sadd16eq, 608 -sadd16ne, 608 -sadd16mi, 608 -sadd16pl, 608 -sadd16vs, 608 -sadd16vc, 608 -sadd16hi, 608 -sadd16ls, 608 -sadd16ge, 608 -sadd16lt, 608 -sadd16gt, 608 -sadd16le, 608 -sadd16al, 608 -sadd16lo, 608 -sadd16cc, 608 -sadd16hs, 608 -sadd16cs, 608 -sadd16nv, 608 -sadd8, 610 -sadd8eq, 610 -sadd8ne, 610 -sadd8mi, 610 -sadd8pl, 610 -sadd8vs, 610 -sadd8vc, 610 -sadd8hi, 610 -sadd8ls, 610 -sadd8ge, 610 -sadd8lt, 610 -sadd8gt, 610 -sadd8le, 610 -sadd8al, 610 -sadd8lo, 610 -sadd8cc, 610 -sadd8hs, 610 -sadd8cs, 610 -sadd8nv, 610 -saddsubx,612 -saddsubxeq, 612 -saddsubxne, 612 -saddsubxmi, 612 -saddsubxpl, 612 -saddsubxvs, 612 -saddsubxvc, 612 -saddsubxhi, 612 -saddsubxls, 612 -saddsubxge, 612 -saddsubxlt, 612 -saddsubxgt, 612 -saddsubxle, 612 -saddsubxal, 612 -saddsubxlo, 612 -saddsubxcc, 612 -saddsubxhs, 612 -saddsubxcs, 612 -saddsubxnv, 612 -sasx, 612 -sasxeq, 612 -sasxne, 612 -sasxmi, 612 -sasxpl, 612 -sasxvs, 612 -sasxvc, 612 -sasxhi, 612 -sasxls, 612 -sasxge, 612 -sasxlt, 612 -sasxgt, 612 -sasxle, 612 -sasxal, 612 -sasxlo, 612 -sasxcc, 612 -sasxhs, 612 -sasxcs, 612 -sasxnv, 612 -sbc, 614 -sbceq, 614 -sbcne, 614 -sbcmi, 614 -sbcpl, 614 -sbcvs, 614 -sbcvc, 614 -sbchi, 614 -sbcls, 614 -sbcge, 614 -sbclt, 614 -sbcgt, 614 -sbcle, 614 -sbcal, 614 -sbclo, 614 -sbccc, 614 -sbchs, 614 -sbccs, 614 -sbcnv, 614 -sbcs, 614 -sbceqs, 614 -sbcnes, 614 -sbcmis, 614 -sbcpls, 614 -sbcvss, 614 -sbcvcs, 614 -sbchis, 614 -sbclss, 614 -sbcges, 614 -sbclts, 614 -sbcgts, 614 -sbcles, 614 -sbcals, 614 -sbclos, 614 -sbcccs, 614 -sbchss, 614 -sbccss, 614 -sbcnvs, 614 -sbcseq, 614 -sbcsne, 614 -sbcsmi, 614 -sbcspl, 614 -sbcsvs, 614 -sbcsvc, 614 -sbcshi, 614 -sbcsls, 614 -sbcsge, 614 -sbcslt, 614 -sbcsgt, 614 -sbcsle, 614 -sbcsal, 614 -sbcslo, 614 -sbcscc, 614 -sbcshs, 614 -sbcscs, 614 -sbcsnv, 614 -sbfx, 620 -sbfxeq, 620 -sbfxne, 620 -sbfxmi, 620 -sbfxpl, 620 -sbfxvs, 620 -sbfxvc, 620 -sbfxhi, 620 -sbfxls, 620 -sbfxge, 620 -sbfxlt, 620 -sbfxgt, 620 -sbfxle, 620 -sbfxal, 620 -sbfxlo, 620 -sbfxcc, 620 -sbfxhs, 620 -sbfxcs, 620 -sbfxnv, 620 -sdiv, 622 -sdiveq, 622 -sdivne, 622 -sdivmi, 622 -sdivpl, 622 -sdivvs, 622 -sdivvc, 622 -sdivhi, 622 -sdivls, 622 -sdivge, 622 -sdivlt, 622 -sdivgt, 622 -sdivle, 622 -sdival, 622 -sdivlo, 622 -sdivcc, 622 -sdivhs, 622 -sdivcs, 622 -sdivnv, 622 -sel, 622 -seleq, 622 -selne, 622 -selmi, 622 -selpl, 622 -selvs, 622 -selvc, 622 -selhi, 622 -sells, 622 -selge, 622 -sellt, 622 -selgt, 622 -selle, 622 -selal, 622 -sello, 622 -selcc, 622 -selhs, 622 -selcs, 622 -selnv, 622 -setend, 626 -sev, 628 -seveq, 628 -sevne, 628 -sevmi, 628 -sevpl, 628 -sevvs, 628 -sevvc, 628 -sevhi, 628 -sevls, 628 -sevge, 628 -sevlt, 628 -sevgt, 628 -sevle, 628 -seval, 628 -sevlo, 628 -sevcc, 628 -sevhs, 628 -sevcs, 628 -sevnv, 628 -shadd16,630 -shadd16eq, 630 -shadd16ne, 630 -shadd16mi, 630 -shadd16pl, 630 -shadd16vs, 630 -shadd16vc, 630 -shadd16hi, 630 -shadd16ls, 630 -shadd16ge, 630 -shadd16lt, 630 -shadd16gt, 630 -shadd16le, 630 -shadd16al, 630 -shadd16lo, 630 -shadd16cc, 630 -shadd16hs, 630 -shadd16cs, 630 -shadd16nv, 630 -shadd8, 632 -shadd8eq, 632 -shadd8ne, 632 -shadd8mi, 632 -shadd8pl, 632 -shadd8vs, 632 -shadd8vc, 632 -shadd8hi, 632 -shadd8ls, 632 -shadd8ge, 632 -shadd8lt, 632 -shadd8gt, 632 -shadd8le, 632 -shadd8al, 632 -shadd8lo, 632 -shadd8cc, 632 -shadd8hs, 632 -shadd8cs, 632 -shadd8nv, 632 -shaddsubx,634 -shaddsubxeq, 634 -shaddsubxne, 634 -shaddsubxmi, 634 -shaddsubxpl, 634 -shaddsubxvs, 634 -shaddsubxvc, 634 -shaddsubxhi, 634 -shaddsubxls, 634 -shaddsubxge, 634 -shaddsubxlt, 634 -shaddsubxgt, 634 -shaddsubxle, 634 -shaddsubxal, 634 -shaddsubxlo, 634 -shaddsubxcc, 634 -shaddsubxhs, 634 -shaddsubxcs, 634 -shaddsubxnv, 634 -shasx, 634 -shasxeq, 634 -shasxne, 634 -shasxmi, 634 -shasxpl, 634 -shasxvs, 634 -shasxvc, 634 -shasxhi, 634 -shasxls, 634 -shasxge, 634 -shasxlt, 634 -shasxgt, 634 -shasxle, 634 -shasxal, 634 -shasxlo, 634 -shasxcc, 634 -shasxhs, 634 -shasxcs, 634 -shasxnv, 634 -shsubaddx,636 -shsubaddxeq, 636 -shsubaddxne, 636 -shsubaddxmi, 636 -shsubaddxpl, 636 -shsubaddxvs, 636 -shsubaddxvc, 636 -shsubaddxhi, 636 -shsubaddxls, 636 -shsubaddxge, 636 -shsubaddxlt, 636 -shsubaddxgt, 636 -shsubaddxle, 636 -shsubaddxal, 636 -shsubaddxlo, 636 -shsubaddxcc, 636 -shsubaddxhs, 636 -shsubaddxcs, 636 -shsubaddxnv, 636 -shsax, 636 -shsaxeq, 636 -shsaxne, 636 -shsaxmi, 636 -shsaxpl, 636 -shsaxvs, 636 -shsaxvc, 636 -shsaxhi, 636 -shsaxls, 636 -shsaxge, 636 -shsaxlt, 636 -shsaxgt, 636 -shsaxle, 636 -shsaxal, 636 -shsaxlo, 636 -shsaxcc, 636 -shsaxhs, 636 -shsaxcs, 636 -shsaxnv, 636 -shsub16,638 -shsub16eq, 638 -shsub16ne, 638 -shsub16mi, 638 -shsub16pl, 638 -shsub16vs, 638 -shsub16vc, 638 -shsub16hi, 638 -shsub16ls, 638 -shsub16ge, 638 -shsub16lt, 638 -shsub16gt, 638 -shsub16le, 638 -shsub16al, 638 -shsub16lo, 638 -shsub16cc, 638 -shsub16hs, 638 -shsub16cs, 638 -shsub16nv, 638 -shsub8, 640 -shsub8eq, 640 -shsub8ne, 640 -shsub8mi, 640 -shsub8pl, 640 -shsub8vs, 640 -shsub8vc, 640 -shsub8hi, 640 -shsub8ls, 640 -shsub8ge, 640 -shsub8lt, 640 -shsub8gt, 640 -shsub8le, 640 -shsub8al, 640 -shsub8lo, 640 -shsub8cc, 640 -shsub8hs, 640 -shsub8cs, 640 -shsub8nv, 640 -smc, 1576 -smi, 1576 -smlabb, 642 -smlabbeq, 642 -smlabbne, 642 -smlabbmi, 642 -smlabbpl, 642 -smlabbvs, 642 -smlabbvc, 642 -smlabbhi, 642 -smlabbls, 642 -smlabbge, 642 -smlabblt, 642 -smlabbgt, 642 -smlabble, 642 -smlabbal, 642 -smlabblo, 642 -smlabbcc, 642 -smlabbhs, 642 -smlabbcs, 642 -smlabbnv, 642 -smlabt, 642 -smlabteq, 642 -smlabtne, 642 -smlabtmi, 642 -smlabtpl, 642 -smlabtvs, 642 -smlabtvc, 642 -smlabthi, 642 -smlabtls, 642 -smlabtge, 642 -smlabtlt, 642 -smlabtgt, 642 -smlabtle, 642 -smlabtal, 642 -smlabtlo, 642 -smlabtcc, 642 -smlabths, 642 -smlabtcs, 642 -smlabtnv, 642 -smlatb, 642 -smlatbeq, 642 -smlatbne, 642 -smlatbmi, 642 -smlatbpl, 642 -smlatbvs, 642 -smlatbvc, 642 -smlatbhi, 642 -smlatbls, 642 -smlatbge, 642 -smlatblt, 642 -smlatbgt, 642 -smlatble, 642 -smlatbal, 642 -smlatblo, 642 -smlatbcc, 642 -smlatbhs, 642 -smlatbcs, 642 -smlatbnv, 642 -smlatt, 642 -smlatteq, 642 -smlattne, 642 -smlattmi, 642 -smlattpl, 642 -smlattvs, 642 -smlattvc, 642 -smlatthi, 642 -smlattls, 642 -smlattge, 642 -smlattlt, 642 -smlattgt, 642 -smlattle, 642 -smlattal, 642 -smlattlo, 642 -smlattcc, 642 -smlatths, 642 -smlattcs, 642 -smlattnv, 642 -smlad, 644 -smladeq, 644 -smladne, 644 -smladmi, 644 -smladpl, 644 -smladvs, 644 -smladvc, 644 -smladhi, 644 -smladls, 644 -smladge, 644 -smladlt, 644 -smladgt, 644 -smladle, 644 -smladal, 644 -smladlo, 644 -smladcc, 644 -smladhs, 644 -smladcs, 644 -smladnv, 644 -smladx, 644 -smladxeq, 644 -smladxne, 644 -smladxmi, 644 -smladxpl, 644 -smladxvs, 644 -smladxvc, 644 -smladxhi, 644 -smladxls, 644 -smladxge, 644 -smladxlt, 644 -smladxgt, 644 -smladxle, 644 -smladxal, 644 -smladxlo, 644 -smladxcc, 644 -smladxhs, 644 -smladxcs, 644 -smladxnv, 644 -smlal, 646 -smlaleq, 646 -smlalne, 646 -smlalmi, 646 -smlalpl, 646 -smlalvs, 646 -smlalvc, 646 -smlalhi, 646 -smlalls, 646 -smlalge, 646 -smlallt, 646 -smlalgt, 646 -smlalle, 646 -smlalal, 646 -smlallo, 646 -smlalcc, 646 -smlalhs, 646 -smlalcs, 646 -smlalnv, 646 -smlals, 646 -smlaleqs, 646 -smlalnes, 646 -smlalmis, 646 -smlalpls, 646 -smlalvss, 646 -smlalvcs, 646 -smlalhis, 646 -smlallss, 646 -smlalges, 646 -smlallts, 646 -smlalgts, 646 -smlalles, 646 -smlalals, 646 -smlallos, 646 -smlalccs, 646 -smlalhss, 646 -smlalcss, 646 -smlalnvs, 646 -smlalseq,646 -smlalsne, 646 -smlalsmi, 646 -smlalspl, 646 -smlalsvs, 646 -smlalsvc, 646 -smlalshi, 646 -smlalsls, 646 -smlalsge, 646 -smlalslt, 646 -smlalsgt, 646 -smlalsle, 646 -smlalsal, 646 -smlalslo, 646 -smlalscc, 646 -smlalshs, 646 -smlalscs, 646 -smlalsnv, 646 -smlalbb,648 -smlalbbeq, 648 -smlalbbne, 648 -smlalbbmi, 648 -smlalbbpl, 648 -smlalbbvs, 648 -smlalbbvc, 648 -smlalbbhi, 648 -smlalbbls, 648 -smlalbbge, 648 -smlalbblt, 648 -smlalbbgt, 648 -smlalbble, 648 -smlalbbal, 648 -smlalbblo, 648 -smlalbbcc, 648 -smlalbbhs, 648 -smlalbbcs, 648 -smlalbbnv, 648 -smlalbt,648 -smlalbteq, 648 -smlalbtne, 648 -smlalbtmi, 648 -smlalbtpl, 648 -smlalbtvs, 648 -smlalbtvc, 648 -smlalbthi, 648 -smlalbtls, 648 -smlalbtge, 648 -smlalbtlt, 648 -smlalbtgt, 648 -smlalbtle, 648 -smlalbtal, 648 -smlalbtlo, 648 -smlalbtcc, 648 -smlalbths, 648 -smlalbtcs, 648 -smlalbtnv, 648 -smlaltb,648 -smlaltbeq, 648 -smlaltbne, 648 -smlaltbmi, 648 -smlaltbpl, 648 -smlaltbvs, 648 -smlaltbvc, 648 -smlaltbhi, 648 -smlaltbls, 648 -smlaltbge, 648 -smlaltblt, 648 -smlaltbgt, 648 -smlaltble, 648 -smlaltbal, 648 -smlaltblo, 648 -smlatlbcc, 648 -smlatlbhs, 648 -smlatlbcs, 648 -smlatlbnv, 648 -smlaltt,648 -smlaltteq, 648 -smlalttne, 648 -smlalttmi, 648 -smlalttpl, 648 -smlalttvs, 648 -smlalttvc, 648 -smlaltthi, 648 -smlalttls, 648 -smlalttge, 648 -smlalttlt, 648 -smlalttgt, 648 -smlalttle, 648 -smlalttal, 648 -smlalttlo, 648 -smlalttcc, 648 -smlaltths, 648 -smlalttcs, 648 -smlalttnv, 648 -smlald, 650 -smlaldeq, 650 -smlaldne, 650 -smlaldmi, 650 -smlaldpl, 650 -smlaldvs, 650 -smlaldvc, 650 -smlaldhi, 650 -smlaldls, 650 -smlaldge, 650 -smlaldlt, 650 -smlaldgt, 650 -smlaldle, 650 -smlaldal, 650 -smlaldlo, 650 -smlaldcc, 650 -smlaldhs, 650 -smlaldcs, 650 -smlaldnv, 650 -smlawb, 652 -smlawbeq, 652 -smlawbne, 652 -smlawbmi, 652 -smlawbpl, 652 -smlawbvs, 652 -smlawbvc, 652 -smlawbhi, 652 -smlawbls, 652 -smlawbge, 652 -smlawblt, 652 -smlawbgt, 652 -smlawble, 652 -smlawbal, 652 -smlawblo, 652 -smlawbcc, 652 -smlawbhs, 652 -smlawbcs, 652 -smlawbnv, 652 -smlawt, 652 -smlawteq, 652 -smlawtne, 652 -smlawtmi, 652 -smlawtpl, 652 -smlawtvs, 652 -smlawtvc, 652 -smlawthi, 652 -smlawtls, 652 -smlawtge, 652 -smlawtlt, 652 -smlawtgt, 652 -smlawtle, 652 -smlawtal, 652 -smlawtlo, 652 -smlawtcc, 652 -smlawths, 652 -smlawtcs, 652 -smlawtnv, 652 -smlsd, 654 -smlsdeq, 654 -smlsdne, 654 -smlsdmi, 654 -smlsdpl, 654 -smlsdvs, 654 -smlsdvc, 654 -smlsdhi, 654 -smlsdls, 654 -smlsdge, 654 -smlsdlt, 654 -smlsdgt, 654 -smlsdle, 654 -smlsdal, 654 -smlsdlo, 654 -smlsdcc, 654 -smlsdhs, 654 -smlsdcs, 654 -smlsdnv, 654 -smlsdx, 654 -smlsdxeq, 654 -smlsdxne, 654 -smlsdxmi, 654 -smlsdxpl, 654 -smlsdxvs, 654 -smlsdxvc, 654 -smlsdxhi, 654 -smlsdxls, 654 -smlsdxge, 654 -smlsdxlt, 654 -smlsdxgt, 654 -smlsdxle, 654 -smlsdxal, 654 -smlsdxlo, 654 -smlsdxcc, 654 -smlsdxhs, 654 -smlsdxcs, 654 -smlsdxnv, 654 -smlsld, 656 -smlsldeq, 656 -smlsldne, 656 -smlsldmi, 656 -smlsldpl, 656 -smlsldvs, 656 -smlsldvc, 656 -smlsldhi, 656 -smlsldls, 656 -smlsldge, 656 -smlsldlt, 656 -smlsldgt, 656 -smlsldle, 656 -smlsldal, 656 -smlsldlo, 656 -smlsldcc, 656 -smlsldhs, 656 -smlsldcs, 656 -smlsldnv, 656 -smlsldx 656 -smlsldxeq, 656 -smlsldxne, 656 -smlsldxmi, 656 -smlsldxpl, 656 -smlsldxvs, 656 -smlsldxvc, 656 -smlsldxhi, 656 -smlsldxls, 656 -smlsldxge, 656 -smlsldxlt, 656 -smlsldxgt, 656 -smlsldxle, 656 -smlsldxal, 656 -smlsldxlo, 656 -smlsldxcc, 656 -smlsldxhs, 656 -smlsldxcs, 656 -smlsldxnv, 656 -smmla, 658 -smmlaeq, 658 -smmlane, 658 -smmlami, 658 -smmlapl, 658 -smmlavs, 658 -smmlavc, 658 -smmlahi, 658 -smmlals, 658 -smmlage, 658 -smmlalt, 658 -smmlagt, 658 -smmlale, 658 -smmlaal, 658 -smmlalo, 658 -smmlacc, 658 -smmlahs, 658 -smmlacs, 658 -smmlanv, 658 -smmlar, 658 -smmlareq, 658 -smmlarne, 658 -smmlarmi, 658 -smmlarpl, 658 -smmlarvs, 658 -smmlarvc, 658 -smmlarhi, 658 -smmlarls, 658 -smmlarge, 658 -smmlarlt, 658 -smmlargt, 658 -smmlarle, 658 -smmlaral, 658 -smmlarlo, 658 -smmlarcc, 658 -smmlarhs, 658 -smmlarcs, 658 -smmlarnv, 658 -smmls, 660 -smmlseq, 660 -smmlsne, 660 -smmlsmi, 660 -smmlspl, 660 -smmlsvs, 660 -smmlsvc, 660 -smmlshi, 660 -smmlsls, 660 -smmlsge, 660 -smmlslt, 660 -smmlsgt, 660 -smmlsle, 660 -smmlsal, 660 -smmlslo, 660 -smmlscc, 660 -smmlshs, 660 -smmlscs, 660 -smmlsnv, 660 -smmlsr, 660 -smmlsreq, 660 -smmlsrne, 660 -smmlsrmi, 660 -smmlsrpl, 660 -smmlsrvs, 660 -smmlsrvc, 660 -smmlsrhi, 660 -smmlsrls, 660 -smmlsrge, 660 -smmlsrlt, 660 -smmlsrgt, 660 -smmlsrle, 660 -smmlsral, 660 -smmlsrlo, 660 -smmlsrcc, 660 -smmlsrhs, 660 -smmlsrcs, 660 -smmlsrnv, 660 -smmul, 662 -smmuleq, 662 -smmulne, 662 -smmulmi, 662 -smmulpl, 662 -smmulvs, 662 -smmulvc, 662 -smmulhi, 662 -smmulls, 662 -smmulge, 662 -smmullt, 662 -smmulgt, 662 -smmulle, 662 -smmulal, 662 -smmullo, 662 -smmulcc, 662 -smmulhs, 662 -smmulcs, 662 -smmulnv, 662 -smmulr, 662 -smmulreq, 662 -smmulrne, 662 -smmulrmi, 662 -smmulrpl, 662 -smmulrvs, 662 -smmulrvc, 662 -smmulrhi, 662 -smmulrls, 662 -smmulrge, 662 -smmulrlt, 662 -smmulrgt, 662 -smmulrle, 662 -smmulral, 662 -smmulrlo, 662 -smmulrcc, 662 -smmulrhs, 662 -smmulrcs, 662 -smmulrnv, 662 -smuad, 664 -smuadeq, 664 -smuadne, 664 -smuadmi, 664 -smuadpl, 664 -smuadvs, 664 -smuadvc, 664 -smuadhi, 664 -smuadls, 664 -smuadge, 664 -smuadlt, 664 -smuadgt, 664 -smuadle, 664 -smuadal, 664 -smuadlo, 664 -smuadcc, 664 -smuadhs, 664 -smuadcs, 664 -smuadnv, 664 -smuadx, 664 -smuadxeq, 664 -smuadxne, 664 -smuadxmi, 664 -smuadxpl, 664 -smuadxvs, 664 -smuadxvc, 664 -smuadxhi, 664 -smuadxls, 664 -smuadxge, 664 -smuadxlt, 664 -smuadxgt, 664 -smuadxle, 664 -smuadxal, 664 -smuadxlo, 664 -smuadxcc, 664 -smuadxhs, 664 -smuadxcs, 664 -smuadxnv, 664 -smulbb, 666 -smulbbeq, 666 -smulbbne, 666 -smulbbmi, 666 -smulbbpl, 666 -smulbbvs, 666 -smulbbvc, 666 -smulbbhi, 666 -smulbbls, 666 -smulbbge, 666 -smulbblt, 666 -smulbbgt, 666 -smulbble, 666 -smulbbal, 666 -smulbblo, 666 -smulbbcc, 666 -smulbbhs, 666 -smulbbcs, 666 -smulbbnv, 666 -smulbt, 666 -smulbteq, 666 -smulbtne, 666 -smulbtmi, 666 -smulbtpl, 666 -smulbtvs, 666 -smulbtvc, 666 -smulbthi, 666 -smulbtls, 666 -smulbtge, 666 -smulbtlt, 666 -smulbtgt, 666 -smulbtle, 666 -smulbtal, 666 -smulbtlo, 666 -smulbtcc, 666 -smulbths, 666 -smulbtcs, 666 -smulbtnv, 666 -smultb, 666 -smultbeq, 666 -smultbne, 666 -smultbmi, 666 -smultbpl, 666 -smultbvs, 666 -smultbvc, 666 -smultbhi, 666 -smultbls, 666 -smultbge, 666 -smultblt, 666 -smultbgt, 666 -smultble, 666 -smultbal, 666 -smultblo, 666 -smultbcc, 666 -smultbhs, 666 -smultbcs, 666 -smultbnv, 666 -smultt, 666 -smultteq, 666 -smulttne, 666 -smulttmi, 666 -smulttpl, 666 -smulttvs, 666 -smulttvc, 666 -smultthi, 666 -smulttls, 666 -smulttge, 666 -smulttlt, 666 -smulttgt, 666 -smulttle, 666 -smulttal, 666 -smulttlo, 666 -smulttcc, 666 -smultths, 666 -smulttcs, 666 -smulttnv, 666 -smull, 668 -smulleq, 668 -smullne, 668 -smullmi, 668 -smullpl, 668 -smullvs, 668 -smullvc, 668 -smullhi, 668 -smullls, 668 -smullge, 668 -smulllt, 668 -smullgt, 668 -smullle, 668 -smullal, 668 -smulllo, 668 -smullcc, 668 -smullhs, 668 -smullcs, 668 -smullnv, 668 -smulls, 668 -smulleqs, 668 -smullnes, 668 -smullmis, 668 -smullpls, 668 -smullvss, 668 -smullvcs, 668 -smullhis, 668 -smulllss, 668 -smullges, 668 -smulllts, 668 -smullgts, 668 -smullles, 668 -smullals, 668 -smulllos, 668 -smullccs, 668 -smullhss, 668 -smullcss, 668 -smullnvs, 668 -smullseq,668 -smullsne, 668 -smullsmi, 668 -smullspl, 668 -smullsvs, 668 -smullsvc, 668 -smullshi, 668 -smullsls, 668 -smullsge, 668 -smullslt, 668 -smullsgt, 668 -smullsle, 668 -smullsal, 668 -smullslo, 668 -smullscc, 668 -smullshs, 668 -smullscs, 668 -smullsnv, 668 -smulwb, 670 -smulwbeq, 670 -smulwbne, 670 -smulwbmi, 670 -smulwbpl, 670 -smulwbvs, 670 -smulwbvc, 670 -smulwbhi, 670 -smulwbls, 670 -smulwbge, 670 -smulwblt, 670 -smulwbgt, 670 -smulwble, 670 -smulwbal, 670 -smulwblo, 670 -smulwbcc, 670 -smulwbhs, 670 -smulwbcs, 670 -smulwbnv, 670 -smulwt, 670 -smulwteq, 670 -smulwtne, 670 -smulwtmi, 670 -smulwtpl, 670 -smulwtvs, 670 -smulwtvc, 670 -smulwthi, 670 -smulwtls, 670 -smulwtge, 670 -smulwtlt, 670 -smulwtgt, 670 -smulwtle, 670 -smulwtal, 670 -smulwtlo, 670 -smulwtcc, 670 -smulwths, 670 -smulwtcs, 670 -smulwtnv, 670 -smusd, 672 -smusdeq, 672 -smusdne, 672 -smusdmi, 672 -smusdpl, 672 -smusdvs, 672 -smusdvc, 672 -smusdhi, 672 -smusdls, 672 -smusdge, 672 -smusdlt, 672 -smusdgt, 672 -smusdle, 672 -smusdal, 672 -smusdlo, 672 -smusdcc, 672 -smusdhs, 672 -smusdcs, 672 -smusdnv, 672 -smusdx, 672 -smusdxeq, 672 -smusdxne, 672 -smusdxmi, 672 -smusdxpl, 672 -smusdxvs, 672 -smusdxvc, 672 -smusdxhi, 672 -smusdxls, 672 -smusdxge, 672 -smusdxlt, 672 -smusdxgt, 672 -smusdxle, 672 -smusdxal, 672 -smusdxlo, 672 -smusdxcc, 672 -smusdxhs, 672 -smusdxcs, 672 -smusdxnv, 672 -srsda, 1578 -srsdaeq, 1578 -srsdane, 1578 -srsdami, 1578 -srsdapl, 1578 -srsdavs, 1578 -srsdavc, 1578 -srsdahi, 1578 -srsdals, 1578 -srsdage, 1578 -srsdalt, 1578 -srsdagt, 1578 -srsdale, 1578 -srsdaal, 1578 -srsdalo, 1578 -srsdacc, 1578 -srsdahs, 1578 -srsdacs, 1578 -srsdanv, 1578 -srsdb, 1578 -srsdbeq, 1578 -srsdbne, 1578 -srsdbmi, 1578 -srsdbpl, 1578 -srsdbvs, 1578 -srsdbvc, 1578 -srsdbhi, 1578 -srsdbls, 1578 -srsdbge, 1578 -srsdblt, 1578 -srsdbgt, 1578 -srsdble, 1578 -srsdbal, 1578 -srsdblo, 1578 -srsdbcc, 1578 -srsdbhs, 1578 -srsdbcs, 1578 -srsdbnv, 1578 -srsia, 1578 -srsiaeq, 1578 -srsiane, 1578 -srsiami, 1578 -srsiapl, 1578 -srsiavs, 1578 -srsiavc, 1578 -srsiahi, 1578 -srsials, 1578 -srsiage, 1578 -srsialt, 1578 -srsiagt, 1578 -srsiale, 1578 -srsiaal, 1578 -srsialo, 1578 -srsiacc, 1578 -srsiahs, 1578 -srsiacs, 1578 -srsianv, 1578 -srsib, 1578 -srsibeq, 1578 -srsibne, 1578 -srsibmi, 1578 -srsibpl, 1578 -srsibvs, 1578 -srsibvc, 1578 -srsibhi, 1578 -srsibls, 1578 -srsibge, 1578 -srsiblt, 1578 -srsibgt, 1578 -srsible, 1578 -srsibal, 1578 -srsiblo, 1578 -srsibcc, 1578 -srsibhs, 1578 -srsibcs, 1578 -srsibnv, 1578 -ssat, 674 -ssateq, 674 -ssatne, 674 -ssatmi, 674 -ssatpl, 674 -ssatvs, 674 -ssatvc, 674 -ssathi, 674 -ssatls, 674 -ssatge, 674 -ssatlt, 674 -ssatgt, 674 -ssatle, 674 -ssatal, 674 -ssatlo, 674 -ssatcc, 674 -ssaths, 674 -ssatcs, 674 -ssatnv, 674 -ssat16, 676 -ssateq16, 676 -ssatne16, 676 -ssatmi16, 676 -ssatpl16, 676 -ssatvs16, 676 -ssatvc16, 676 -ssathi16, 676 -ssatls16, 676 -ssatge16, 676 -ssatlt16, 676 -ssatgt16, 676 -ssatle16, 676 -ssatal16, 676 -ssatlo16, 676 -ssatcc16, 676 -ssaths16, 676 -ssatcs16, 676 -ssatnv16, 676 -ssubaddx,678 -ssubaddxeq, 678 -ssubaddxne, 678 -ssubaddxmi, 678 -ssubaddxpl, 678 -ssubaddxvs, 678 -ssubaddxvc, 678 -ssubaddxhi, 678 -ssubaddxls, 678 -ssubaddxge, 678 -ssubaddxlt, 678 -ssubaddxgt, 678 -ssubaddxle, 678 -ssubaddxal, 678 -ssubaddxlo, 678 -ssubaddxcc, 678 -ssubaddxhs, 678 -ssubaddxcs, 678 -ssubaddxnv, 678 -ssax, 678 -ssaxeq, 678 -ssaxne, 678 -ssaxmi, 678 -ssaxpl, 678 -ssaxvs, 678 -ssaxvc, 678 -ssaxhi, 678 -ssaxls, 678 -ssaxge, 678 -ssaxlt, 678 -ssaxgt, 678 -ssaxle, 678 -ssaxal, 678 -ssaxlo, 678 -ssaxcc, 678 -ssaxhs, 678 -ssaxcs, 678 -ssaxnv, 678 -ssub16, 680 -ssub16eq, 680 -ssub16ne, 680 -ssub16mi, 680 -ssub16pl, 680 -ssub16vs, 680 -ssub16vc, 680 -ssub16hi, 680 -ssub16ls, 680 -ssub16ge, 680 -ssub16lt, 680 -ssub16gt, 680 -ssub16le, 680 -ssub16al, 680 -ssub16lo, 680 -ssub16cc, 680 -ssub16hs, 680 -ssub16cs, 680 -ssub16nv, 680 -ssub8, 682 -ssub8eq, 682 -ssub8ne, 682 -ssub8mi, 682 -ssub8pl, 682 -ssub8vs, 682 -ssub8vc, 682 -ssub8hi, 682 -ssub8ls, 682 -ssub8ge, 682 -ssub8lt, 682 -ssub8gt, 682 -ssub8le, 682 -ssub8al, 682 -ssub8lo, 682 -ssub8cc, 682 -ssub8hs, 682 -ssub8cs, 682 -ssub8nv, 682 -stc, 684 -stceq, 684 -stcne, 684 -stcmi, 684 -stcpl, 684 -stcvs, 684 -stcvc, 684 -stchi, 684 -stcls, 684 -stcge, 684 -stclt, 684 -stcgt, 684 -stcle, 684 -stcal, 684 -stclo, 684 -stccc, 684 -stchs, 684 -stccs, 684 -stcnv, 684 -stcl, 684 -stceql, 684 -stcnel, 684 -stcmil, 684 -stcpll, 684 -stcvsl, 684 -stcvcl, 684 -stchil, 684 -stclsl, 684 -stcgel, 684 -stcltl, 684 -stcgtl, 684 -stclel, 684 -stcall, 684 -stclol, 684 -stcccl, 684 -stchsl, 684 -stccsl, 684 -stcnvl, 684 -stcleq, 684 -stclne, 684 -stclmi, 684 -stclpl, 684 -stclvs, 684 -stclvc, 684 -stclhi, 684 -stclls, 684 -stclge, 684 -stcllt, 684 -stclgt, 684 -stclle, 684 -stclal, 684 -stcllo, 684 -stclcc, 684 -stclhs, 684 -stclcs, 684 -stclnv, 684 -stc2, 684 -stc2eq, 684 -stc2ne, 684 -stc2mi, 684 -stc2pl, 684 -stc2vs, 684 -stc2vc, 684 -stc2hi, 684 -stc2ls, 684 -stc2ge, 684 -stc2lt, 684 -stc2gt, 684 -stc2le, 684 -stc2al, 684 -stc2lo, 684 -stc2cc, 684 -stc2hs, 684 -stc2cs, 684 -stc2nv, 684 -stc2l, 684 -stc2leq, 684 -stc2lne, 684 -stc2lmi, 684 -stc2lpl, 684 -stc2lvs, 684 -stc2lvc, 684 -stc2lhi, 684 -stc2lls, 684 -stc2lge, 684 -stc2llt, 684 -stc2lgt, 684 -stc2lle, 684 -stc2lal, 684 -stc2llo, 684 -stc2lcc, 684 -stc2lhs, 684 -stc2lcs, 684 -stc2lnv, 684 -stm, 686 -stmeq, 686 -stmne, 686 -stmmi, 686 -stmpl, 686 -stmvs, 686 -stmvc, 686 -stmhi, 686 -stmls, 686 -stmge, 686 -stmlt, 686 -stmgt, 686 -stmle, 686 -stmal, 686 -stmlo, 686 -stmcc, 686 -stmhs, 686 -stmcs, 686 -stmnv, 686 -stmia, 686 -stmeqia, 686 -stmneia, 686 -stmmiia, 686 -stmplia, 686 -stmvsia, 686 -stmvcia, 686 -stmhiia, 686 -stmlsia, 686 -stmgeia, 686 -stmltia, 686 -stmgtia, 686 -stmleia, 686 -stmalia, 686 -stmloia, 686 -stmccia, 686 -stmhsia, 686 -stmcsia, 686 -stmnvia, 686 -stmea, 686 -stmeqea, 686 -stmneea, 686 -stmmiea, 686 -stmplea, 686 -stmvsea, 686 -stmvcea, 686 -stmhiea, 686 -stmlsea, 686 -stmgeea, 686 -stmltea, 686 -stmgtea, 686 -stmleea, 686 -stmalea, 686 -stmloea, 686 -stmccea, 686 -stmhsea, 686 -stmcsea, 686 -stmnvea, 686 -stmib, 692 -stmeqib, 692 -stmneib, 692 -stmmiib, 692 -stmplib, 692 -stmvsib, 692 -stmvcib, 692 -stmhiib, 692 -stmlsib, 692 -stmgeib, 692 -stmltib, 692 -stmgtib, 692 -stmleib, 692 -stmalib, 692 -stmloib, 692 -stmccib, 692 -stmhsib, 692 -stmcsib, 692 -stmnvib, 692 -stmibeq,692 -stmibne, 692 -stmibmi, 692 -stmibpl, 692 -stmibvs, 692 -stmibvc, 692 -stmibhi, 692 -stmibls, 692 -stmibge, 692 -stmiblt, 692 -stmibgt, 692 -stmible, 692 -stmibal, 692 -stmiblo, 692 -stmibcc, 692 -stmibhs, 692 -stmibcs, 692 -stmibnv, 692 -stmeqda,692 -stmnefa, 692 -stmmifa, 692 -stmplfa, 692 -stmvsfa, 692 -stmvcfa, 692 -stmhifa, 692 -stmlsfa, 692 -stmgefa, 692 -stmltfa, 692 -stmgtfa, 692 -stmlefa, 692 -stmalfa, 692 -stmlofa, 692 -stmccfa, 692 -stmhsfa, 692 -stmcsfa, 692 -stmnvfa, 692 -stmda, 688 -stmeqda, 688 -stmneda, 688 -stmmida, 688 -stmplda, 688 -stmvsda, 688 -stmvcda, 688 -stmhida, 688 -stmlsda, 688 -stmgeda, 688 -stmltda, 688 -stmgtda, 688 -stmleda, 688 -stmalda, 688 -stmloda, 688 -stmccda, 688 -stmhsda, 688 -stmcsda, 688 -stmnvda, 688 -stmdaeq,688 -stmdane, 688 -stmdami, 688 -stmdapl, 688 -stmdavs, 688 -stmdavc, 688 -stmdahi, 688 -stmdals, 688 -stmdage, 688 -stmdalt, 688 -stmdagt, 688 -stmdale, 688 -stmdaal, 688 -stmdalo, 688 -stmdacc, 688 -stmdahs, 688 -stmdacs, 688 -stmdanv, 688 -stmeqed,688 -stmneed, 688 -stmmied, 688 -stmpled, 688 -stmvsed, 688 -stmvced, 688 -stmhied, 688 -stmlsed, 688 -stmgeed, 688 -stmlted, 688 -stmgted, 688 -stmleed, 688 -stmaled, 688 -stmloed, 688 -stmcced, 688 -stmhsed, 688 -stmcsed, 688 -stmnved, 688 -stmdb, 690 -stmeqdb, 690 -stmnedb, 690 -stmmidb, 690 -stmpldb, 690 -stmvsdb, 690 -stmvcdb, 690 -stmhidb, 690 -stmlsdb, 690 -stmgedb, 690 -stmltdb, 690 -stmgtdb, 690 -stmledb, 690 -stmaldb, 690 -stmlodb, 690 -stmccdb, 690 -stmhsdb, 690 -stmcsdb, 690 -stmnvdb, 690 -stmeqfd,690 -stmnefd, 690 -stmmifd, 690 -stmplfd, 690 -stmvsfd, 690 -stmvcfd, 690 -stmhifd, 690 -stmlsfd, 690 -stmgefd, 690 -stmltfd, 690 -stmgtfd, 690 -stmlefd, 690 -stmalfd, 690 -stmlofd, 690 -stmccfd, 690 -stmhsfd, 690 -stmcsfd, 690 -stmnvfd, 690 -stmdbeq,690 -stmdbne, 690 -stmdbmi, 690 -stmdbpl, 690 -stmdbvs, 690 -stmdbvc, 690 -stmdbhi, 690 -stmdbls, 690 -stmdbge, 690 -stmdblt, 690 -stmdbgt, 690 -stmdble, 690 -stmdbal, 690 -stmdblo, 690 -stmdbcc, 690 -stmdbhs, 690 -stmdbcs, 690 -stmdbnv, 690 -str, 694 -streq, 694 -strne, 694 -strmi, 694 -strpl, 694 -strvs, 694 -strvc, 694 -strhi, 694 -strls, 694 -strge, 694 -strlt, 694 -strgt, 694 -strle, 694 -stral, 694 -strlo, 694 -strcc, 694 -strhs, 694 -strcs, 694 -strnv, 694 -strb, 700 -streqb, 700 -strneb, 700 -strmib, 700 -strplb, 700 -strvsb, 700 -strvcb, 700 -strhib, 700 -strlsb, 700 -strgeb, 700 -strltb, 700 -strgtb, 700 -strleb, 700 -stralb, 700 -strlob, 700 -strccb, 700 -strhsb, 700 -strcsb, 700 -strnvb, 700 -strbeq, 700 -strbne, 700 -strbmi, 700 -strbpl, 700 -strbvs, 700 -strbvc, 700 -strbhi, 700 -strbls, 700 -strbge, 700 -strblt, 700 -strbgt, 700 -strble, 700 -strbal, 700 -strblo, 700 -strbcc, 700 -strbhs, 700 -strbcs, 700 -strbnv, 700 -strbt, 706 -streqbt, 706 -strnebt, 706 -strmibt, 706 -strplbt, 706 -strvsbt, 706 -strvcbt, 706 -strhibt, 706 -strlsbt, 706 -strgebt, 706 -strltbt, 706 -strgtbt, 706 -strlebt, 706 -stralbt, 706 -strlobt, 706 -strccbt, 706 -strhsbt, 706 -strcsbt, 706 -strnvbt, 706 -strbteq 706 -strbtne, 706 -strbtmi, 706 -strbtpl, 706 -strbtvs, 706 -strbtvc, 706 -strbthi, 706 -strbtls, 706 -strbtge, 706 -strbtlt, 706 -strbtgt, 706 -strbtle, 706 -strbtal, 706 -strbtlo, 706 -strbtcc, 706 -strbths, 706 -strbtcs, 706 -strbtnv, 706 -strd, 708 -streqd, 708 -strned, 708 -strmid, 708 -strpld, 708 -strvsd, 708 -strvcd, 708 -strhid, 708 -strlsd, 708 -strged, 708 -strltd, 708 -strgtd, 708 -strled, 708 -strald, 708 -strlod, 708 -strccd, 708 -strhsd, 708 -strcsd, 708 -strnvd, 708 -strdeq, 708 -strdne, 708 -strdmi, 708 -strdpl, 708 -strdvs, 708 -strdvc, 708 -strdhi, 708 -strdls, 708 -strdge, 708 -strdlt, 708 -strdgt, 708 -strdle, 708 -strdal, 708 -strdlo, 708 -strdcc, 708 -strdhs, 708 -strdcs, 708 -strdnv, 708 -strex, 712 -strexeq, 712 -strexne, 712 -strexmi, 712 -strexpl, 712 -strexvs, 712 -strexvc, 712 -strexhi, 712 -strexls, 712 -strexge, 712 -strexlt, 712 -strexgt, 712 -strexle, 712 -strexal, 712 -strexlo, 712 -strexcc, 712 -strexhs, 712 -strexcs, 712 -strexnv, 712 -strexb, 714 -strexbeq, 714 -strexbne, 714 -strexbmi, 714 -strexbpl, 714 -strexbvs, 714 -strexbvc, 714 -strexbhi, 714 -strexbls, 714 -strexbge, 714 -strexblt, 714 -strexbgt, 714 -strexble, 714 -strexbal, 714 -strexblo, 714 -strexbcc, 714 -strexbhs, 714 -strexbcs, 714 -strexbnv, 714 -strexd, 716 -strexdeq, 716 -strexdne, 716 -strexdmi, 716 -strexdpl, 716 -strexdvs, 716 -strexdvc, 716 -strexdhi, 716 -strexdls, 716 -strexdge, 716 -strexdlt, 716 -strexdgt, 716 -strexdle, 716 -strexdal, 716 -strexdlo, 716 -strexdcc, 716 -strexdhs, 716 -strexdcs, 716 -strexdnv, 716 -strexh, 718 -strexheq, 718 -strexhne, 718 -strexhmi, 718 -strexhpl, 718 -strexhvs, 718 -strexhvc, 718 -strexhhi, 718 -strexhls, 718 -strexhge, 718 -strexhlt, 718 -strexhgt, 718 -strexhle, 718 -strexhal, 718 -strexhlo, 718 -strexhcc, 718 -strexhhs, 718 -strexhcs, 718 -strexhnv, 718 -strh, 720 -streqh, 720 -strneh, 720 -strmih, 720 -strplh, 720 -strvsh, 720 -strvch, 720 -strhih, 720 -strlsh, 720 -strgeh, 720 -strlth, 720 -strgth, 720 -strleh, 720 -stralh, 720 -strloh, 720 -strcch, 720 -strhsh, 720 -strcsh, 720 -strnvh, 720 -strheq, 720 -strhne, 720 -strhmi, 720 -strhpl, 720 -strhvs, 720 -strhvc, 720 -strhhi, 720 -strhls, 720 -strhge, 720 -strhlt, 720 -strhgt, 720 -strhle, 720 -strhal, 720 -strhlo, 720 -strhcc, 720 -strhhs, 720 -strhcs, 720 -strhnv, 720 -strht, 726 -strhteq, 726 -strhtne, 726 -strhtmi, 726 -strhtpl, 726 -strhtvs, 726 -strhtvc, 726 -strhthi, 726 -strhtls, 726 -strhtge, 726 -strhlt, 726 -strhtgt, 726 -strhtle, 726 -strhtal, 726 -strhtlo, 726 -strhtcc, 726 -strhths, 726 -strhtcs, 726 -strhtnv, 726 -strt, 728 -streqt, 728 -strnet, 728 -strmit, 728 -strplt, 728 -strvst, 728 -strvct, 728 -strhit, 728 -strlst, 728 -strget, 728 -strltt, 728 -strgtt, 728 -strlet, 728 -stralt, 728 -strlot, 728 -strcct, 728 -strhst, 728 -strcst, 728 -strnvt, 728 -strteq, 728 -strtne, 728 -strtmi, 728 -strtpl, 728 -strtvs, 728 -strtvc, 728 -strthi, 728 -strtls, 728 -strtge, 728 -strtlt, 728 -strtgt, 728 -strtle, 728 -strtal, 728 -strtlo, 728 -strtcc, 728 -strths, 728 -strtcs, 728 -strtnv, 728 -sub, 730 -subeq, 730 -subne, 730 -submi, 730 -subpl, 730 -subvs, 730 -subvc, 730 -subhi, 730 -subls, 730 -subge, 730 -sublt, 730 -subgt, 730 -suble, 730 -subal, 730 -sublo, 730 -subcc, 730 -subhs, 730 -subcs, 730 -subnv, 730 -subs, 730 -subeqs, 730 -subnes, 730 -submis, 730 -subpls, 730 -subvss, 730 -subvcs, 730 -subhis, 730 -sublss, 730 -subges, 730 -sublts, 730 -subgts, 730 -subles, 730 -subals, 730 -sublos, 730 -subccs, 730 -subhss, 730 -subcss, 730 -subnvs, 730 -subseq, 730 -subsne, 730 -subsmi, 730 -subspl, 730 -subsvs, 730 -subsvc, 730 -subshi, 730 -subsls, 730 -subsge, 730 -subslt, 730 -subsgt, 730 -subsle, 730 -subsal, 730 -subslo, 730 -subscc, 730 -subshs, 730 -subscs, 730 -subsnv, 730 -svc, 742 -svceq, 742 -svcne, 742 -svcmi, 742 -svcpl, 742 -svcvs, 742 -svcvc, 742 -svchi, 742 -svcls, 742 -svcge, 742 -svclt, 742 -svcgt, 742 -svcle, 742 -svcal, 742 -svclo, 742 -svccc, 742 -svchs, 742 -svccs, 742 -svcnv, 742 -swi, 742 -swieq, 742 -swine, 742 -swimi, 742 -swipl, 742 -swivs, 742 -swivc, 742 -swihi, 742 -swils, 742 -swige, 742 -swilt, 742 -swigt, 742 -swile, 742 -swial, 742 -swilo, 742 -swicc, 742 -swihs, 742 -swics, 742 -swinv, 742 -swp, 744 -swpeq, 744 -swpne, 744 -swpmi, 744 -swppl, 744 -swpvs, 744 -swpvc, 744 -swphi, 744 -swpls, 744 -swpge, 744 -swplt, 744 -swpgt, 744 -swple, 744 -swpal, 744 -swplo, 744 -swpcc, 744 -swphs, 744 -swpcs, 744 -swpnv, 744 -swpb, 744 -swpeqb, 744 -swpneb, 744 -swpmib, 744 -swpplb, 744 -swpvsb, 744 -swpvcb, 744 -swphib, 744 -swplsb, 744 -swpgeb, 744 -swpltb, 744 -swpgtb, 744 -swpleb, 744 -swpalb, 744 -swplob, 744 -swpccb, 744 -swphsb, 744 -swpcsb, 744 -swpnvb, 744 -sxtab, 746 -sxtabeq, 746 -sxtabne, 746 -sxtabmi, 746 -sxtabpl, 746 -sxtabvs, 746 -sxtabvc, 746 -sxtabhi, 746 -sxtabls, 746 -sxtabge, 746 -sxtablt, 746 -sxtabgt, 746 -sxtable, 746 -sxtabal, 746 -sxtablo, 746 -sxtabcc, 746 -sxtabhs, 746 -sxtabcs, 746 -sxtabnv, 746 -sxtab16, 748 -sxtab16eq, 748 -sxtab16ne, 748 -sxtab16mi, 748 -sxtab16pl, 748 -sxtab16vs, 748 -sxtab16vc, 748 -sxtab16hi, 748 -sxtab16ls, 748 -sxtab16ge, 748 -sxtab16lt, 748 -sxtab16gt, 748 -sxtab16le, 748 -sxtab6al, 748 -sxtab6lo, 748 -sxtab16cc, 748 -sxtab16hs, 748 -sxtab16cs, 748 -sxtab16nv, 748 -sxtah, 750 -sxtaheq, 750 -sxtahne, 750 -sxtahmi, 750 -sxtahpl, 750 -sxtahvs, 750 -sxtahvc, 750 -sxtahhi, 750 -sxtahls, 750 -sxtahge, 750 -sxtahlt, 750 -sxtahgt, 750 -sxtahle, 750 -sxtahal, 750 -sxtahlo, 750 -sxtahcc, 750 -sxtahhs, 750 -sxtahcs, 750 -sxtahnv, 750 -sxtb, 752 -sxtbeq, 752 -sxtbne, 752 -sxtbmi, 752 -sxtbpl, 752 -sxtbvs, 752 -sxtbvc, 752 -sxtbhi, 752 -sxtbls, 752 -sxtbge, 752 -sxtblt, 752 -sxtbgt, 752 -sxtble, 752 -sxtbal, 752 -sxtblo, 752 -sxtbcc, 752 -sxtbhs, 752 -sxtbcs, 752 -sxtbnv, 752 -sxtb16, 754 -sxtb16eq, 754 -sxtb16ne, 754 -sxtb16mi, 754 -sxtb16pl, 754 -sxtb16vs, 754 -sxtb16vc, 754 -sxtb16hi, 754 -sxtb16ls, 754 -sxtb16ge, 754 -sxtb16lt, 754 -sxtb16gt, 754 -sxtb16le, 754 -sxtb16al, 754 -sxtb16lo, 754 -sxtb16cc, 754 -sxtb16hs, 754 -sxtb16cs, 754 -sxtb16nv, 754 -sxth, 756 -sxtheq, 756 -sxthne, 756 -sxthmi, 756 -sxthpl, 756 -sxthvs, 756 -sxthvc, 756 -sxthhi, 756 -sxthls, 756 -sxthge, 756 -sxthlt, 756 -sxthgt, 756 -sxthle, 756 -sxthal, 756 -sxthlo, 756 -sxthcc, 756 -sxthhs, 756 -sxthcs, 756 -sxthnv, 756 -tbb, 758 -tbbeq, 758 -tbbne, 758 -tbbmi, 758 -tbbpl, 758 -tbbvs, 758 -tbbvc, 758 -tbbhi, 758 -tbbls, 758 -tbbge, 758 -tbblt, 758 -tbbgt, 758 -tbble, 758 -tbbal, 758 -tbblo, 758 -tbbcc, 758 -tbbhs, 758 -tbbcs, 758 -tbbnv, 758 -tbh, 758 -tbheq, 758 -tbhne, 758 -tbhmi, 758 -tbhpl, 758 -tbhvs, 758 -tbhvc, 758 -tbhhi, 758 -tbhls, 758 -tbhge, 758 -tbhlt, 758 -tbhgt, 758 -tbhle, 758 -tbhal, 758 -tbhlo, 758 -tbhcc, 758 -tbhhs, 758 -tbhcs, 758 -tbhnv, 758 -teq, 760 -teqeq, 760 -teqne, 760 -teqmi, 760 -teqpl, 760 -teqvs, 760 -teqvc, 760 -teqhi, 760 -teqls, 760 -teqge, 760 -teqlt, 760 -teqgt, 760 -teqle, 760 -teqal, 760 -teqlo, 760 -teqcc, 760 -teqhs, 760 -teqcs, 760 -teqnv, 760 -tst, 766 -tsteq, 766 -tstne, 766 -tstmi, 766 -tstpl, 766 -tstvs, 766 -tstvc, 766 -tsthi, 766 -tstls, 766 -tstge, 766 -tstlt, 766 -tstgt, 766 -tstle, 766 -tstal, 766 -tstlo, 766 -tstcc, 766 -tsths, 766 -tstcs, 766 -tstnv, 766 -uadd16, 772 -uadd16eq, 772 -uadd16ne, 772 -uadd16mi, 772 -uadd16pl, 772 -uadd16vs, 772 -uadd16vc, 772 -uadd16hi, 772 -uadd16ls, 772 -uadd16ge, 772 -uadd16lt, 772 -uadd16gt, 772 -uadd16le, 772 -uadd16al, 772 -uadd16lo, 772 -uadd16cc, 772 -uadd16hs, 772 -uadd16cs, 772 -uadd16nv, 772 -uadd8, 774 -uadd8eq, 774 -uadd8ne, 774 -uadd8mi, 774 -uadd8pl, 774 -uadd8vs, 774 -uadd8vc, 774 -uadd8hi, 774 -uadd8ls, 774 -uadd8ge, 774 -uadd8lt, 774 -uadd8gt, 774 -uadd8le, 774 -uadd8al, 774 -uadd8lo, 774 -uadd8cc, 774 -uadd8hs, 774 -uadd8cs, 774 -uadd8nv, 774 -uaddsubx, 776 -uaddsubxeq, 776 -uaddsubxne, 776 -uaddsubxmi, 776 -uaddsubxpl, 776 -uaddsubxvs, 776 -uaddsubxvc, 776 -uaddsubxhi, 776 -uaddsubxls, 776 -uaddsubxge, 776 -uaddsubxlt, 776 -uaddsubxgt, 776 -uaddsubxle, 776 -uaddsubxal, 776 -uaddsubxlo, 776 -uaddsubxcc, 776 -uaddsubxhs, 776 -uaddsubxcs, 776 -uaddsubxnv, 776 -uasx, 776 -uasxeq, 776 -uasxne, 776 -uasxmi, 776 -uasxpl, 776 -uasxvs, 776 -uasxvc, 776 -uasxhi, 776 -uasxls, 776 -uasxge, 776 -uasxlt, 776 -uasxgt, 776 -uasxle, 776 -uasxal, 776 -uasxlo, 776 -uasxcc, 776 -uasxhs, 776 -uasxcs, 776 -uasxnv, 776 -ubfx, 778 -ubfxeq, 778 -ubfxne, 778 -ubfxmi, 778 -ubfxpl, 778 -ubfxvs, 778 -ubfxvc, 778 -ubfxhi, 778 -ubfxls, 778 -ubfxge, 778 -ubfxlt, 778 -ubfxgt, 778 -ubfxle, 778 -ubfxal, 778 -ubfxlo, 778 -ubfxcc, 778 -ubfxhs, 778 -ubfxcs, 778 -ubfxnv, 778 -udiv, 780 -udiveq, 780 -udivne, 780 -udivmi, 780 -udivpl, 780 -udivvs, 780 -udivvc, 780 -udivhi, 780 -udivls, 780 -udivge, 780 -udivlt, 780 -udivgt, 780 -udivle, 780 -udival, 780 -udivlo, 780 -udivcc, 780 -udivhs, 780 -udivcs, 780 -udivnv, 780 -uhadd16, 782 -uhadd16eq, 782 -uhadd16ne, 782 -uhadd16mi, 782 -uhadd16pl, 782 -uhadd16vs, 782 -uhadd16vc, 782 -uhadd16hi, 782 -uhadd16ls, 782 -uhadd16ge, 782 -uhadd16lt, 782 -uhadd16gt, 782 -uhadd16le, 782 -uhadd16al, 782 -uhadd16lo, 782 -uhadd16cc, 782 -uhadd16hs, 782 -uhadd16cs, 782 -uhadd16nv, 782 -uhadd8, 784 -uhadd8eq, 784 -uhadd8ne, 784 -uhadd8mi, 784 -uhadd8pl, 784 -uhadd8vs, 784 -uhadd8vc, 784 -uhadd8hi, 784 -uhadd8ls, 784 -uhadd8ge, 784 -uhadd8lt, 784 -uhadd8gt, 784 -uhadd8le, 784 -uhadd8al, 784 -uhadd8lo, 784 -uhadd8cc, 784 -uhadd8hs, 784 -uhadd8cs, 784 -uhadd8nv, 784 -uhaddsubx, 786 -uhaddsubxeq, 786 -uhaddsubxne, 786 -uhaddsubxmi, 786 -uhaddsubxpl, 786 -uhaddsubxvs, 786 -uhaddsubxvc, 786 -uhaddsubxhi, 786 -uhaddsubxls, 786 -uhaddsubxge, 786 -uhaddsubxlt, 786 -uhaddsubxgt, 786 -uhaddsubxle, 786 -uhaddsubxal, 786 -uhaddsubxlo, 786 -uhaddsubxcc, 786 -uhaddsubxhs, 786 -uhaddsubxcs, 786 -uhaddsubxnv, 786 -uhasx, 786 -uhasxeq, 786 -uhasxne, 786 -uhasxmi, 786 -uhasxpl, 786 -uhasxvs, 786 -uhasxvc, 786 -uhasxhi, 786 -uhasxls, 786 -uhasxge, 786 -uhasxlt, 786 -uhasxgt, 786 -uhasxle, 786 -uhasxal, 786 -uhasxlo, 786 -uhasxcc, 786 -uhasxhs, 786 -uhasxcs, 786 -uhasxnv, 786 -uhsubaddx,788 -uhsubaddxeq, 788 -uhsubaddxne, 788 -uhsubaddxmi, 788 -uhsubaddxpl, 788 -uhsubaddxvs, 788 -uhsubaddxvc, 788 -uhsubaddxhi, 788 -uhsubaddxls, 788 -uhsubaddxge, 788 -uhsubaddxlt, 788 -uhsubaddxgt, 788 -uhsubaddxle, 788 -uhsubaddxal, 788 -uhsubaddxlo, 788 -uhsubaddxcc, 788 -uhsubaddxhs, 788 -uhsubaddxcs, 788 -uhsubaddxnv, 788 -uhsax, 788 -uhsaxeq, 788 -uhsaxne, 788 -uhsaxmi, 788 -uhsaxpl, 788 -uhsaxvs, 788 -uhsaxvc, 788 -uhsaxhi, 788 -uhsaxls, 788 -uhsaxge, 788 -uhsaxlt, 788 -uhsaxgt, 788 -uhsaxle, 788 -uhsaxal, 788 -uhsaxlo, 788 -uhsaxcc, 788 -uhsaxhs, 788 -uhsaxcs, 788 -uhsaxnv, 788 -uhsub16, 790 -uhsub16eq, 790 -uhsub16ne, 790 -uhsub16mi, 790 -uhsub16pl, 790 -uhsub16vs, 790 -uhsub16vc, 790 -uhsub16hi, 790 -uhsub16ls, 790 -uhsub16ge, 790 -uhsub16lt, 790 -uhsub16gt, 790 -uhsub16le, 790 -uhsub16al, 790 -uhsub16lo, 790 -uhsub16cc, 790 -uhsub16hs, 790 -uhsub16cs, 790 -uhsub16nv, 790 -uhsub8, 792 -uhsub8eq, 792 -uhsub8ne, 792 -uhsub8mi, 792 -uhsub8pl, 792 -uhsub8vs, 792 -uhsub8vc, 792 -uhsub8hi, 792 -uhsub8ls, 792 -uhsub8ge, 792 -uhsub8lt, 792 -uhsub8gt, 792 -uhsub8le, 792 -uhsub8al, 792 -uhsub8lo, 792 -uhsub8cc, 792 -uhsub8hs, 792 -uhsub8cs, 792 -uhsub8nv, 792 -umaal, 794 -umaaleq, 794 -umaalne, 794 -umaalmi, 794 -umaalpl, 794 -umaalvs, 794 -umaalvc, 794 -umaalhi, 794 -umaalls, 794 -umaalge, 794 -umaallt, 794 -umaalgt, 794 -umaalle, 794 -umaalal, 794 -umaallo, 794 -umaalcc, 794 -umaalhs, 794 -umaalcs, 794 -umaalnv, 794 -umlal, 796 -umlaleq, 796 -umlalne, 796 -umlalmi, 796 -umlalpl, 796 -umlalvs, 796 -umlalvc, 796 -umlalhi, 796 -umlalls, 796 -umlalge, 796 -umlallt, 796 -umlalgt, 796 -umlalle, 796 -umlalal, 796 -umlallo, 796 -umlalcc, 796 -umlalhs, 796 -umlalcs, 796 -umlalnv, 796 -umlals, 796 -umlaleqs, 796 -umlalnes, 796 -umlalmis, 796 -umlalpls, 796 -umlalvss, 796 -umlalvcs, 796 -umlalhis, 796 -umlallss, 796 -umlalges, 796 -umlallts, 796 -umlalgts, 796 -umlalles, 796 -umlalals, 796 -umlallos, 796 -umlalccs, 796 -umlalhss, 796 -umlalcss, 796 -umlalnvs, 796 -umlals, 796 -umlalseq, 796 -umlalsne, 796 -umlalsmi, 796 -umlalspl, 796 -umlalsvs, 796 -umlalsvc, 796 -umlalshi, 796 -umlalsls, 796 -umlalsge, 796 -umlalslt, 796 -umlalsgt, 796 -umlalsle, 796 -umlalsal, 796 -umlalslo, 796 -umlalscc, 796 -umlalshs, 796 -umlalscs, 796 -umlalsnv, 796 -umull, 798 -umulleq, 798 -umullne, 798 -umullmi, 798 -umullpl, 798 -umullvs, 798 -umullvc, 798 -umullhi, 798 -umullls, 798 -umullge, 798 -umulllt, 798 -umullgt, 798 -umullle, 798 -umullal, 798 -umulllo, 798 -umullcc, 798 -umullhs, 798 -umullcs, 798 -umullnv, 798 -umulls, 798 -umulleqs, 798 -umullnes, 798 -umullmis, 798 -umullpls, 798 -umullvss, 798 -umullvcs, 798 -umullhis, 798 -umulllss, 798 -umullges, 798 -umulllts, 798 -umullgts, 798 -umullles, 798 -umullals, 798 -umulllos, 798 -umullccs, 798 -umullhss, 798 -umullcss, 798 -umullnvs, 798 -umulls, 798 -umullseq, 798 -umullsne, 798 -umullsmi, 798 -umullspl, 798 -umullsvs, 798 -umullsvc, 798 -umullshi, 798 -umullsls, 798 -umullsge, 798 -umullslt, 798 -umullsgt, 798 -umullsle, 798 -umullsal, 798 -umullslo, 798 -umullscc, 798 -umullshs, 798 -umullscs, 798 -umullsnv, 798 -uqadd16, 800 -uqadd16eq, 800 -uqadd16ne, 800 -uqadd16mi, 800 -uqadd16pl, 800 -uqadd16vs, 800 -uqadd16vc, 800 -uqadd16hi, 800 -uqadd16ls, 800 -uqadd16ge, 800 -uqadd16lt, 800 -uqadd16gt, 800 -uqadd16le, 800 -uqadd16al, 800 -uqadd16lo, 800 -uqadd16cc, 800 -uqadd16hs, 800 -uqadd16cs, 800 -uqadd16nv, 800 -uqadd8, 802 -uqadd8eq, 802 -uqadd8ne, 802 -uqadd8mi, 802 -uqadd8pl, 802 -uqadd8vs, 802 -uqadd8vc, 802 -uqadd8hi, 802 -uqadd8ls, 802 -uqadd8ge, 802 -uqadd8lt, 802 -uqadd8gt, 802 -uqadd8le, 802 -uqadd8al, 802 -uqadd8lo, 802 -uqadd8cc, 802 -uqadd8hs, 802 -uqadd8cs, 802 -uqadd8nv, 802 -uqaddsubx, 804 -uqaddsubxeq, 804 -uqaddsubxne, 804 -uqaddsubxmi, 804 -uqaddsubxpl, 804 -uqaddsubxvs, 804 -uqaddsubxvc, 804 -uqaddsubxhi, 804 -uqaddsubxls, 804 -uqaddsubxge, 804 -uqaddsubxlt, 804 -uqaddsubxgt, 804 -uqaddsubxle, 804 -uqaddsubxal, 804 -uqaddsubxlo, 804 -uqaddsubxcc, 804 -uqaddsubxhs, 804 -uqaddsubxcs, 804 -uqaddsubxnv, 804 -uqasx, 804 -uqasxeq, 804 -uqasxne, 804 -uqasxmi, 804 -uqasxpl, 804 -uqasxvs, 804 -uqasxvc, 804 -uqasxhi, 804 -uqasxls, 804 -uqasxge, 804 -uqasxlt, 804 -uqasxgt, 804 -uqasxle, 804 -uqasxal, 804 -uqasxlo, 804 -uqasxcc, 804 -uqasxhs, 804 -uqasxcs, 804 -uqasxnv, 804 -uqsubaddx, 806 -uqsubaddxeq, 806 -uqsubaddxne, 806 -uqsubaddxmi, 806 -uqsubaddxpl, 806 -uqsubaddxvs, 806 -uqsubaddxvc, 806 -uqsubaddxhi, 806 -uqsubaddxls, 806 -uqsubaddxge, 806 -uqsubaddxlt, 806 -uqsubaddxgt, 806 -uqsubaddxle, 806 -uqsubaddxal, 806 -uqsubaddxlo, 806 -uqsubaddxcc, 806 -uqsubaddxhs, 806 -uqsubaddxcs, 806 -uqsubaddxnv, 806 -uqsax, 806 -uqsaxeq, 806 -uqsaxne, 806 -uqsaxmi, 806 -uqsaxpl, 806 -uqsaxvs, 806 -uqsaxvc, 806 -uqsaxhi, 806 -uqsaxls, 806 -uqsaxge, 806 -uqsaxlt, 806 -uqsaxgt, 806 -uqsaxle, 806 -uqsaxal, 806 -uqsaxlo, 806 -uqsaxcc, 806 -uqsaxhs, 806 -uqsaxcs, 806 -uqsaxnv, 806 -uqsub16, 808 -uqsub16eq, 808 -uqsub16ne, 808 -uqsub16mi, 808 -uqsub16pl, 808 -uqsub16vs, 808 -uqsub16vc, 808 -uqsub16hi, 808 -uqsub16ls, 808 -uqsub16ge, 808 -uqsub16lt, 808 -uqsub16gt, 808 -uqsub16le, 808 -uqsub16al, 808 -uqsub16lo, 808 -uqsub16cc, 808 -uqsub16hs, 808 -uqsub16cs, 808 -uqsub16nv, 808 -uqsub8, 810 -uqsub8eq, 810 -uqsub8ne, 810 -uqsub8mi, 810 -uqsub8pl, 810 -uqsub8vs, 810 -uqsub8vc, 810 -uqsub8hi, 810 -uqsub8ls, 810 -uqsub8ge, 810 -uqsub8lt, 810 -uqsub8gt, 810 -uqsub8le, 810 -uqsub8al, 810 -uqsub8lo, 810 -uqsub8cc, 810 -uqsub8hs, 810 -uqsub8cs, 810 -uqsub8nv, 810 -usad8, 812 -usad8eq, 812 -usad8ne, 812 -usad8mi, 812 -usad8pl, 812 -usad8vs, 812 -usad8vc, 812 -usad8hi, 812 -usad8ls, 812 -usad8ge, 812 -usad8lt, 812 -usad8gt, 812 -usad8le, 812 -usad8al, 812 -usad8lo, 812 -usad8cc, 812 -usad8hs, 812 -usad8cs, 812 -usad8nv, 812 -usada8, 814 -usada8eq, 814 -usada8ne, 814 -usada8mi, 814 -usada8pl, 814 -usada8vs, 814 -usada8vc, 814 -usada8hi, 814 -usada8ls, 814 -usada8ge, 814 -usada8lt, 814 -usada8gt, 814 -usada8le, 814 -usada8al, 814 -usada8lo, 814 -usada8cc, 814 -usada8hs, 814 -usada8cs, 814 -usada8nv, 814 -usat, 816 -usateq, 816 -usatne, 816 -usatmi, 816 -usatpl, 816 -usatvs, 816 -usatvc, 816 -usathi, 816 -usatls, 816 -usatge, 816 -usatlt, 816 -usatgt, 816 -usatle, 816 -usatal, 816 -usatlo, 816 -usatcc, 816 -usaths, 816 -usatcs, 816 -usatnv, 816 -usat16, 818 -usat16eq, 818 -usat16ne, 818 -usat16mi, 818 -usat16pl, 818 -usat16vs, 818 -usat16vc, 818 -usat16hi, 818 -usat16ls, 818 -usat16ge, 818 -usat16lt, 818 -usat16gt, 818 -usat16le, 818 -usat16al, 818 -usat16lo, 818 -usat16cc, 818 -usat16hs, 818 -usat16cs, 818 -usat16nv, 818 -usubaddx, 820 -usubaddxeq, 820 -usubaddxne, 820 -usubaddxmi, 820 -usubaddxpl, 820 -usubaddxvs, 820 -usubaddxvc, 820 -usubaddxhi, 820 -usubaddxls, 820 -usubaddxge, 820 -usubaddxlt, 820 -usubaddxgt, 820 -usubaddxle, 820 -usubaddxal, 820 -usubaddxlo, 820 -usubaddxcc, 820 -usubaddxhs, 820 -usubaddxcs, 820 -usubaddxnv, 820 -usax, 820 -usaxeq, 820 -usaxne, 820 -usaxmi, 820 -usaxpl, 820 -usaxvs, 820 -usaxvc, 820 -usaxhi, 820 -usaxls, 820 -usaxge, 820 -usaxlt, 820 -usaxgt, 820 -usaxle, 820 -usaxal, 820 -usaxlo, 820 -usaxcc, 820 -usaxhs, 820 -usaxcs, 820 -usaxnv, 820 -usub16, 822 -usub16eq, 822 -usub16ne, 822 -usub16mi, 822 -usub16pl, 822 -usub16vs, 822 -usub16vc, 822 -usub16hi, 822 -usub16ls, 822 -usub16ge, 822 -usub16lt, 822 -usub16gt, 822 -usub16le, 822 -usub16al, 822 -usub16lo, 822 -usub16cc, 822 -usub16hs, 822 -usub16cs, 822 -usub16nv, 822 -usub8, 824 -usub8eq, 824 -usub8ne, 824 -usub8mi, 824 -usub8pl, 824 -usub8vs, 824 -usub8vc, 824 -usub8hi, 824 -usub8ls, 824 -usub8ge, 824 -usub8lt, 824 -usub8gt, 824 -usub8le, 824 -usub8al, 824 -usub8lo, 824 -usub8cc, 824 -usub8hs, 824 -usub8cs, 824 -usub8nv, 824 -uxtab, 826 -uxtabeq, 826 -uxtabne, 826 -uxtabmi, 826 -uxtabpl, 826 -uxtabvs, 826 -uxtabvc, 826 -uxtabhi, 826 -uxtabls, 826 -uxtabge, 826 -uxtablt, 826 -uxtabgt, 826 -uxtable, 826 -uxtabal, 826 -uxtablo, 826 -uxtabcc, 826 -uxtabhs, 826 -uxtabcs, 826 -uxtabnv, 826 -uxtab16, 828 -uxtab16eq, 828 -uxtab16ne, 828 -uxtab16mi, 828 -uxtab16pl, 828 -uxtab16vs, 828 -uxtab16vc, 828 -uxtab16hi, 828 -uxtab16ls, 828 -uxtab16ge, 828 -uxtab16lt, 828 -uxtab16gt, 828 -uxtab16le, 828 -uxtab16al, 828 -uxtab16lo, 828 -uxtab16cc, 828 -uxtab16hs, 828 -uxtab16cs, 828 -uxtab16nv, 828 -uxtah, 830 -uxtaheq, 830 -uxtahne, 830 -uxtahmi, 830 -uxtahpl, 830 -uxtahvs, 830 -uxtahvc, 830 -uxtahhi, 830 -uxtahls, 830 -uxtahge, 830 -uxtahlt, 830 -uxtahgt, 830 -uxtahle, 830 -uxtahal, 830 -uxtahlo, 830 -uxtahcc, 830 -uxtahhs, 830 -uxtahcs, 830 -uxtahnv, 830 -uxtb, 832 -uxtbeq, 832 -uxtbne, 832 -uxtbmi, 832 -uxtbpl, 832 -uxtbvs, 832 -uxtbvc, 832 -uxtbhi, 832 -uxtbls, 832 -uxtbge, 832 -uxtblt, 832 -uxtbgt, 832 -uxtble, 832 -uxtbal, 832 -uxtblo, 832 -uxtbcc, 832 -uxtbhs, 832 -uxtbcs, 832 -uxtbnv, 832 -uxtb16, 834 -uxtb16eq, 834 -uxtb16ne, 834 -uxtb16mi, 834 -uxtb16pl, 834 -uxtb16vs, 834 -uxtb16vc, 834 -uxtb16hi, 834 -uxtb16ls, 834 -uxtb16ge, 834 -uxtb16lt, 834 -uxtb16gt, 834 -uxtb16le, 834 -uxtb16al, 834 -uxtb16lo, 834 -uxtb16cc, 834 -uxtb16hs, 834 -uxtb16cs, 834 -uxtb16nv, 834 -uxth, 836 -uxtheq, 836 -uxthne, 836 -uxthmi, 836 -uxthpl, 836 -uxthvs, 836 -uxthvc, 836 -uxthhi, 836 -uxthls, 836 -uxthge, 836 -uxthlt, 836 -uxthgt, 836 -uxthle, 836 -uxthal, 836 -uxthlo, 836 -uxthcc, 836 -uxthhs, 836 -uxthcs, 836 -uxthnv, 836 -vaba, 838 -vabal, 838 -vabd, 840 -vabdl, 840 -vabs, 844 -vacge, 846 -vacgt, 846 -vacle, 846 -vaclt, 846 -vadd, 848 -vaddhn, 852 -vaddl, 854 -vaddw, 854 -vand, 856 -vbic, 858 -vbif, 862 -vbit, 862 -vbsl, 862 -vceq, 864 -vcge, 868 -vcgt, 872 -vcle, 876 -vcls, 878 -vclt, 880 -vclz, 882 -vcmp, 884 -vcmpeq, 884 -vcmpne, 884 -vcmpmi, 884 -vcmppl, 884 -vcmpvs, 884 -vcmpvc, 884 -vcmphi, 884 -vcmpls, 884 -vcmpge, 884 -vcmplt, 884 -vcmpgt, 884 -vcmple, 884 -vcmpal, 884 -vcmplo, 884 -vcmpcc, 884 -vcmphs, 884 -vcmpcs, 884 -vcmpnv, 884 -vcmpe, 884 -vcmpeeq, 884 -vcmpene, 884 -vcmpemi, 884 -vcmpepl, 884 -vcmpevs, 884 -vcmpevc, 884 -vcmpehi, 884 -vcmpels, 884 -vcmpege, 884 -vcmpelt, 884 -vcmpegt, 884 -vcmpele, 884 -vcmpeal, 884 -vcmpelo, 884 -vcmpecc, 884 -vcmpehs, 884 -vcmpecs, 884 -vcmpenv, 884 -vcnt, 886 -vcvt, 888 -vcvteq, 888 -vcvtne, 888 -vcvtmi, 888 -vcvtpl, 888 -vcvtvs, 888 -vcvtvc, 888 -vcvthi, 888 -vcvtls, 888 -vcvtge, 888 -vcvtlt, 888 -vcvtgt, 888 -vcvtle, 888 -vcvtal, 888 -vcvtlo, 888 -vcvtcc, 888 -vcvths, 888 -vcvtcs, 888 -vcvtnv, 888 -vcvtr, 890 -vcvtreq, 890 -vcvtrne, 890 -vcvtrmi, 890 -vcvtrpl, 890 -vcvtrvs, 890 -vcvtrvc, 890 -vcvtrhi, 890 -vcvtrls, 890 -vcvtrge, 890 -vcvtrlt, 890 -vcvtrgt, 890 -vcvtrle, 890 -vcvtral, 890 -vcvtrlo, 890 -vcvtrcc, 890 -vcvtrhs, 890 -vcvtrcs, 890 -vcvtrnv, 890 -vcvtb, 900 -vcvtbeq, 900 -vcvtbne, 900 -vcvtbmi, 900 -vcvtbpl, 900 -vcvtbvs, 900 -vcvtbvc, 900 -vcvtbhi, 900 -vcvtbls, 900 -vcvtbge, 900 -vcvtblt, 900 -vcvtbgt, 900 -vcvtble, 900 -vcvtbal, 900 -vcvtblo, 900 -vcvtbcc, 900 -vcvtbhs, 900 -vcvtbcs, 900 -vcvtbnv, 900 -vcvtt, 900 -vcvtteq, 900 -vcvttne, 900 -vcvttmi, 900 -vcvttpl, 900 -vcvttvs, 900 -vcvttvc, 900 -vcvtthi, 900 -vcvttls, 900 -vcvttge, 900 -vcvttlt, 900 -vcvttgt, 900 -vcvttle, 900 -vcvttal, 900 -vcvttlo, 900 -vcvttcc, 900 -vcvtths, 900 -vcvttcs, 900 -vcvttnv, 900 -vdiv, 902 -vdiveq, 902 -vdivne, 902 -vdivmi, 902 -vdivpl, 902 -vdivvs, 902 -vdivvc, 902 -vdivhi, 902 -vdivls, 902 -vdivge, 902 -vdivlt, 902 -vdivgt, 902 -vdivle, 902 -vdival, 902 -vdivlo, 902 -vdivcc, 902 -vdivhs, 902 -vdivcs, 902 -vdivnv, 902 -vdup, 904 -veor, 908 -vext, 910 -vhadd, 912 -vhsub, 912 -vld1, 914 -vld2, 920 -vld3, 926 -vld4, 932 -vldmia, 938 -vldmiaeq, 938 -vldmiane, 938 -vldmiami, 938 -vldmiapl, 938 -vldmiavs, 938 -vldmiavc, 938 -vldmiahi, 938 -vldmials, 938 -vldmiage, 938 -vldmialt, 938 -vldmiagt, 938 -vldmiale, 938 -vldmiaal, 938 -vldmialo, 938 -vldmiacc, 938 -vldmiahs, 938 -vldmiacs, 938 -vldmianv, 938 -vldmdb, 938 -vldmdbeq, 938 -vldmdbne, 938 -vldmdbmi, 938 -vldmdbpl, 938 -vldmdbvs, 938 -vldmdbvc, 938 -vldmdbhi, 938 -vldmdbls, 938 -vldmdbge, 938 -vldmdblt, 938 -vldmdbgt, 938 -vldmdble, 938 -vldmdbal, 938 -vldmdblo, 938 -vldmdbcc, 939 -vldmdbhs, 939 -vldmdbcs, 939 -vldmdbnv, 939 -vldr, 940 -vldreq, 940 -vldrne, 940 -vldrmi, 940 -vldrpl, 940 -vldrvs, 940 -vldrvc, 940 -vldrhi, 940 -vldrls, 940 -vldrge, 940 -vldrlt, 940 -vldrgt, 940 -vldrle, 940 -vldral, 940 -vldrlo, 940 -vldrcc, 940 -vldrhs, 940 -vldrcs, 940 -vldrnv, 940 -vmax, 942 -vmin, 942 -vmla, 946 -vmlal, 946 -vmls, 946 -vmlsl, 946 -vmov, 952 -vmoveq, 956 -vmovne, 956 -vmovmi, 956 -vmovpl, 956 -vmovvs, 956 -vmovvc, 956 -vmovhi, 956 -vmovls, 956 -vmovge, 956 -vmovlt, 956 -vmovgt, 956 -vmovle, 956 -vmoval, 956 -vmovlo, 956 -vmovcc, 956 -vmovhs, 956 -vmovcs, 956 -vmovnv, 956 -vmovl, 966 -vmovn, 968 -vmrs, 970 -vmrseq, 970 -vmrsne, 970 -vmrsmi, 970 -vmrspl, 970 -vmrsvs, 970 -vmrsvc, 970 -vmrshi, 970 -vmrsls, 970 -vmrsge, 970 -vmrslt, 970 -vmrsgt, 970 -vmrsle, 970 -vmrsal, 970 -vmrslo, 970 -vmrscc, 970 -vmrshs, 970 -vmrscs, 970 -vmrsnv, 970 -vmsr, 972 -vmsreq, 972 -vmsrne, 972 -vmsrmi, 972 -vmsrpl, 972 -vmsrvs, 972 -vmsrvc, 972 -vmsrhi, 972 -vmsrls, 972 -vmsrge, 972 -vmsrlt, 972 -vmsrgt, 972 -vmsrle, 972 -vmsral, 972 -vmsrlo, 972 -vmsrcc, 972 -vmsrhs, 972 -vmsrcs, 972 -vmsrnv, 972 -vmul, 974 -vmull, 974 -vmvn, 980 -vneg, 984 -vnmla, 986 -vnmlaeq, 986 -vnmlane, 986 -vnmlami, 986 -vnmlapl, 986 -vnmlavs, 986 -vnmlavc, 986 -vnmlahi, 986 -vnmlals, 986 -vnmlage, 986 -vnmlalt, 986 -vnmlagt, 986 -vnmlale, 986 -vnmlaal, 986 -vnmlalo, 986 -vnmlacc, 986 -vnmlahs, 986 -vnmlacs, 986 -vnmlanv, 986 -vnmls, 986 -vnmlseq, 986 -vnmlsne, 986 -vnmlsmi, 986 -vnmlspl, 986 -vnmlsvs, 986 -vnmlsvc, 986 -vnmlshi, 986 -vnmlsls, 986 -vnmlsge, 986 -vnmlslt, 986 -vnmlsgt, 986 -vnmlsle, 986 -vnmlsal, 986 -vnmlslo, 986 -vnmlscc, 986 -vnmlshs, 986 -vnmlscs, 986 -vnmlsnv, 986 -vnmul, 986 -vnmuleq, 986 -vnmulne, 986 -vnmulmi, 986 -vnmulpl, 986 -vnmulvs, 986 -vnmulvc, 986 -vnmulhi, 986 -vnmulls, 986 -vnmulge, 986 -vnmullt, 986 -vnmulgt, 986 -vnmulle, 986 -vnmulal, 986 -vnmullo, 986 -vnmulcc, 986 -vnmulhs, 986 -vnmulcs, 986 -vnmulnv, 986 -vorn, 988 -vorr, 990 -vpadal, 994 -vpadd, 996 -vpaddl, 1000 -vpmax, 1002 -vpmin, 1002 -vpop, 1006 -vpopeq, 1006 -vpopne, 1006 -vpopmi, 1006 -vpoppl, 1006 -vpopvs, 1006 -vpopvc, 1006 -vpophi, 1006 -vpopls, 1006 -vpopge, 1006 -vpoplt, 1006 -vpopgt, 1006 -vpople, 1006 -vpopal, 1006 -vpoplo, 1006 -vpopcc, 1006 -vpophs, 1006 -vpopcs, 1006 -vpopnv, 1006 -vpush, 1008 -vpusheq, 1008 -vpushne, 1008 -vpushmi, 1008 -vpushpl, 1008 -vpushvs, 1008 -vpushvc, 1008 -vpushhi, 1008 -vpushls, 1008 -vpushge, 1008 -vpushlt, 1008 -vpushgt, 1008 -vpushle, 1008 -vpushal, 1008 -vpushlo, 1008 -vpushcc, 1008 -vpushhs, 1008 -vpushcs, 1008 -vpushnv, 1008 -vqabs, 1010 -vqadd, 1012 -vqdmlal, 1014 -vqdmlsl, 1014 -vqdmulh, 1016 -vqdmull, 1018 -vqmovn, 1020 -vqmovun, 1020 -vqneg, 1022 -vqrdmulh, 1024 -vqrshl, 1026 -vqrshrn, 1028 -vqrshrun, 1028 -vqshl, 1030 -vqshlu, 1032 -vqshrn, 1034 -vqshrun, 1034 -vqsub, 1036 -vraddhn, 1038 -vrecpe, 1040 -vrecps, 1042 -vrev16, 1044 -vrev32, 1044 -vrev64, 1044 -vrhadd, 1046 -vrshl, 1048 -vrshr, 1050 -vrshrn, 1052 -vrsqrte, 1054 -vrsqrts, 1056 -vrsra, 1058 -vrsubhn, 1060 -vshl, 1062 -vshll, 1066 -vshr, 1068 -vshrn, 1070 -vsli, 1072 -vsqrt, 1074 -vsqrteq, 1074 -vsqrtne, 1074 -vsqrtmi, 1074 -vsqrtpl, 1074 -vsqrtvs, 1074 -vsqrtvc, 1074 -vsqrthi, 1074 -vsqrtls, 1074 -vsqrtge, 1074 -vsqrtlt, 1074 -vsqrtgt, 1074 -vsqrtle, 1074 -vsqrtal, 1074 -vsqrtlo, 1074 -vsqrtcc, 1074 -vsqrths, 1074 -vsqrtcs, 1074 -vsqrtnv, 1074 -vsra, 1076 -vsri, 1078 -vst1, 1080 -vst2, 1084 -vst3, 1088 -vst4, 1092 -vstmia, 1096 -vstmiaeq, 1096 -vstmiane, 1096 -vstmiami, 1096 -vstmiapl, 1096 -vstmiavs, 1096 -vstmiavc, 1096 -vstmiahi, 1096 -vstmials, 1096 -vstmiage, 1096 -vstmialt, 1096 -vstmiagt, 1096 -vstmiale, 1096 -vstmiaal, 1096 -vstmialo, 1096 -vstmiacc, 1096 -vstmiahs, 1096 -vstmiacs, 1096 -vstmianv, 1096 -vstmdb, 1096 -vstmdbeq, 1096 -vstmdbne, 1096 -vstmdbmi, 1096 -vstmdbpl, 1096 -vstmdbvs, 1096 -vstmdbvc, 1096 -vstmdbhi, 1096 -vstmdbls, 1096 -vstmdbge, 1096 -vstmdblt, 1096 -vstmdbgt, 1096 -vstmdble, 1096 -vstmdbal, 1096 -vstmdblo, 1096 -vstmdbcc, 1096 -vstmdbhs, 1096 -vstmdbcs, 1096 -vstmdbnv, 1096 -vstr, 1098 -vstreq, 1098 -vstrne, 1098 -vstrmi, 1098 -vstrpl, 1098 -vstrvs, 1098 -vstrvc, 1098 -vstrhi, 1098 -vstrls, 1098 -vstrge, 1098 -vstrlt, 1098 -vstrgt, 1098 -vstrle, 1098 -vstral, 1098 -vstrlo, 1098 -vstrcc, 1098 -vstrhs, 1098 -vstrcs, 1098 -vstrnv, 1098 -vsub, 1100 -vsubeq, 1100 -vsubne, 1100 -vsubmi, 1100 -vsubpl, 1100 -vsubvs, 1100 -vsubvc, 1100 -vsubhi, 1100 -vsubls, 1100 -vsubge, 1100 -vsublt, 1100 -vsubgt, 1100 -vsuble, 1100 -vsubal, 1100 -vsublo, 1100 -vsubcc, 1100 -vsubhs, 1100 -vsubcs, 1100 -vsubnv, 1100 -vsubhn, 1104 -vsubl, 1106 -vsubw, 1106 -vswp, 1108 -vtbl, 1110 -vtbx, 1110 -vtrn, 1112 -vtst, 1114 -vuzp, 1116 -vzip, 1118 -wfe, 1120 -wfeeq, 1120 -wfene, 1120 -wfemi, 1120 -wfepl, 1120 -wfevs, 1120 -wfevc, 1120 -wfehi, 1120 -wfels, 1120 -wfege, 1120 -wfelt, 1120 -wfegt, 1120 -wfele, 1120 -wfeal, 1120 -wfelo, 1120 -wfecc, 1120 -wfehs, 1120 -wfecs, 1120 -wfenv, 1120 -wfi, 1122 -wfieq, 1122 -wfine, 1122 -wfimi, 1122 -wfipl, 1122 -wfivs, 1122 -wfivc, 1122 -wfihi, 1122 -wfils, 1122 -wfige, 1122 -wfilt, 1122 -wfigt, 1122 -wfile, 1122 -wfial, 1122 -wfilo, 1122 -wficc, 1122 -wfihs, 1122 -wfics, 1122 -wfinv, 1122 -yield, 1124 -yieldeq, 1124 -yieldne, 1124 -yieldmi, 1124 -yieldpl, 1124 -yieldvs, 1124 -yieldvc, 1124 -yieldhi, 1124 -yieldls, 1124 -yieldge, 1124 -yieldlt, 1124 -yieldgt, 1124 -yieldle, 1124 -yieldal, 1124 -yieldlo, 1124 -yieldcc, 1124 -yieldhs, 1124 -yieldcs, 1124 -yieldnv, 1124 +adc, 7136 +add, 7155 +adr, 7157 +aesd, 7853 +aese, 7855 +aesimc, 7857 +aesmc, 7859 +and, 7167 +asr, 7171 +asrs, 7175 +b, 7177 +bfc, 7180 +bfi, 7182 +bic, 7191 +bkpt, 7193 +bl, 7195 +blx, 7198 +bx, 7200 +bxj, 7202 +cbnz, 7203 +clrex, 7204 +clz, 7205 +cmn, 7212 +cmp, 7219 +cps, 7221 +crc32, 7226 +crc32c, 7229 +csdb, 7232 +dbg, 7234 +dcps1, 7235 +dcps2, 7237 +dcps3, 7239 +dmb, 7241 +dsb, 7244 +eor, 7254 +eret, 7256 +esb, 7258 +fldm, 7861 +fstmdbx, 7864 +hlt, 7260 +hvc, 7262 +isb, 7264 +it, 7266 +lda, 7268 +ldab, 7270 +ldaex, 7272 +ldaexb, 7274 +ldaexd, 7276 +ldaexh, 7278 +ldah, 7280 +ldc, 7284 +ldm, 7292 +ldmda, 7294 +ldmdb, 7296 +ldmib, 7299 +ldr, 7308 +ldrb, 7317 +ldrbt, 7320 +ldrd, 7329 +ldrex, 7332 +ldrexb, 7334 +ldrexd, 7336 +ldrexh, 7338 +ldrh, 7346 +ldrht, 7349 +ldrsb, 7357 +ldrsbt, 7360 +ldrsh, 7368 +ldrsht, 7371 +ldrt, 7374 +lsl, 7379 +lsls, 7383 +lsr, 7387 +lsrs, 7391 +mcr, 7393 +mcrr, 7395 +mla, 7397 +mls, 7399 +mov, 7411 +movt, 7415 +mrc, 7417 +mrrc, 7419 +mrs, 7423 +msr, 7433 +mul, 7436 +mvn, 7443 +nop, 7445 +orn, 7449 +orr, 7458 +pkhbt, 7460 +pld, 7468 +pli, 7474 +pop, 7480 +pssbb, 7482 +push, 7488 +qadd, 7489 +qadd16, 7491 +qadd8, 7493 +qasx, 7495 +qdadd, 7497 +qdsub, 7499 +qsax, 7501 +qsub, 7503 +qsub16, 7505 +qsub8, 7507 +rbit, 7509 +rev, 7511 +rev16, 7513 +revsh, 7515 +rfe, 7517 +ror, 7522 +rors, 7526 +rrx, 7528 +rrxs, 7530 +rsb, 7538 +rsc, 7544 +sadd16, 7546 +sadd8, 7548 +sasx, 7550 +sb, 7552 +sbc, 7561 +sbfx, 7563 +sdiv, 7565 +sel, 7567 +setend, 7569 +setpan, 7570 +sev, 7571 +sevl, 7573 +sha1c, 7867 +sha1h, 7869 +sha1m, 7871 +sha1p, 7873 +sha1su0, 7875 +sha1su1, 7877 +sha256h, 7879 +sha256h2, 7881 +sha256su0, 7883 +sha256su1, 7885 +shadd16, 7575 +shadd8, 7577 +shasx, 7579 +shsax, 7581 +shsub16, 7583 +shsub8, 7585 +smc, 7587 +smlabb, 7589 +smlad, 7591 +smlal, 7593 +smlalbb, 7595 +smlald, 7598 +smlawb, 7601 +smlsd, 7603 +smlsld, 7605 +smmla, 7607 +smmls, 7609 +smmul, 7611 +smuad, 7613 +smulbb, 7615 +smull, 7617 +smulwb, 7619 +smusd, 7621 +srs, 7623 +ssat, 7627 +ssat16, 7629 +ssax, 7631 +ssbb, 7633 +ssub16, 7635 +ssub8, 7637 +stc, 7639 +stl, 7642 +stlb, 7644 +stlex, 7646 +stlexb, 7649 +stlexd, 7651 +stlexh, 7654 +stlh, 7657 +stm, 7663 +stmda, 7665 +stmdb, 7667 +stmib, 7670 +str, 7677 +strb, 7684 +strbt, 7687 +strd, 7695 +strex, 7698 +strexb, 7701 +strexd, 7703 +strexh, 7706 +strh, 7713 +strht, 7716 +strt, 7720 +sub, 7739 +svc, 7742 +sxtab, 7744 +sxtab16, 7746 +sxtah, 7748 +sxtb, 7750 +sxtb16, 7752 +sxth, 7754 +tbb, 7756 +teq, 7762 +tsb, 7764 +tst, 7771 +uadd16, 7773 +uadd8, 7775 +uasx, 7777 +ubfx, 7779 +udf, 7781 +udiv, 7783 +uhadd16, 7785 +uhadd8, 7787 +uhasx, 7789 +uhsax, 7791 +uhsub16, 7793 +uhsub8, 7795 +umaal, 7797 +umlal, 7799 +umull, 7801 +uqadd16, 7803 +uqadd8, 7805 +uqasx, 7807 +uqsax, 7809 +uqsub16, 7811 +uqsub8, 7813 +usad8, 7815 +usada8, 7817 +usat, 7819 +usat16, 7821 +usax, 7823 +usub16, 7825 +usub8, 7827 +uxtab, 7829 +uxtab16, 7831 +uxtah, 7833 +uxtb, 7835 +uxtb16, 7837 +uxth, 7839 +vaba, 7887 +vabal, 7890 +vabd, 7894 +vabdl, 7897 +vabs, 7899 +vacge, 7903 +vacgt, 7908 +vacle, 7906 +vaclt, 7911 +vadd, 7917 +vaddhn, 7919 +vaddl, 7921 +vaddw, 7923 +vand, 7928 +vbic, 7933 +vbif, 7935 +vbit, 7937 +vbsl, 7939 +vcadd, 7941 +vceq, 7946 +vcge, 7953 +vcgt, 7960 +vcle, 7967 +vcls, 7970 +vclt, 7975 +vclz, 7978 +vcmla, 7983 +vcmp, 7986 +vcmpe, 7990 +vcnt, 7994 +vcvt, 8015 +vcvta, 8021 +vcvtb, 8026 +vcvtm, 8030 +vcvtn, 8034 +vcvtp, 8038 +vcvtr, 8040 +vcvtt, 8047 +vdiv, 8049 +vdot, 8054 +vdup, 8058 +veor, 8060 +vext, 8065 +vfma, 8067 +vfmab, 8073 +vfmal, 8078 +vfms, 8081 +vfmsl, 8088 +vfnma, 8091 +vfnms, 8094 +vhadd, 8097 +vhsub, 8100 +vins, 8103 +vjcvt, 8105 +vld1, 8115 +vld2, 8131 +vld3, 8145 +vld4, 8157 +vldm, 8161 +vldr, 8169 +vmax, 8175 +vmaxnm, 8178 +vmin, 8185 +vminnm, 8188 +vmla, 8198 +vmlal, 8203 +vmls, 8211 +vmlsl, 8216 +vmmla, 8218 +vmov, 8241 +vmovl, 8244 +vmovn, 8246 +vmovx, 8248 +vmrs, 8250 +vmsr, 8253 +vmul, 8263 +vmull, 8269 +vmvn, 8275 +vneg, 8277 +vnmla, 8281 +vnmls, 8284 +vnmul, 8287 +vorn, 8293 +vorr, 8298 +vpadal, 8300 +vpadd, 8305 +vpaddl, 8307 +vpmax, 8312 +vpmin, 8316 +vpop, 8318 +vpush, 8320 +vqabs, 8322 +vqadd, 8324 +vqdmlal, 8326 +vqdmlsl, 8329 +vqdmulh, 8332 +vqdmull, 8336 +vqmovn, 8339 +vqneg, 8341 +vqrdmlah, 8343 +vqrdmlsh, 8347 +vqrdmulh, 8351 +vqrshl, 8355 +vqrshrn, 8359 +vqrshrun, 8362 +vqshl, 8367 +vqshrn, 8371 +vqshrun, 8374 +vqsub, 8376 +vraddhn, 8378 +vrecpe, 8380 +vrecps, 8382 +vrev16, 8384 +vrev32, 8387 +vrev64, 8390 +vrhadd, 8393 +vrinta, 8398 +vrintm, 8402 +vrintn, 8406 +vrintp, 8410 +vrintr, 8412 +vrintx, 8416 +vrintz, 8420 +vrshl, 8422 +vrshr, 8428 +vrshrn, 8432 +vrsqrte, 8434 +vrsqrts, 8436 +vrsra, 8438 +vrsubhn, 8441 +vsdot, 8445 +vseleq, 8447 +vshl, 8454 +vshll, 8457 +vshr, 8463 +vshrn, 8467 +vsli, 8469 +vsmmla, 8472 +vsqrt, 8474 +vsra, 8476 +vsri, 8479 +vst1, 8487 +vst2, 8501 +vst3, 8512 +vst4, 8522 +vstm, 8526 +vstr, 8531 +vsub, 8538 +vsubhn, 8540 +vsubl, 8542 +vsubw, 8544 +vsudot, 8546 +vswp, 8548 +vtbl, 8550 +vtrn, 8553 +vtst, 8556 +vudot, 8560 +vummla, 8562 +vusdot, 8566 +vusmmla, 8568 +vuzp, 8573 +vzip, 8577 +wfe, 7841 +wfi, 7843 +yield, 7845 \ No newline at end of file