diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
index 3437c42c8c..00d90c7820 100755
--- a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
@@ -1,4 +1,4 @@
-# Qualcomm Hexagon (V73) General Instruction Set
+# Qualcomm Hexagon (V60-V81) General Instruction Set
 
 #
 # Custom pcode-op
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec
index fa67708196..1d1e25f58e 100755
--- a/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec
@@ -1,12 +1,14 @@
 # Qualcomm Hexagon (V79) and HVX (V79)
 
 ## KNOWN ISSUES
-# 1. Shift amounts may be positive or negative, however in some cases no special handling 
-#    is provided for negative shift amounts.
+# 1. Shift amounts may be positive or negative.  The register-form shifts model the
+#    7-bit signed shift amount explicitly; other forms may still assume a positive amount.
 # 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops
 #
 ## NOTES
-# 1. Implementation includes V73 system registers, instruction set may be incomplete
+# 1. Implementation includes V73 system registers, instruction set may be incomplete.
+#    Decode additionally covers the V66 ZReg matrix extension and V81 valign4 as
+#    decode-only stubs (unimpl pcode).
 # 2. HVX register pairs may be access with a vector-swap mode (lsb of 5-bit field is 1)
 #    introduced with Hexagon v67.
 # 3. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes,
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
index 43509bb90b..35a3daf4a8 100644
--- a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
@@ -2,6 +2,8 @@
 
 # NOTES:
 # - HVX implementation has been updated through V79
+# - Decode additionally covers the V66 ZReg matrix family (vrmpyz / vr8mpyz / vr16mpyz
+#   and the z-register loads) plus V81 valign4, as decode-only stubs (unimpl pcode).
 # - HVX hardware supports either 64-byte or 128-byte vector lengths.  See hexagon.slaspec for
 #   default length of 128-bytes.