From 6c1352fc90d1340b96e8662bb6e94dfe0c5e18ba Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 29 Jun 2026 10:24:13 -0400 Subject: [PATCH] GP-7016: Corrected VPEXTRW to ignore the VEX.W1 bit --- Ghidra/Processors/x86/data/languages/avx.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/avx.sinc b/Ghidra/Processors/x86/data/languages/avx.sinc index 962aee4b1c..59b3dd6f07 100644 --- a/Ghidra/Processors/x86/data/languages/avx.sinc +++ b/Ghidra/Processors/x86/data/languages/avx.sinc @@ -1871,14 +1871,14 @@ define pcodeop vpextrq_avx ; # PEXTRW 4-277 PAGE 1397 LINE 72478 define pcodeop vpextrw_avx ; -:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 { Reg32 = vpextrw_avx( XmmReg2, imm8:1 ); # TODO Reg64 = zext(Reg32) } # PEXTRW 4-277 PAGE 1397 LINE 72483 -:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 +:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 { Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 ); # TODO Reg64 = zext(Reg32)