From 087216607aa8c4c9c7bb9312c1ce6cc0ac1d30a9 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 7 Oct 2019 09:27:58 -0400 Subject: [PATCH] GT-3202: Sparcv9, corrected pcode for 32-bit std instruction. --- .../Sparc/data/languages/SparcV9.sinc | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc b/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc index 632a1def96..2e2cb1f412 100644 --- a/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc +++ b/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc @@ -537,20 +537,19 @@ macro unpackflags(ccr) { # size = 4, but this extended store insn needs to write 8 bytes :stx RD,ea is op=3 & RD & rd_d & op3=0x0e & ea { - # There is a bug in the sleigh compiler that implements the tmp_hi:4 = rd_d[32,32] instruction incorrectly - #tmp_lo:4 = rd_d[0,32]; - #tmp_hi:4 = rd_d[32,32]; - #tmp:8 = zext(tmp_lo) + zext(tmp_hi << 32); - *ea = rd_d;#tmp; + tmp_lo:4 = rd_d[0,32]; + tmp_hi:4 = rd_d[32,32]; + tmp:8 = zext(tmp_lo) + (zext(tmp_hi) << 32); + *ea = tmp; } :clrx ea is op=3 & rd=0 & op3=0x0e & ea { *ea = 0:8; } :std RD,ea is op=3 & RD & rd_d & op3=0x07 & ea { - #tmp_lo:4 = rd_d[0,32]; - #tmp_hi:4 = rd_d[32,32]; - #tmp:8 = zext(tmp_lo) + zext(tmp_hi << 32); - *ea = rd_d;#tmp; + tmp_lo:4 = rd_d[0,32]; + tmp_hi:4 = rd_d[32,32]; + tmp:8 = zext(tmp_lo) + (zext(tmp_hi) << 32); + *ea = tmp; } :clrd ea is op=3 & rd=0 & op3=0x07 & ea { *ea = 0:8; }