From 0bbb92eb7a271fc2855ea099cfd09fc2ce648c7c Mon Sep 17 00:00:00 2001 From: Andrew Strelsky Date: Thu, 12 Jan 2023 12:04:14 -0500 Subject: [PATCH] x86-64 riprel fix --- Ghidra/Processors/x86/data/languages/ia.sinc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 15b5369f7b..5613ec111d 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -715,9 +715,9 @@ addr32: [Base + imm32] is mod=2 & r_m=4; index=4 & Base; imm32 { local addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { local tmp=Base+Index*ss; export tmp; } addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; } @ifdef IA64 -addr32: [RIP + simm32] is bit64=1 & mod=0 & r_m=4; index=4 & base=5; simm32 & RIP & pcRelSimm32 { export *[const]:4 pcRelSimm32; } +addr32: [pcRelSimm32] is bit64=1 & mod=0 & r_m=4; index=4 & base=5; pcRelSimm32 { export *[const]:4 pcRelSimm32; } -Addr32_64: [EIP + simm32] is mod=0 & r_m=5; simm32 & EIP & pcRelSimm32 { export *[const]:8 pcRelSimm32; } +Addr32_64: [pcRelSimm32] is mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; } Addr32_64: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:8 imm32; } Addr32_64: addr32 is addr32 { tmp:8 = sext(addr32); export tmp; } @@ -731,7 +731,7 @@ addr64: [Rmr64 + simm8_64] is mod=1 & Rmr64; simm8_64 addr64: [Rmr64 + simm32_64] is mod=2 & Rmr64; simm32_64 { local tmp=Rmr64+simm32_64; export tmp; } addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; } addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; } -addr64: [RIP + simm32] is mod=0 & r_m=5; simm32 & RIP & pcRelSimm32 { export *[const]:8 pcRelSimm32; } +addr64: [pcRelSimm32] is mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; } addr64: [Base64 + Index64*ss] is mod=0 & r_m=4; Index64 & Base64 & ss { local tmp=Base64+Index64*ss; export tmp; } addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; } addr64: [simm32_64 + Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { local tmp=simm32_64+Index64*ss; export tmp; }