From e606a9a18f6020653ecba78cf00d4a8f5fc21afd Mon Sep 17 00:00:00 2001 From: veritas501 Date: Tue, 11 May 2021 13:10:18 +0800 Subject: [PATCH 1/2] fix(mips32r6): jic is not call but jump See https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00086-2B-MIPS32BIS-AFP-6.06.pdf, page 205 (page 215 in file). jic is not like jialc, which set ra by `GPR[31] <- PC + 4`, it's just a jump. So, if meet jic reg,xxx , identify it as a jump. If meet jic ra,xxx , identify it as a return. --- .../MIPS/data/languages/mips32Instructions.sinc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc b/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc index e3b7acc0d2..4d5a4f6d4f 100644 --- a/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc +++ b/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc @@ -1644,7 +1644,14 @@ define pcodeop SYNC; build RTsrc; tmp:$(REGSIZE) = sext(simmed:2) + RTsrc; JXWritePC(tmp); - call [pc]; + goto [pc]; +} + +:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed & rt=0x1f { + build RTsrc; + tmp:$(REGSIZE) = sext(simmed:2) + RTsrc; + JXWritePC(tmp); + return [pc]; } @ifndef COPR_C From 89ecfcc236f0b2752f60039913a1f78b7a7a357b Mon Sep 17 00:00:00 2001 From: veritas501 Date: Wed, 12 May 2021 15:02:15 +0800 Subject: [PATCH 2/2] fix(mips32r6): Optimize inst jic --- .../Processors/MIPS/data/languages/mips32Instructions.sinc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc b/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc index 4d5a4f6d4f..4b32189316 100644 --- a/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc +++ b/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc @@ -1647,10 +1647,9 @@ define pcodeop SYNC; goto [pc]; } -:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed & rt=0x1f { +:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed & immed=0x00 & rt=0x1f { build RTsrc; - tmp:$(REGSIZE) = sext(simmed:2) + RTsrc; - JXWritePC(tmp); + JXWritePC(ra); return [pc]; }