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Merge remote-tracking branch 'origin/GP-6876_ghidorahrex_riscv_w_operands_fix--SQUASHED' into patch

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Ryan Kurtz
2026-07-01 09:47:26 -04:00
parent 0e8ad9072b 43d043e941
commit 24e2a6eb62
8 changed files with 61 additions and 61 deletions
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40
Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc
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@@ -1,10 +1,10 @@
# RV32A Standard Extension # RV32A Standard Extension
# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4) # amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4)
:amoadd.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl :amoadd.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
tmp = tmp + tmprs2; tmp = tmp + tmprs2;
@@ -13,10 +13,10 @@
# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4) # amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4)
:amoand.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl :amoand.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
tmp = tmp & tmprs2; tmp = tmp & tmprs2;
@@ -25,10 +25,10 @@
# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4) # amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4)
:amomax.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl :amomax.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
if (tmprs2 s<= tmp) goto inst_next; if (tmprs2 s<= tmp) goto inst_next;
@@ -37,10 +37,10 @@
# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4) # amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4)
:amomaxu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl :amomaxu.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
if (tmprs2 <= tmp) goto inst_next; if (tmprs2 <= tmp) goto inst_next;
@@ -49,10 +49,10 @@
# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4) # amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4)
:amomin.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl :amomin.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
if (tmprs2 s>= tmp) goto inst_next; if (tmprs2 s>= tmp) goto inst_next;
@@ -61,10 +61,10 @@
# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4) # amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4)
:amominu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl :amominu.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
if (tmprs2 >= tmp) goto inst_next; if (tmprs2 >= tmp) goto inst_next;
@@ -73,10 +73,10 @@
# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4) # amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4)
:amoor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl :amoor.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
tmp = tmp | tmprs2; tmp = tmp | tmprs2;
@@ -85,10 +85,10 @@
# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4) # amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4)
:amoswap.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl :amoswap.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
*[ram]:4 tmprs1 = tmprs2; *[ram]:4 tmprs1 = tmprs2;
@@ -96,10 +96,10 @@
# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4) # amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4)
:amoxor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl :amoxor.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl
{ {
local tmprs1 = rs1; local tmprs1 = rs1;
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmp:4 = *[ram]:4 tmprs1; local tmp:4 = *[ram]:4 tmprs1;
assignW(rd, tmp); assignW(rd, tmp);
tmp = tmp ^ tmprs2; tmp = tmp ^ tmprs2;
@@ -118,9 +118,9 @@
# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4) # sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4)
:sc.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl :sc.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl
{ {
local tmprs2 = rs2W; local tmprs2:$(WXLEN) = rs2:$(WXLEN);
local tmprs1 = rs1; local tmprs1 = rs1;
rd = 1; rd = 1;
if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next; if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next;

20
Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc
View File

@@ -35,18 +35,18 @@
# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0) # fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0)
:fcvt.d.w frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0 :fcvt.d.w frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0
{ {
local tmp:8 = int2float(rs1W); local tmp:8 = int2float(rs1:$(WXLEN));
frd = tmp; frd = tmp;
} }
# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0) # fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0)
:fcvt.d.wu frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1 :fcvt.d.wu frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1
{ {
#ATTN unsigned can be an issue here #ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W); local u32:8 = zext(rs1:$(WXLEN));
local tmp:8 = int2float(u32); local tmp:8 = int2float(u32);
frd = tmp; frd = tmp;
} }
@@ -61,17 +61,19 @@
# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0) # fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0)
:fcvt.w.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0 :fcvt.w.d rd,frs1D,FRM is frs1D & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
{ {
rdW = trunc(frs1D); local tmp:4 = trunc(frs1D);
rd = sext(tmp);
} }
# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0) # fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1 :fcvt.wu.d rd,frs1D,FRM is frs1D & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
{ {
#TODO unsigned local cond = (frs1D s<0);
rdW = trunc(frs1D); local tmp:4 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1D));
rd = sext(tmp); # x[rd] = sext(f32->u32(f[rs1]))
} }

28
Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc
View File

@@ -27,35 +27,37 @@
# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0) # fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0)
:fcvt.s.w frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0 :fcvt.s.w frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
{ {
local tmp:4 = int2float(rs1W); local tmp:4 = int2float(rs1:$(WXLEN));
fassignS(frd, tmp); fassignS(frd, tmp);
} }
# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0) # fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0)
:fcvt.s.wu frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1 :fcvt.s.wu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
{ {
#ATTN unsigned can be an issue here #ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W); local u32:8 = zext(rs1:$(WXLEN));
local tmp:4 = int2float(u32); local tmp:4 = int2float(u32);
fassignS(frd, tmp); fassignS(frd, tmp);
} }
# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0) # fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0)
:fcvt.w.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0 :fcvt.w.s rd,frs1S,FRM is frs1S & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
{ {
rdW = trunc(frs1S); local tmp:4 = trunc(frs1S);
rd = sext(tmp);
} }
# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0) # fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1 :fcvt.wu.s rd,frs1S,FRM is frs1S & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
{ {
#TODO unsigned local cond = (frs1S s<0);
rdW = trunc(frs1S); local tmp:4 = (zext(cond) * 0:4) + (zext(!cond) * trunc(frs1S));
rd = sext(tmp); # x[rd] = sext(f32->u32(f[rs1]))
} }
@@ -153,17 +155,17 @@
# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0) # fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0)
:fmv.w.x frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 :fmv.w.x frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0
{ {
fassignS(frd, rs1W); fassignS(frd, rs1:$(WXLEN));
} }
# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0) # fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0)
:fmv.x.w rdW,frs1S is frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 :fmv.x.w rd,frs1S is frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0
{ {
local tmpreg:4 = &frs1S; local tmpreg:4 = &frs1S;
local tmp:4 = *[register]:4 tmpreg; local tmp:4 = *[register]:4 tmpreg;
rdW = tmp; rd = zext(tmp);
} }

7
Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc
View File

@@ -64,13 +64,16 @@
# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0) # fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0)
:fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0 :fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
{ {
rd = trunc(frs1); local tmp:4 = trunc(frs1S);
rd = sext(tmp);
} }
# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0) # fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0)
:fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1 :fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
{ {
rd = trunc(frs1); local cond = (frs1S s<0);
local tmp:4 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1S));
rdL = sext(tmp);
} }

5
Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc
View File

@@ -28,8 +28,9 @@
# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) # fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0)
:fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3 :fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
{ {
#TODO unsigned local cond = (frs1D s<0);
rdL = trunc(frs1D); local tmp:8 = (zext(cond) * 0:8) + (zext(!cond) * trunc(frs1D));
rdL = tmp;
} }

5
Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc
View File

@@ -10,8 +10,9 @@
# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) # fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0)
:fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3 :fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
{ {
#TODO unsigned local cond = (frs1S s<0);
rdL = trunc(frs1S); local tmp:8 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1S));
rdL = tmp;
} }

8
Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc
View File

@@ -107,15 +107,15 @@
# subw d,s,t 4000003b fe00707f SIMPLE (64, 0) # subw d,s,t 4000003b fe00707f SIMPLE (64, 0)
:subw rd,rs1W,rs2W is rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 :subw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20
{ {
local result = rs1W - rs2W; local result = rs1:$(WXLEN)- rs2:$(WXLEN);
rd = sext(result); rd = sext(result);
} }
# negw d,t 4000003b fe0ff07f ALIAS (64, 0) # negw d,t 4000003b fe0ff07f ALIAS (64, 0)
:negw rd,rs2W is rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 :negw rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
{ {
local tmp = -rs2W; local tmp = -rs2:$(WXLEN);
rd = sext(tmp); rd = sext(tmp);
} }

9
Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
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@@ -617,15 +617,6 @@ rs3: zero is zero & op2731=0 { export 0:$(XLEN); }
rd: r0711 is r0711 { export r0711; } rd: r0711 is r0711 { export r0711; }
rd: zero is r0711=0 & zero { local tmp:$(XLEN) = 0; export tmp; } rd: zero is r0711=0 & zero { local tmp:$(XLEN) = 0; export tmp; }
rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; }
rs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); }
rs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; }
rs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); }
rdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; }
rdW: zero is r0711=0 & zero { local tmp:$(WXLEN) = 0; export tmp; }
#TODO does this need to be in an if/endif #TODO does this need to be in an if/endif
@if ADDRSIZE == "64" @if ADDRSIZE == "64"