mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-28 17:11:11 -09:00
Code Issues Packages Projects Releases Wiki Activity

Add Rockwell 65C02 opcodes.

Browse Source
This commit is contained in:
Alessandro Gatti
2021-07-04 16:30:04 +02:00
parent b91b43100d
commit 2802425d68
2 changed files with 40 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
Ghidra/Processors/6502/data/languages/65c02.slaspec
View File

@@ -1,5 +1,13 @@
@include "6502.slaspec" @include "6502.slaspec"
define token bitopbyte (8)
bitop = (0,7)
action = (7,7)
bitindex = (4,6) dec
optype = (0,3)
;
define token testopbyte (8) define token testopbyte (8)
top = (0, 7) top = (0, 7)
taaa = (5, 7) taaa = (5, 7)
@@ -38,6 +46,20 @@ ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr;
resultFlags(A); resultFlags(A);
} }
:BBR "#"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) == 0;
if (jump) goto REL;
}
:BBS "#"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) != 0;
if (jump) goto REL;
}
:BIT "#"imm8 is op=0x89; imm8 :BIT "#"imm8 is op=0x89; imm8
{ {
local value:1 = imm8; local value:1 = imm8;
@@ -131,6 +153,13 @@ ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr;
resultFlags(Y); resultFlags(Y);
} }
:RMB "#"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value & ~(1 << bitindex);
*:1 ptr = value;
}
:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP :SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP
{ {
local op1 = ZIOP; local op1 = ZIOP;
@@ -140,6 +169,13 @@ ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr;
A = result; A = result;
} }
:SMB "#"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value | (1 << bitindex);
*:1 ptr = value;
}
:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP :STA ZIOP is (cc=2 & aaa=4) ... & ZIOP
{ {
ZIOP = A; ZIOP = A;

4
Ghidra/Processors/6502/data/manuals/65c02.idx
View File

@@ -2,6 +2,8 @@
ADC, 327 ADC, 327
AND, 328 AND, 328
ASL, 329 ASL, 329
BBR, 457
BBS, 458
BCC, 330 BCC, 330
BCS, 331 BCS, 331
BEQ, 332 BEQ, 332
@@ -43,6 +45,7 @@ PLA, 382
PLP, 385 PLP, 385
PLX, 386 PLX, 386
PLY, 387 PLY, 387
RMB, 459
ROL, 389 ROL, 389
ROR, 390 ROR, 390
RTI, 391 RTI, 391
@@ -51,6 +54,7 @@ SBC, 395
SEC, 397 SEC, 397
SED, 398 SED, 398
SEI, 399 SEI, 399
SMB, 460
STA, 401 STA, 401
STX, 403 STX, 403
STY, 404 STY, 404