From 2853f487a86364ef2b24ee012fa8d82584b3adfe Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 21 Aug 2023 15:25:15 +0000 Subject: [PATCH] GP-3211: Code review fixes --- .../pcodetest/c_src/BIOPS_DOUBLE.test | 13 ++ .../pcodetest/c_src/BIOPS_FLOAT.test | 13 -- .../languages/Loongarch32_Instructions.sinc | 193 ++++-------------- .../languages/Loongarch64_Instructions.sinc | 123 ++++++----- .../data/languages/double_Instructions.sinc | 50 ++--- .../data/languages/float_Instructions.sinc | 56 +++-- .../Loongarch/data/languages/ilp32f.cspec | 24 +-- .../Loongarch/data/languages/lasx.sinc | 10 - .../Loongarch/data/languages/lbt.sinc | 10 +- .../Loongarch/data/languages/loongarch.ldefs | 9 +- .../data/languages/loongarch_main.sinc | 25 +-- .../Loongarch/data/languages/lp64f.cspec | 15 ++ .../Loongarch/data/languages/lsx.sinc | 10 - .../data/languages/privileged-32.sinc | 5 +- .../Loongarch64_O0_EmulatorTest.java | 2 +- .../Loongarch64_O3_EmulatorTest.java | 2 +- 16 files changed, 230 insertions(+), 330 deletions(-) diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test index 5738519d20..34bba39353 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test @@ -1,5 +1,18 @@ #include "pcode_test.h" +#ifdef HAS_DOUBLE +TEST f8_compareLogic_Main() +{ + extern f8 f8_compareLogic(f8 lhs, f8 rhs); + ASSERTF8(f8_compareLogic(0x1, 0x1), 21); + ASSERTF8(f8_compareLogic(0x1, 0x2), 21); + ASSERTF8(f8_compareLogic(0x2, 0x1), 22); + ASSERTF8(f8_compareLogic(-0x1, -0x1), 21); + ASSERTF8(f8_compareLogic(-0x1, -0x2), 21); + ASSERTF8(f8_compareLogic(-0x2, -0x1), 24); +} +#endif + /* Comparison operators */ #ifdef HAS_DOUBLE TEST f8_greaterThan_Main() diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test index 20f2e7a4a9..6f638105ce 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test @@ -13,19 +13,6 @@ TEST f4_compareLogic_Main() } #endif -#ifdef HAS_DOUBLE -TEST f8_compareLogic_Main() -{ - extern f8 f8_compareLogic(f8 lhs, f8 rhs); - ASSERTF8(f8_compareLogic(0x1, 0x1), 21); - ASSERTF8(f8_compareLogic(0x1, 0x2), 21); - ASSERTF8(f8_compareLogic(0x2, 0x1), 22); - ASSERTF8(f8_compareLogic(-0x1, -0x1), 21); - ASSERTF8(f8_compareLogic(-0x1, -0x2), 21); - ASSERTF8(f8_compareLogic(-0x2, -0x1), 24); -} -#endif - /* Comparison operators */ #ifdef HAS_FLOAT TEST f4_greaterThan_Main() diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc index 946ef94cc1..be0d205bc2 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc @@ -10,11 +10,7 @@ local add1:4 = RJ32src; local add2:4 = RK32src; local result = add1 + add2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt addi.w mask=0x02800000 [@la32, @primary, @qemu] @@ -23,11 +19,7 @@ local add1:4 = RJ32src; local add2:4 = simm10_12; local result = add1 + add2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -35,11 +27,7 @@ #0x00040000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] :alsl.w RD, RJ32src, RK32src, alsl_shift is op17_31=0x2 & RD & RJ32src & RK32src & alsl_shift { local result:4 = (RJ32src << alsl_shift) + RK32src; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -122,25 +110,23 @@ #la-base-32.txt lu12i.w mask=0x14000000 [@la32, @primary, @qemu] #0x14000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] :lu12i.w RD, simm12i is op25_31=0xa & RD & simm12i { -@ifdef LA64 RD = sext(simm12i); -@else - RD = simm12i; -@endif } #la-base-32.txt maskeqz mask=0x00130000 [@la32, @qemu] #0x00130000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :maskeqz RD, RJsrc, RKsrc is op15_31=0x26 & RD & RJsrc & RKsrc { - RD = (zext(RKsrc == 0) * 0) + (zext(RKsrc != 0) * RJsrc); + local test = (RKsrc == 0); + RD = (zext(test) * 0) + (zext(!test) * RJsrc); } #la-base-32.txt masknez mask=0x00138000 [@la32, @qemu] #0x00138000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :masknez RD, RJsrc, RKsrc is op15_31=0x27 & RD & RJsrc & RKsrc { - RD = (zext(RKsrc != 0) * 0) + (zext(RKsrc == 0) * RJsrc); + local test = (RKsrc != 0); + RD = (zext(test) * 0) + (zext(!test) * RJsrc); } @@ -275,11 +261,9 @@ local tmp1:4 = RJ32src s>> shift; local tmp2:4 = RJ32src << (32 - shift); local result = tmp1 + tmp2; -@ifdef LA64 + RD = sext(result); -@else - RD = result; -@endif + } #la-base-32.txt rotri.w mask=0x004c8000 [@la32, @qemu] @@ -289,11 +273,9 @@ local tmp1:4 = RJ32src s>> shift; local tmp2:4 = RJ32src << (32 - shift); local result = tmp1 + tmp2; -@ifdef LA64 + RD = sext(result); -@else - RD = result; -@endif + } @@ -302,11 +284,7 @@ :sll.w RD, RJ32src, RK32src is op15_31=0x2e & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src << shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt slli.w mask=0x00408000 [@la32, @primary, @qemu] @@ -314,11 +292,7 @@ :slli.w RD, RJ32src, imm10_5 is op15_31=0x81 & RD & RJ32src& imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src << shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -352,11 +326,7 @@ :srl.w RD, RJ32src, RK32src is op15_31=0x2f & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src >> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt srli.w mask=0x00448000 [@la32, @primary, @qemu] @@ -364,11 +334,7 @@ :srli.w RD, RJ32src, imm10_5 is op15_31=0x89 & RD & RJ32src & imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src >> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -377,11 +343,7 @@ :sra.w RD, RJ32src, RK32src is op15_31=0x30 & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src s>> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt srai.w mask=0x00488000 [@la32, @primary, @qemu] @@ -389,11 +351,7 @@ :srai.w RD, RJ32src, imm10_5 is op15_31=0x91 & RD & RJ32src & imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src s>> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -403,11 +361,7 @@ local sub1:4 = RJ32src; local sub2:4 = RK32src; local result = sub1 - sub2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -440,11 +394,7 @@ #0x24000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] :ldptr.w RD, ldstptr_addr is op24_31=0x24 & RD & RJsrc & ldstptr_addr { local data:4 = *[ram]:4 ldstptr_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -473,11 +423,7 @@ #0x28800000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] :ld.w RD, ldst_addr is op22_31=0xa2 & RD & RJsrc & ldst_addr { local data:4 = *[ram]:4 ldst_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -560,11 +506,7 @@ #0x38080000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :ldx.w RD, ldstx_addr is op15_31=0x7010 & RD & ldstx_addr { local data:4 = *[ram]:4 ldstx_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -707,20 +649,19 @@ #la-base-32.txt jirl mask=0x4c000000 [@orig_fmt=DJSk16ps2, @la32, @primary, @qemu] #0x4c000000 0xfc000000 r0:5,r5:5,so10:16<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_16_s0'] -:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & offs16 & RelJ16 { +:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & RelJ16 { RD = inst_next; - local addr:$(ADDRSIZE) = RJsrc + (offs16 << 2); call [RelJ16]; } # alias of jirl zero, ra, 0 -:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & offs16=0 { +:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & simm10_16=0 { local retAddr = RJsrc; return [retAddr]; } # alias of jirl zer, rj, 0 -:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & offs16=0 { +:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & simm10_16=0 { local retAddr = RJsrc; return [retAddr]; } @@ -733,20 +674,14 @@ #la-atomics-32.txt ll.w mask=0x20000000 [@orig_fmt=DJSk14ps2, @la32, @primary] #0x20000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :ll.w RD, ldstptr_addr is op24_31=0x20 & RD & ldstptr_addr { local data:4 = *[ram]:4 ldstptr_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } #la-atomics-32.txt sc.w mask=0x21000000 [@orig_fmt=DJSk14ps2, @la32, @primary] #0x21000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :sc.w RD, ldstptr_addr is op24_31=0x21 & RD & ldstptr_addr { *[ram]:4 ldstptr_addr = RD:4; } @@ -800,18 +735,22 @@ #la-atomics-32.txt ammax.w mask=0x38650000 [@orig_fmt=DKJ] #0x38650000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.w RD, RJsrc, RK32src is op15_31=0x70ca & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-32.txt ammin.w mask=0x38660000 [@orig_fmt=DKJ] #0x38660000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.w RD, RJsrc, RK32src is op15_31=0x70cc & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -869,9 +808,11 @@ #0x386e0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.w RD, RJsrc, RK32src is op15_31=0x70dc & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -879,9 +820,11 @@ #0x386f0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.w RD, RJsrc, RK32src is op15_31=0x70de & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -911,11 +854,7 @@ :cto.w RD, RJ32src is op10_31=0x6 & RD & RJ32src { local tmp:4 = 0; tzcount32(~RJ32src, tmp); -@ifdef LA64 RD = zext(tmp); -@else - RD = tmp; -@endif } #la-bitops-32.txt ctz.w mask=0x00001c00 [@la32, @qemu] @@ -923,11 +862,7 @@ :ctz.w RD, RJ32src is op10_31=0x7 & RD & RJ32src { local tmp:4 = 0; tzcount32(RJ32src, tmp); -@ifdef LA64 RD = zext(tmp); -@else - RD = tmp; -@endif } @@ -936,11 +871,7 @@ :revb.2h RD, RJ32src is op10_31=0xc & RD & RJ32src { tmp0:4 = (zext(RJ32src[0,8]) << 8) + zext(RJ32src[8,8]); tmp1:4 = (zext(RJ32src[16,8]) << 8) + zext(RJ32src[24,8]); -@ifdef LA64 RD = sext((tmp1 << 16) + tmp0); -@else - RD = (tmp1 << 16) + tmp0; -@endif } @@ -949,11 +880,7 @@ :bitrev.4b RD, RJ32src is op10_31=0x12 & RD & RJ32src { local v:4 = 0; byterev32(RJ32src, v); -@ifdef LA64 RD = sext(v); -@else - RD = v; -@endif } @@ -962,11 +889,7 @@ :bitrev.w RD, RJ32src is op10_31=0x14 & RD & RJ32src { local v:4 = 0; bitrev32(RJ32src, v); -@ifdef LA64 RD = sext(v); -@else - RD = v; -@endif } @@ -977,11 +900,7 @@ local mask:4 = (1 << bitstop) - 1; local tmp_hi:4 = RK32src & ~mask; local tmp_lo:4 = (RJ32src & (mask << (32-bitstop)) >> (32-bitstop)); -@ifdef LA64 RD = sext(tmp_hi + tmp_lo); -@else - RD = tmp_hi + tmp_lo; -@endif } define pcodeop crc.w.b.w; @@ -1046,11 +965,7 @@ define pcodeop bstrins.w; local len:1 = msb + 1 - lsb; local mask:4 = (1 << len) - 1; local repl:4 = (RJ32src & (mask << lsb)) >> lsb; -@ifdef LA64 RD = sext((RD32 & (~mask)) | repl); -@else - RD = (RD & (~mask)) | repl; -@endif } @@ -1062,11 +977,7 @@ define pcodeop bstrins.w; local len:1 = msb + 1 - lsb; local mask:4 = (1 << len) - 1; local repl:4 = (RJ32src & (mask << lsb)) >> lsb; -@ifdef LA64 RD = sext(repl); -@else - RD = repl; -@endif } @@ -1078,17 +989,15 @@ define pcodeop bstrins.w; #la-bound.txt asrtle mask=0x00010000 [@orig_name=asrtle.d] #0x00010000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] :asrtle.d RJsrc, RKsrc is op15_31=0x2 & op0_4=0x0 & RJsrc & RKsrc { - if (RJsrc <= RKsrc) goto ; + if (RJsrc <= RKsrc) goto inst_next; addr_bound_exception(RJsrc, RKsrc); - } #la-bound.txt asrtgt mask=0x00018000 [@orig_name=asrtgt.d] #0x00018000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] :asrtgt.d RJsrc, RKsrc is op15_31=0x3 & op0_4=0x0 & RJsrc & RKsrc { - if (RJsrc > RKsrc) goto ; + if (RJsrc > RKsrc) goto inst_next; addr_bound_exception(RJsrc, RKsrc); - } @@ -1098,10 +1007,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } #la-bound.txt ldgt.h mask=0x38788000 @@ -1110,10 +1018,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:2 vaddr); - } #la-bound.txt ldgt.w mask=0x38790000 @@ -1122,10 +1029,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:4 vaddr); - } @@ -1135,10 +1041,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } #la-bound.txt ldle.h mask=0x387a8000 @@ -1147,10 +1052,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:2 vaddr); - } #la-bound.txt ldle.w mask=0x387b0000 @@ -1159,10 +1063,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:4 vaddr); - } @@ -1172,10 +1075,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(vaddr, RKsrc); - goto ; + goto inst_next; *[ram]:1 RJsrc = RDsrc:1; - } #la-bound.txt stgt.h mask=0x387c8000 @@ -1184,10 +1086,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(vaddr, RKsrc); - goto ; + goto inst_next; *[ram]:2 vaddr = RDsrc:2; - } #la-bound.txt stgt.w mask=0x387d0000 @@ -1196,10 +1097,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = RDsrc:4; - } #la-bound.txt stle.b mask=0x387e0000 @@ -1208,10 +1108,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:1 vaddr = RDsrc:1; - } #la-bound.txt stle.h mask=0x387e8000 @@ -1220,10 +1119,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:2 vaddr = RDsrc:2; - } #la-bound.txt stle.w mask=0x387f0000 @@ -1232,10 +1130,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = RDsrc:4; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc index 15859141ed..b3f142e728 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc @@ -31,11 +31,7 @@ #0x00060000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] :alsl.wu RD, RJ32src, RK32src, alsl_shift is op17_31=0x3 & RD & RJ32src & RK32src & alsl_shift { local result:4 = (RJ32src << alsl_shift) + RK32src; -@ifdef LA64 RD = zext(result); -@else - RD = result; -@endif } @@ -204,16 +200,15 @@ #la-base-64.txt cu52i.d mask=0x03000000 [@orig_name=lu52i.d, @qemu] #0x03000000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] -:lu52i.d RD, RJsrc, simm10_12 is op22_31=0xc & RD & RJsrc & simm10_12 { - local simm52i:$(REGSIZE) = (simm10_12 << 52) + (RJsrc & 0xfffffffffffff); - RD = simm52i; +:lu52i.d RD, RJsrc, simm52i is op22_31=0xc & RD & RJsrc & simm52i { + RD = simm52i + (RJsrc & 0xfffffffffffff); } #la-base-64.txt cu32i.d mask=0x16000000 [@orig_name=lu32i.d, @qemu] #0x16000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] -:lu32i.d RD, simm5_20 is op25_31=0xb & RD & RD32 & simm5_20 { - RD = (simm5_20 << 32) + zext(RD32); +:lu32i.d RD, simm32i is op25_31=0xb & RD & RD32 & simm32i { + RD = simm32i + zext(RD32); } @@ -280,7 +275,6 @@ #la-atomics-64.txt ll.d mask=0x22000000 [@orig_fmt=DJSk14ps2] #0x22000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :ll.d RD, ldstptr_addr is op24_31=0x22 & RD & ldstptr_addr { RD = *[ram]:8 ldstptr_addr; } @@ -288,7 +282,6 @@ #la-atomics-64.txt sc.d mask=0x23000000 [@orig_fmt=DJSk14ps2] #0x23000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :sc.d RD, ldstptr_addr is op24_31=0x23 & RD & ldstptr_addr { *[ram]:8 ldstptr_addr = RD; } @@ -342,54 +335,66 @@ #la-atomics-64.txt ammax.d mask=0x38658000 [@orig_fmt=DKJ] #0x38658000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.d RD, RJsrc, RKsrc is op15_31=0x70cb & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.d mask=0x38668000 [@orig_fmt=DKJ] #0x38668000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.d RD, RJsrc, RKsrc is op15_31=0x70cd & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammax.wu mask=0x38670000 [@orig_fmt=DKJ] #0x38670000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.wu RD, RJsrc, RK32src is op15_31=0x70ce & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammax.du mask=0x38678000 [@orig_fmt=DKJ] #0x38678000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.du RD, RJsrc, RKsrc is op15_31=0x70cf & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.wu mask=0x38680000 [@orig_fmt=DKJ] #0x38680000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.wu RD, RJsrc, RK32src is op15_31=0x70d0 & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.du mask=0x38688000 [@orig_fmt=DKJ] #0x38688000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.du RD, RJsrc, RKsrc is op15_31=0x70d1 & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -447,9 +452,11 @@ #0x386e8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.d RD, RJsrc, RKsrc is op15_31=0x70dd & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -457,9 +464,11 @@ #0x386f8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.d RD, RJsrc, RKsrc is op15_31=0x70df & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -467,9 +476,11 @@ #0x38700000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.wu RD, RJsrc, RK32src is op15_31=0x70e0 & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -477,9 +488,11 @@ #0x38708000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.du RD, RJsrc, RKsrc is op15_31=0x70e1 & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -487,9 +500,11 @@ #0x38710000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.wu RD, RJsrc, RK32src is op15_31=0x70e2 & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -497,9 +512,11 @@ #0x38718000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.du RD, RJsrc, RKsrc is op15_31=0x70e3 & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -683,10 +700,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:8 vaddr); - } #la-bound-64.txt ldle.d mask=0x387b8000 @@ -695,10 +711,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } @@ -708,10 +723,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = RDsrc:8; - } #la-bound-64.txt stle.d mask=0x387f8000 @@ -720,10 +734,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = RDsrc:8; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc index adc639eb1e..019c425c73 100644 --- a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc @@ -34,7 +34,8 @@ :fmax.d drD, drJ, drK is op15_31=0x212 & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); + local test = jval f>= kval; + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -43,7 +44,8 @@ :fmin.d drD, drJ, drK is op15_31=0x216 & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); + local test = jval f<= kval; + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -52,7 +54,8 @@ :fmaxa.d drD, drJ, drK is op15_31=0x21a & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); + local test = (abs(jval) f>= abs(kval)); + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -61,7 +64,8 @@ :fmina.d drD, drJ, drK is op15_31=0x21e & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); + local test = (abs(jval) f<= abs(kval)); + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -279,20 +283,20 @@ drD = f- ((drJ f* drK) f- drA); } -dSNaN: "c" is cond_s = 0 { } -dSNaN: "s" is cond_s = 1 { } +dSNaN: "c" is ccf_s = 0 { } +dSNaN: "s" is ccf_s = 1 { } -dcond: dSNaN^"af" is cond=0x0 & dSNaN { DCMPR = 0; } -dcond: dSNaN^"lt" is cond=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; } -dcond: dSNaN^"eq" is cond=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; } -dcond: dSNaN^"le" is cond=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; } -dcond: dSNaN^"un" is cond=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); } -dcond: dSNaN^"ult" is cond=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); } -dcond: dSNaN^"ueq" is cond=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); } -dcond: dSNaN^"ule" is cond=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); } -dcond: dSNaN^"ne" is cond=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; } -dcond: dSNaN^"or" is cond=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); } -dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); } +dcond: dSNaN^"af" is ccf=0x0 & dSNaN { DCMPR = 0; } +dcond: dSNaN^"lt" is ccf=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; } +dcond: dSNaN^"eq" is ccf=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; } +dcond: dSNaN^"le" is ccf=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; } +dcond: dSNaN^"un" is ccf=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); } +dcond: dSNaN^"ult" is ccf=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); } +dcond: dSNaN^"ueq" is ccf=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); } +dcond: dSNaN^"ule" is ccf=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); } +dcond: dSNaN^"ne" is ccf=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; } +dcond: dSNaN^"or" is ccf=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); } +dcond: dSNaN^"une" is ccf=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); } #la-fp-d.txt fcmp.caf.d mask=0x0c200000 #0x0c200000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] @@ -337,10 +341,9 @@ dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; drD = sext(*[ram]:8 vaddr); - } @@ -350,10 +353,9 @@ dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; drD = sext(*[ram]:8 vaddr); - } define pcodeop fstgt.d; @@ -364,10 +366,9 @@ define pcodeop fstgt.d; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = drD; - } define pcodeop fstle.d; @@ -378,10 +379,9 @@ define pcodeop fstle.d; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = drD; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc index 72662a462a..c187c65257 100644 --- a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc @@ -102,7 +102,6 @@ define pcodeop uncertain_fcsr; #la-fp.txt bcnez mask=0x48000100 [@orig_fmt=CjSd5k16ps2] #0x48000100 0xfc000300 c5:3,sb0:5|10:16<<2 ['fcc5_3_s0', 'sbranch0_0_s2'] -#TODO: FIX RELATIVE OFFSET :bcnez fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=1 & Rel21 { if(fccJ != 0) goto Rel21; } @@ -168,7 +167,8 @@ define pcodeop uncertain_fcsr; :fmax.s frD, frJ, frK is op15_31=0x211 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); + local test = (jval f>= kval); + frD = (zext(test) * jval) + (zext(!test) * kval); } #la-fp-s.txt fmin.s mask=0x010a8000 @@ -176,7 +176,8 @@ define pcodeop uncertain_fcsr; :fmin.s frD, frJ, frK is op15_31=0x215 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); + local test = (jval f<= kval); + frD = (zext(test) * jval) + (zext(!test) * kval); } @@ -185,7 +186,8 @@ define pcodeop uncertain_fcsr; :fmaxa.s frD, frJ, frK is op15_31=0x219 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); + local test = (abs(jval) f>= abs(kval)); + frD = (zext(test) * jval) + (zext(!test) * kval); } #la-fp-s.txt fmina.s mask=0x010e8000 @@ -193,7 +195,8 @@ define pcodeop uncertain_fcsr; :fmina.s frD, frJ, frK is op15_31=0x21d & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); + local test = (abs(jval) f<= abs(kval)); + frD = (zext(test) * jval) + (zext(!test) * kval); } @@ -371,9 +374,8 @@ define pcodeop uncertain_fcsr; #la-fp-s.txt ffint.s.l mask=0x011d1800 #0x011d1800 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] -:ffint.s.l frD,frJ is op10_31=0x4746 & frD & frJ { - local val:8 = int2float(frJ); - frD = frJ(0); +:ffint.s.l frD, drD is op10_31=0x4746 & frD & drD { + frD = int2float(drD); } @@ -411,20 +413,20 @@ define pcodeop uncertain_fcsr; *[ram]:4 ldstx_addr = frD; } -SNaN: "c" is cond_s = 0 { } -SNaN: "s" is cond_s = 1 { } +SNaN: "c" is ccf_s = 0 { } +SNaN: "s" is ccf_s = 1 { } -fcond: SNaN^"af" is cond=0x0 & SNaN { FCMPR = 0; } -fcond: SNaN^"lt" is cond=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; } -fcond: SNaN^"eq" is cond=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; } -fcond: SNaN^"le" is cond=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; } -fcond: SNaN^"un" is cond=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); } -fcond: SNaN^"ult" is cond=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); } -fcond: SNaN^"ueq" is cond=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); } -fcond: SNaN^"ule" is cond=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); } -fcond: SNaN^"ne" is cond=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; } -fcond: SNaN^"or" is cond=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); } -fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); } +fcond: SNaN^"af" is ccf=0x0 & SNaN { FCMPR = 0; } +fcond: SNaN^"lt" is ccf=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; } +fcond: SNaN^"eq" is ccf=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; } +fcond: SNaN^"le" is ccf=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; } +fcond: SNaN^"un" is ccf=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); } +fcond: SNaN^"ult" is ccf=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); } +fcond: SNaN^"ueq" is ccf=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); } +fcond: SNaN^"ule" is ccf=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); } +fcond: SNaN^"ne" is ccf=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; } +fcond: SNaN^"or" is ccf=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); } +fcond: SNaN^"une" is ccf=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); } #la-fp-s.txt fcmp.caf.s mask=0x0c100000 #0x0c100000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] @@ -442,10 +444,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; frD = sext(*[ram]:4 vaddr); - } @@ -455,10 +456,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; frD = sext(*[ram]:4 vaddr); - } @@ -468,10 +468,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = frD; - } @@ -481,9 +480,8 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = frD; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec index fba9d74aba..a643556d93 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec @@ -29,18 +29,6 @@ - - - - - - - - - - - - @@ -65,6 +53,18 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lasx.sinc b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc index 0ae4624457..9e79e3316c 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lasx.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc @@ -434,7 +434,6 @@ define pcodeop xvld; #lasx.txt xvld mask=0x2c800000 #0x2c800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvld xrD, RJsrc,simm10_12 is op22_31=0xb2 & xrD & RJsrc & simm10_12 { xrD = xvld(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -443,7 +442,6 @@ define pcodeop xvst; #lasx.txt xvst mask=0x2cc00000 #0x2cc00000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvst xrD, RJsrc,simm10_12 is op22_31=0xb3 & xrD & RJsrc & simm10_12 { xrD = xvst(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -452,7 +450,6 @@ define pcodeop xvldrepl.d; #lasx.txt xvldrepl.d mask=0x32100000 [@orig_fmt=XdJSk9ps3] #0x32100000 0xfff80000 x0:5, r5:5,so10:9<<3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.d xrD, RJsrc,simm10_9 is op19_31=0x642 & xrD & RJsrc & simm10_9 { xrD = xvldrepl.d(xrD, RJsrc, simm10_9:$(REGSIZE)); } @@ -461,7 +458,6 @@ define pcodeop xvldrepl.w; #lasx.txt xvldrepl.w mask=0x32200000 [@orig_fmt=XdJSk10ps2] #0x32200000 0xfff00000 x0:5, r5:5,so10:10<<2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.w xrD, RJsrc,simm10_10 is op20_31=0x322 & xrD & RJsrc & simm10_10 { xrD = xvldrepl.w(xrD, RJsrc, simm10_10:$(REGSIZE)); } @@ -470,7 +466,6 @@ define pcodeop xvldrepl.h; #lasx.txt xvldrepl.h mask=0x32400000 [@orig_fmt=XdJSk11ps1] #0x32400000 0xffe00000 x0:5, r5:5,so10:11<<1 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.h xrD, RJsrc,simm10_11 is op21_31=0x192 & xrD & RJsrc & simm10_11 { xrD = xvldrepl.h(xrD, RJsrc, simm10_11:$(REGSIZE)); } @@ -479,7 +474,6 @@ define pcodeop xvldrepl.b; #lasx.txt xvldrepl.b mask=0x32800000 #0x32800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.b xrD, RJsrc,simm10_12 is op22_31=0xca & xrD & RJsrc & simm10_12 { xrD = xvldrepl.b(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -488,7 +482,6 @@ define pcodeop xvstelm.d; #lasx.txt xvstelm.d mask=0x33100000 [@orig_fmt=XdJSk8ps3Un2] #0x33100000 0xfff00000 x0:5, r5:5,so10:8<<3,u18:2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.d xrD, RJsrc,simm10_8, imm18_2 is op20_31=0x331 & xrD & RJsrc & simm10_8 & imm18_2 { xrD = xvstelm.d(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); } @@ -497,7 +490,6 @@ define pcodeop xvstelm.w; #lasx.txt xvstelm.w mask=0x33200000 [@orig_fmt=XdJSk8ps2Un3] #0x33200000 0xffe00000 x0:5, r5:5,so10:8<<2,u18:3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.w xrD, RJsrc,simm10_8, imm18_3 is op21_31=0x199 & xrD & RJsrc & simm10_8 & imm18_3 { xrD = xvstelm.w(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); } @@ -506,7 +498,6 @@ define pcodeop xvstelm.h; #lasx.txt xvstelm.h mask=0x33400000 [@orig_fmt=XdJSk8ps1Un4] #0x33400000 0xffc00000 x0:5, r5:5,so10:8<<1,u18:4 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.h xrD, RJsrc,simm10_8, imm18_4 is op22_31=0xcd & xrD & RJsrc & simm10_8 & imm18_4 { xrD = xvstelm.h(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); } @@ -515,7 +506,6 @@ define pcodeop xvstelm.b; #lasx.txt xvstelm.b mask=0x33800000 #0x33800000 0xff800000 x0:5, r5:5,so10:8,u18:5 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_5_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.b xrD, RJsrc,simm10_8, imm18_5 is op23_31=0x67 & xrD & RJsrc & simm10_8 & imm18_5 { xrD = xvstelm.b(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_5:$(REGSIZE)); } diff --git a/Ghidra/Processors/Loongarch/data/languages/lbt.sinc b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc index 1e0ae9b313..81d4b57c64 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lbt.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc @@ -1330,7 +1330,6 @@ define pcodeop ldl.w; #lbt.txt ldl.w mask=0x2e000000 [@lbt] #0x2e000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldl.w RD, RJ, simm10_12 is op22_31=0xb8 & RD & RJ & simm10_12 { RD = ldl.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1339,7 +1338,6 @@ define pcodeop ldr.w; #lbt.txt ldr.w mask=0x2e400000 [@lbt] #0x2e400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldr.w RD, RJ, simm10_12 is op22_31=0xb9 & RD & RJ & simm10_12 { RD = ldr.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1348,7 +1346,6 @@ define pcodeop ldl.d; #lbt.txt ldl.d mask=0x2e800000 [@lbt] #0x2e800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldl.d RD, RJ, simm10_12 is op22_31=0xba & RD & RJ & simm10_12 { RD = ldl.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1357,7 +1354,6 @@ define pcodeop ldr.d; #lbt.txt ldr.d mask=0x2ec00000 [@lbt] #0x2ec00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldr.d RD, RJ, simm10_12 is op22_31=0xbb & RD & RJ & simm10_12 { RD = ldr.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1366,7 +1362,6 @@ define pcodeop stl.w; #lbt.txt stl.w mask=0x2f000000 [@lbt] #0x2f000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :stl.w RD, RJ, simm10_12 is op22_31=0xbc & RD & RJ & simm10_12 { RD = stl.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1375,7 +1370,6 @@ define pcodeop str.w; #lbt.txt str.w mask=0x2f400000 [@lbt] #0x2f400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :str.w RD, RJ, simm10_12 is op22_31=0xbd & RD & RJ & simm10_12 { RD = str.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1384,7 +1378,6 @@ define pcodeop stl.d; #lbt.txt stl.d mask=0x2f800000 [@lbt] #0x2f800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :stl.d RD, RJ, simm10_12 is op22_31=0xbe & RD & RJ & simm10_12 { RD = stl.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1393,7 +1386,6 @@ define pcodeop str.d; #lbt.txt str.d mask=0x2fc00000 [@lbt] #0x2fc00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :str.d RD, RJ, simm10_12 is op22_31=0xbf & RD & RJ & simm10_12 { RD = str.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1410,7 +1402,7 @@ define pcodeop jiscr1; #lbt.txt jiscr1 mask=0x48000300 [@lbt, @orig_fmt=Sd5k16ps2] #0x48000300 0xfc0003e0 s0:5|10:16<<2 ['simm0_0_s2'] -:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & off16 & Rel26 { +:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & Rel26 { jiscr1(Rel26); } diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs index 656cf52644..07cca957f8 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs @@ -10,7 +10,7 @@ processorspec="loongarch32.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:32:ilp32f"> - Loongson Architecture + Loongson 3 32-bit with 32-bit FP @@ -24,7 +24,7 @@ processorspec="loongarch32.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:32:ilp32d"> - Loongson Architecture + Loongson 3 32-bit with 64-bit FP @@ -39,8 +39,9 @@ processorspec="loongarch64.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:64:lp64d"> - Loongson Architecture + Loongson 3 64-bit with 64-bit FP + - Loongson Architecture + Loongson 3 64-bit with 64-bit FP diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc index e7991ef90f..64c6f49911 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -1,7 +1,7 @@ define endian=little; -define alignment=1; +define alignment=4; define space ram type=ram_space size=$(REGSIZE) default; define space register type=register_space size=4; @@ -224,8 +224,8 @@ define token instr(32) op0_4 = ( 0, 4) op0_31 = ( 0,31) - cond = (16,19) - cond_s = (15,15) + ccf = (16,19) + ccf_s = (15,15) simm5_20 = ( 5,24) signed simm5_13 = ( 5,17) signed @@ -233,8 +233,7 @@ define token instr(32) simm10_8 = (10,17) signed simm10_5 = (10,14) signed simm10_14 = (10,23) signed - offs16 = (10,25) signed - off16 = (10,25) + simm10_16 = (10,25) signed simm10_12 = (10,21) signed simm10_11 = (10,20) signed simm10_10 = (10,19) signed @@ -295,6 +294,7 @@ define token instr(32) imm10_4 = (10,13) imm10_3 = (10,12) imm10_2 = (10,11) + imm10_16 = (10,25) imm10_14 = (10,23) imm10_12 = (10,21) imm10_1 = (10,10) @@ -431,7 +431,7 @@ FRK: frK is frK { export frK; } @endif # Immediate operand sub-constructors -addu16_imm: val is offs16 [val = offs16 << 16;] { export *[const]:$(REGSIZE) val; } +addu16_imm: val is simm10_16 [val = simm10_16 << 16;] { export *[const]:$(REGSIZE) val; } alsl_shift: sa2 is imm15_2 [sa2 = imm15_2 + 1;] { export *[const]:1 sa2; } @@ -446,14 +446,15 @@ pcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { expor pcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } pcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; } -Rel16: reloc is offs16 [ reloc = inst_start + (offs16 << 2); ] { export *:$(ADDRSIZE) reloc; } -Rel21: reloc is off16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + off16) << 2); ] { export *:$(ADDRSIZE) reloc; } -Rel26: reloc is off16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | off16) << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel21: reloc is imm10_16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel26: reloc is imm10_16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } -RelJ16: RJsrc, offs16 is RJsrc & offs16 { local tmp:$(ADDRSIZE) = RJsrc + (offs16 << 2); export tmp; } - -simm12i: immed is simm5_20 [immed = simm5_20 << 12;] { export *[const]:$(REGSIZE) immed; } +RelJ16: RJsrc, simm10_16 is RJsrc & simm10_16 { local tmp:$(ADDRSIZE) = RJsrc + (simm10_16 << 2); export tmp; } +simm12i: immed is simm5_20 [immed = simm5_20 << 12; ] { export *[const]:$(REGSIZE) immed; } +simm32i: immed is simm5_20 [immed = simm5_20 << 32; ] { export *[const]:$(REGSIZE) immed; } +simm52i: immed is simm10_12 [immed = simm10_12 << 52; ] { export *[const]:$(REGSIZE) immed; } # general pcodeops define pcodeop break; diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec index d5c1de2c9a..60bc475dbd 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec @@ -51,6 +51,21 @@ + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lsx.sinc b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc index af1259713f..936d63a24b 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lsx.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc @@ -434,7 +434,6 @@ define pcodeop vld; #lsx.txt vld mask=0x2c000000 #0x2c000000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vld vrD, RJsrc, simm10_12 is op22_31=0xb0 & vrD & RJsrc & simm10_12 { vrD = vld(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -443,7 +442,6 @@ define pcodeop vst; #lsx.txt vst mask=0x2c400000 #0x2c400000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vst vrD, RJsrc, simm10_12 is op22_31=0xb1 & vrD & RJsrc & simm10_12 { vrD = vst(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -452,7 +450,6 @@ define pcodeop vldrepl.d; #lsx.txt vldrepl.d mask=0x30100000 [@orig_fmt=VdJSk9ps3] #0x30100000 0xfff80000 v0:5, r5:5, so10:9<<3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.d vrD, RJsrc, simm10_9 is op19_31=0x602 & vrD & RJsrc & simm10_9 { vrD = vldrepl.d(vrD, RJsrc, simm10_9:$(REGSIZE)); } @@ -461,7 +458,6 @@ define pcodeop vldrepl.w; #lsx.txt vldrepl.w mask=0x30200000 [@orig_fmt=VdJSk10ps2] #0x30200000 0xfff00000 v0:5, r5:5, so10:10<<2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.w vrD, RJsrc, simm10_10 is op20_31=0x302 & vrD & RJsrc & simm10_10 { vrD = vldrepl.w(vrD, RJsrc, simm10_10:$(REGSIZE)); } @@ -470,7 +466,6 @@ define pcodeop vldrepl.h; #lsx.txt vldrepl.h mask=0x30400000 [@orig_fmt=VdJSk11ps1] #0x30400000 0xffe00000 v0:5, r5:5, so10:11<<1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.h vrD, RJsrc, simm10_11 is op21_31=0x182 & vrD & RJsrc & simm10_11 { vrD = vldrepl.h(vrD, RJsrc, simm10_11:$(REGSIZE)); } @@ -479,7 +474,6 @@ define pcodeop vldrepl.b; #lsx.txt vldrepl.b mask=0x30800000 #0x30800000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.b vrD, RJsrc, simm10_12 is op22_31=0xc2 & vrD & RJsrc & simm10_12 { vrD = vldrepl.b(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -488,7 +482,6 @@ define pcodeop vstelm.d; #lsx.txt vstelm.d mask=0x31100000 [@orig_fmt=VdJSk8ps3Un1] #0x31100000 0xfff80000 v0:5, r5:5, so10:8<<3,u18:1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_1_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.d vrD, RJsrc, simm10_8, imm18_1 is op19_31=0x622 & vrD & RJsrc & simm10_8 & imm18_1 { vrD = vstelm.d(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_1:$(REGSIZE)); } @@ -497,7 +490,6 @@ define pcodeop vstelm.w; #lsx.txt vstelm.w mask=0x31200000 [@orig_fmt=VdJSk8ps2Un2] #0x31200000 0xfff00000 v0:5, r5:5, so10:8<<2,u18:2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.w vrD, RJsrc, simm10_8, imm18_2 is op20_31=0x312 & vrD & RJsrc & simm10_8 & imm18_2 { vrD = vstelm.w(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); } @@ -506,7 +498,6 @@ define pcodeop vstelm.h; #lsx.txt vstelm.h mask=0x31400000 [@orig_fmt=VdJSk8ps1Un3] #0x31400000 0xffe00000 v0:5, r5:5, so10:8<<1,u18:3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.h vrD, RJsrc, simm10_8, imm18_3 is op21_31=0x18a & vrD & RJsrc & simm10_8 & imm18_3 { vrD = vstelm.h(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); } @@ -515,7 +506,6 @@ define pcodeop vstelm.b; #lsx.txt vstelm.b mask=0x31800000 #0x31800000 0xffc00000 v0:5, r5:5, so10:8,u18:4 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.b vrD, RJsrc, simm10_8, imm18_4 is op22_31=0xc6 & vrD & RJsrc & simm10_8 & imm18_4 { vrD = vstelm.b(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); } diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc index 463f177c92..582bd27843 100644 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc @@ -1,6 +1,9 @@ #la-privileged-32.txt csrxchg mask=0x04000000 [@primary] #0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] -csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] {local tmp:$(REGSIZE) = csr; export *[register]:$(REGSIZE) tmp; } +csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { + local tmp:$(REGSIZE) = csr; + export *[register]:$(REGSIZE) tmp; +} :csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { local csrval:$(REGSIZE) = csr; diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java index f4049951e6..bc24bf5010 100644 --- a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java @@ -20,7 +20,7 @@ import junit.framework.Test; public class Loongarch64_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { - private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64d"; private static final String COMPILER_SPEC_ID = "default"; private static final String[] REG_DUMP_SET = new String[] {}; diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java index 81cbaab6b1..bcc6063d84 100644 --- a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java @@ -20,7 +20,7 @@ import junit.framework.Test; public class Loongarch64_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { - private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64d"; private static final String COMPILER_SPEC_ID = "default"; private static final String[] REG_DUMP_SET = new String[] {};