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fix: incorrect sleigh in e_stmvsprw for PPC VLE

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William Tan
2023-01-10 16:55:41 -05:00
parent 58ccc22076
commit 2964e171ea
1 changed files with 8 additions and 8 deletions
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16
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
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@@ -400,14 +400,14 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
#TODO SEE TODO in e_ldmvsprw
# storeReg(CR);
local tmpCR:4 = 0;
tmpCR = tmpCR | zext((cr0 & 0xf) << 0);
tmpCR = tmpCR | zext((cr1 & 0xf) << 4);
tmpCR = tmpCR | zext((cr2 & 0xf) << 8);
tmpCR = tmpCR | zext((cr3 & 0xf) << 12);
tmpCR = tmpCR | zext((cr4 & 0xf) << 16);
tmpCR = tmpCR | zext((cr5 & 0xf) << 20);
tmpCR = tmpCR | zext((cr6 & 0xf) << 24);
tmpCR = tmpCR | zext((cr7 & 0xf) << 28);
tmpCR = tmpCR | (zext(cr0 & 0xf) << 0);
tmpCR = tmpCR | (zext(cr1 & 0xf) << 4);
tmpCR = tmpCR | (zext(cr2 & 0xf) << 8);
tmpCR = tmpCR | (zext(cr3 & 0xf) << 12);
tmpCR = tmpCR | (zext(cr4 & 0xf) << 16);
tmpCR = tmpCR | (zext(cr5 & 0xf) << 20);
tmpCR = tmpCR | (zext(cr6 & 0xf) << 24);
tmpCR = tmpCR | (zext(cr7 & 0xf) << 28);
*:4 tea = tmpCR;
tea = tea + 4;
storeReg(LR);