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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz
2026-02-09 11:47:31 -05:00
parent 7525f3c4be 2b20282f44
commit 2995d8f687
2 changed files with 15 additions and 12 deletions
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14
Ghidra/Processors/8051/data/languages/80251.sinc
View File

@@ -15,6 +15,7 @@ define token srcDestByte (8)
drk03 = (0,3) drk03 = (0,3)
# constraint bits # constraint bits
d7 = (7,7) d7 = (7,7)
d67 = (6,7)
d57 = (5,7) d57 = (5,7)
d47 = (4,7) d47 = (4,7)
s3 = (3,3) s3 = (3,3)
@@ -36,6 +37,7 @@ define token srcDestByte2 (8)
drk03_ = (0,3) drk03_ = (0,3)
# constraint bits # constraint bits
d7_ = (7,7) d7_ = (7,7)
d67_ = (6,7)
d57_ = (5,7) d57_ = (5,7)
s3_ = (3,3) s3_ = (3,3)
s13_ = (1,3) s13_ = (1,3)
@@ -85,13 +87,13 @@ attach variables [ wrj47_d2 ] [
# NOTE: must use constraints DRK, DRKD and DRKS # NOTE: must use constraints DRK, DRKD and DRKS
attach variables [ drk47 drk03 drk47_ drk03_ ] [ attach variables [ drk47 drk03 drk47_ drk03_ ] [
DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28
DPX SPX _ _ _ _ _ _ _ _ _ _ _ _ DPX SPX
]; ];
@define DRK47 "drk47 & (d7=0 | d57=4)" # constraint for using drk47 @define DRK47 "drk47 & (d7=0 | d67=3)" # constraint for using drk47
@define DRK03 "drk03 & (s3=0 | s13=4)" # constraint for using drk03 @define DRK03 "drk03 & (s3=0 | s23=3)" # constraint for using drk03
@define DRK47_ "drk47_ & (d7_=0 | d57_=4)" # constraint for using drk47_ @define DRK47_ "drk47_ & (d7_=0 | d67_=3)" # constraint for using drk47_
AtWRjb: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; } AtWRjb: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; }
AtWRjw: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; } AtWRjw: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; }
@@ -497,7 +499,7 @@ macro pop24(val) {
# MOVH DRk,#data16 # MOVH DRk,#data16
:MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; $(DRK47) & s03=12; Data16x0 { drk47 = (drk47 & 0xffff0000) | (Data16x0 << 16); } :MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=0xa; $(DRK47) & s03=0xc; Data16x0 { drk47 = (drk47 & 0xffff) | (Data16x0 << 16); }
# MOVS WRj,Rm # MOVS WRj,Rm
:MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); } :MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); }

13
Ghidra/Processors/MIPS/data/languages/mips16.sinc
View File

@@ -517,7 +517,8 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA
<done> <done>
} }
:jal Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16 [ ext_delay=0b10; globalset(inst_next, ext_delay);] { :jal Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16
[ ext_delay=0b10; globalset(inst_next, ext_delay); ] {
ra = inst_next | 0x1; ra = inst_next | 0x1;
delayslot( 1 ); delayslot( 1 );
call Abs26_m16; call Abs26_m16;
@@ -525,7 +526,7 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA
} }
:jalr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx :jalr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx
[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { [ ext_delay=0b01; globalset(inst_next, ext_delay); ] {
JXWritePC(m16_rx); JXWritePC(m16_rx);
ra = inst_next | 0x1; ra = inst_next | 0x1;
delayslot( 1 ); delayslot( 1 );
@@ -539,7 +540,7 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA
} }
:jalx Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=1 & Abs26_m16 :jalx Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=1 & Abs26_m16
[ ext_delay=0b10; ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { [ ext_delay=0b10; ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); globalset(inst_next, ext_delay); ] {
ra = inst_next | 0x1; ra = inst_next | 0x1;
delayslot( 1 ); delayslot( 1 );
ISAModeSwitch = 0; ISAModeSwitch = 0;
@@ -547,14 +548,14 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA
} }
:jr ra is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0 :jr ra is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0
[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { [ ext_delay=0b01; globalset(inst_next, ext_delay); ] {
JXWritePC(ra); JXWritePC(ra);
delayslot( 1 ); delayslot( 1 );
return [pc]; return [pc];
} }
:jr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx :jr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx
[ ext_delay=0b01; globalset(inst_next, ext_delay); globalset(inst_start, ext_delay); ] { [ ext_delay=0b01; globalset(inst_next, ext_delay); ] {
JXWritePC(m16_rx); JXWritePC(m16_rx);
delayslot( 1 ); delayslot( 1 );
goto [pc]; goto [pc];
@@ -883,7 +884,7 @@ E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 <<
lockload(tmp); lockload(tmp);
} }
:lui m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 { :lui m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 {
m16_rx = zext(EXT_LIU8) << 16; m16_rx = zext(EXT_LIU8) << 16;
} }