From 34d080f933921ceab38186943d4ec8274db5ae59 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 6 Feb 2023 18:00:43 +0000 Subject: [PATCH] GP-3079: Corrected pcode for x86 fbld instruction --- Ghidra/Processors/x86/data/languages/ia.sinc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index ca9a1a90af..59aa59621d 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -4071,9 +4071,10 @@ define pcodeop f2xm1; :FIADD spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=0 ... & spec_m32 { ST0 = ST0 f+ int2float(spec_m32); } :FIADD spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=0 ... & spec_m16 { ST0 = ST0 f+ int2float(spec_m16); } -:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { spec_m80 = ST0; fpop(); } +define pcodeop convert_bcd; +:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { fdec(); ST0 = convert_bcd(spec_m80); } -:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = ST0; fpop(); } +:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = convert_bcd(ST0); fpop(); } :FCHS is vexMode=0 & byte=0xD9; byte=0xE0 { ST0 = f- ST0; }