diff --git a/Ghidra/Processors/6805/data/languages/6x09.sinc b/Ghidra/Processors/6805/data/languages/6x09.sinc
index 7f7549ff89..6e788ea1cd 100644
--- a/Ghidra/Processors/6805/data/languages/6x09.sinc
+++ b/Ghidra/Processors/6805/data/languages/6x09.sinc
@@ -229,7 +229,7 @@ EA: "["addr"]" is imm8=0x9F; simm16 [ addr = inst_next; ]
 PAGE2: is op=0x10 { } # PAGE2 opcode prefix (0x10)
 PAGE3: is op=0x11 { } # PAGE3 opcode prefix (0x11)
 
-IMMED1: "#"imm8  is imm8  { tmp:1 = imm8; export tmp; }
+IMMED1: "#"imm8  is imm8  { export *[const]:1 imm8; }
 
 REL:  addr    is simm8  [ addr = inst_next + simm8;  ]   { export *:2 addr; } 
 REL2: addr    is simm16 [ addr = inst_next + simm16; ]   { export *:2 addr; } 
@@ -698,7 +698,8 @@ macro PushEntireState()
  
 :JMP OP2    is (op=0x0E | op=0x6E | op=0x7E) ... & OP2
 {
-        goto OP2;
+        local target = OP2;
+        goto [target];
 }
 
 :CLRA    is op=0x4F 
@@ -944,7 +945,7 @@ macro PushEntireState()
         $(I) = 1;
         $(F) = 1;
         tmp:2 = $(SWI_VECTOR);
-        call[tmp];
+        call [tmp];
 }
 
 ################################################################
@@ -1101,7 +1102,8 @@ macro PushEntireState()
 {
         local addr:2 = inst_next;
         Push2(S, addr);
-        call OP2;
+        local target = OP2;
+        call [target];
 }
 
 :STD OP2    is (op=0xDD | op=0xED | op=0xFD) ... & OP2
@@ -1216,7 +1218,7 @@ macro PushEntireState()
 {
         PushEntireState();
         tmp:2 = $(SWI2_VECTOR);
-        call[tmp];
+        call [tmp];
 }
 
 :CMPD OP2    is PAGE2; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2
@@ -1257,7 +1259,7 @@ macro PushEntireState()
 {
         PushEntireState();
         tmp:2 = $(SWI3_VECTOR);
-        call[tmp];
+        call [tmp];
 }
 
 :CMPU OP2    is PAGE3; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2
diff --git a/Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc b/Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc
index 4bc87f06d0..cebcdd5673 100644
--- a/Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc
+++ b/Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc
@@ -16,11 +16,11 @@ EXG_r0Tmp: V    is reg0_exg=7 & V   { exg16_r0 = 0x0; }
 EXG_r0Tmp: A    is reg0_exg=8 & A   { exg8l_r0 = A; exg8h_r0 = A; }
 EXG_r0Tmp: B    is reg0_exg=9 & B   { exg8l_r0 = B; exg8h_r0 = B; }
 EXG_r0Tmp: CC   is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;}
-EXG_r0Tmp: DP   is reg0_exg=12 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}
+EXG_r0Tmp: DP   is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;}
+EXG_r0Tmp: 0    is reg0_exg=12      { exg16_r0 = 0x0; }
 EXG_r0Tmp: 0    is reg0_exg=13      { exg16_r0 = 0x0; }
-EXG_r0Tmp: 0    is reg0_exg=14      { exg16_r0 = 0x0; }
-EXG_r0Tmp: E    is reg0_exg=15 & E  { exg8l_r0 = E; exg8h_r0 = E; }
-EXG_r0Tmp: F    is reg0_exg=16 & F  { exg8l_r0 = F; exg8h_r0 = F; }
+EXG_r0Tmp: E    is reg0_exg=14 & E  { exg8l_r0 = E; exg8h_r0 = E; }
+EXG_r0Tmp: F    is reg0_exg=15 & F  { exg8l_r0 = F; exg8h_r0 = F; }
 
 EXG_r1Tmp: D    is reg1_exg=0 & D   { exg16_r1 = D; }
 EXG_r1Tmp: X    is reg1_exg=1 & X   { exg16_r1 = X; }
@@ -33,11 +33,11 @@ EXG_r1Tmp: V    is reg1_exg=7 & V   { exg16_r1 = 0x0; }
 EXG_r1Tmp: A    is reg1_exg=8 & A   { exg8l_r1 = A; exg8h_r1 = A; }
 EXG_r1Tmp: B    is reg1_exg=9 & B   { exg8l_r1 = B; exg8h_r1 = B; }
 EXG_r1Tmp: CC   is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = CC;}
-EXG_r1Tmp: DP   is reg1_exg=12 & DP { exg8l_r1 = DP; exg8h_r1 = DP;}
+EXG_r1Tmp: DP   is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = DP;}
+EXG_r1Tmp: 0    is reg1_exg=12      { exg16_r1 = 0x0; }
 EXG_r1Tmp: 0    is reg1_exg=13      { exg16_r1 = 0x0; }
-EXG_r1Tmp: 0    is reg1_exg=14      { exg16_r1 = 0x0; }
-EXG_r1Tmp: E    is reg1_exg=15 & E  { exg8l_r1 = E; exg8h_r1 = E; }
-EXG_r1Tmp: F    is reg1_exg=16 & F  { exg8l_r1 = F; exg8h_r1 = F; }
+EXG_r1Tmp: E    is reg1_exg=14 & E  { exg8l_r1 = E; exg8h_r1 = E; }
+EXG_r1Tmp: F    is reg1_exg=15 & F  { exg8l_r1 = F; exg8h_r1 = F; }
 
 EXG_r0Set: D    is reg0_exg=0 & D   { D = exg16_r1; }
 EXG_r0Set: X    is reg0_exg=1 & X   { X = exg16_r1; }
@@ -161,7 +161,7 @@ TFR_GOTO: is reg1_exg   {  } # PC not set
 }
 
 # Transfer register to another register
-:TFR EXG_r0Set,EXG_r1Set    is op=0x1F; EXG_r0Set & EXG_r1Set & EXG_r0Tmp & TFR_GOTO
+:TFR EXG_r0Tmp,EXG_r1Set    is op=0x1F; EXG_r1Set & EXG_r0Tmp & TFR_GOTO
 {
     build EXG_r0Tmp;
     build EXG_r1Set;