From 5194daa9e57a213f233ed122160a101a1131acce Mon Sep 17 00:00:00 2001 From: Daniele Pusceddu Date: Sat, 6 Jun 2026 13:34:24 +0200 Subject: [PATCH 1/2] ARM M-profile: fix mrsipsr ISR_NUMBER mask (0x1f -> 0x1ff) --- Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc index 1f6b9f8c49..18e646f45b 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -2775,7 +2775,7 @@ mrsipsr: "i" is thc0000=1 & Rd0811 { b:1 = isCurrentModePrivileged(); if (!b) goto ; ipsr:4 = getCurrentExceptionNumber(); - Rd0811 = Rd0811 | (ipsr & 0x1f); + Rd0811 = Rd0811 | (ipsr & 0x1ff); } mrsipsr: is thc0000=0 { } From 70b7ec590ad646ebe767e099a88309fad37035cc Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 10 Jun 2026 07:25:22 -0400 Subject: [PATCH 2/2] GP-6061: Implemented several x86 AVX instructions --- Ghidra/Processors/x86/data/languages/avx.sinc | 165 ++- .../Processors/x86/data/languages/avx2.sinc | 84 +- .../x86/data/languages/avx2_manual.sinc | 20 +- .../Processors/x86/data/languages/avx512.sinc | 120 +- .../x86/data/languages/avx512_manual.sinc | 63 +- .../x86/data/languages/avx_manual.sinc | 30 + Ghidra/Processors/x86/data/languages/fma.sinc | 1041 ++++++++++------- 7 files changed, 949 insertions(+), 574 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/avx.sinc b/Ghidra/Processors/x86/data/languages/avx.sinc index 6184fd39ac..962aee4b1c 100644 --- a/Ghidra/Processors/x86/data/languages/avx.sinc +++ b/Ghidra/Processors/x86/data/languages/avx.sinc @@ -95,63 +95,97 @@ define pcodeop vaddsubps_avx ; } # ANDPD 3-64 PAGE 634 LINE 34821 -define pcodeop vandpd_avx ; :VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m128; + XmmReg1[0,64] = vexVVVV_XmmReg[0,64] & m[0,64]; + XmmReg1[64,64] = vexVVVV_XmmReg[64,64] & m[64,64]; + ZmmReg1 = zext(XmmReg1); } # ANDPD 3-64 PAGE 634 LINE 34824 :VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local m:32 = YmmReg2_m256; + YmmReg1[0,64] = vexVVVV_YmmReg[0,64] & m[0,64]; + YmmReg1[64,64] = vexVVVV_YmmReg[64,64] & m[64,64]; + YmmReg1[128,64] = vexVVVV_YmmReg[128,64] & m[128,64]; + YmmReg1[192,64] = vexVVVV_YmmReg[192,64] & m[192,64]; + ZmmReg1 = zext(YmmReg1); } # ANDPS 3-67 PAGE 637 LINE 34947 -define pcodeop vandps_avx ; :VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local tmp:16 = XmmReg2_m128; + XmmReg1[0,32] = vexVVVV_XmmReg[0,32] & tmp[0,32]; + XmmReg1[32,32] = vexVVVV_XmmReg[32,32] & tmp[32,32]; + XmmReg1[64,32] = vexVVVV_XmmReg[64,32] & tmp[64,32]; + XmmReg1[96,32] = vexVVVV_XmmReg[96,32] & tmp[96,32]; + ZmmReg1 = zext(XmmReg1); } # ANDPS 3-67 PAGE 637 LINE 34950 :VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local tmp:32 = YmmReg2_m256; + YmmReg1[0,32] = vexVVVV_YmmReg[0,32] & tmp[0,32]; + YmmReg1[32,32] = vexVVVV_YmmReg[32,32] & tmp[32,32]; + YmmReg1[64,32] = vexVVVV_YmmReg[64,32] & tmp[64,32]; + YmmReg1[96,32] = vexVVVV_YmmReg[96,32] & tmp[96,32]; + YmmReg1[128,32] = vexVVVV_YmmReg[128,32] & tmp[128,32]; + YmmReg1[160,32] = vexVVVV_YmmReg[160,32] & tmp[160,32]; + YmmReg1[192,32] = vexVVVV_YmmReg[192,32] & tmp[192,32]; + YmmReg1[224,32] = vexVVVV_YmmReg[224,32] & tmp[224,32]; + + ZmmReg1 = zext(YmmReg1); } # ANDNPD 3-70 PAGE 640 LINE 35081 -define pcodeop vandnpd_avx ; :VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m128; + XmmReg1[0,64] = ~vexVVVV_XmmReg[0,64] & m[0,64]; + XmmReg1[64,64] = ~vexVVVV_XmmReg[64,64] & m[64,64]; + ZmmReg1 = zext(XmmReg1); } # ANDNPD 3-70 PAGE 640 LINE 35084 :VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local m:32 = YmmReg2_m256; + YmmReg1[0,64] = ~vexVVVV_YmmReg[0,64] & m[0,64]; + YmmReg1[64,64] = ~vexVVVV_YmmReg[64,64] & m[64,64]; + YmmReg1[128,64] = ~vexVVVV_YmmReg[128,64] & m[128,64]; + YmmReg1[192,64] = ~vexVVVV_YmmReg[192,64] & m[192,64]; + ZmmReg1 = zext(YmmReg1); } # ANDNPS 3-73 PAGE 643 LINE 35207 define pcodeop vandnps_avx ; :VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local tmp:16 = XmmReg2_m128; + XmmReg1[0,32] = ~vexVVVV_XmmReg[0,32] & tmp[0,32]; + XmmReg1[32,32] = ~vexVVVV_XmmReg[32,32] & tmp[32,32]; + XmmReg1[64,32] = ~vexVVVV_XmmReg[64,32] & tmp[64,32]; + XmmReg1[96,32] = ~vexVVVV_XmmReg[96,32] & tmp[96,32]; + ZmmReg1 = zext(XmmReg1); } # ANDNPS 3-73 PAGE 643 LINE 35210 :VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local tmp:32 = YmmReg2_m256; + YmmReg1[0,32] = ~vexVVVV_YmmReg[0,32] & tmp[0,32]; + YmmReg1[32,32] = ~vexVVVV_YmmReg[32,32] & tmp[32,32]; + YmmReg1[64,32] = ~vexVVVV_YmmReg[64,32] & tmp[64,32]; + YmmReg1[96,32] = ~vexVVVV_YmmReg[96,32] & tmp[96,32]; + YmmReg1[128,32] = ~vexVVVV_YmmReg[128,32] & tmp[128,32]; + YmmReg1[160,32] = ~vexVVVV_YmmReg[160,32] & tmp[160,32]; + YmmReg1[192,32] = ~vexVVVV_YmmReg[192,32] & tmp[192,32]; + YmmReg1[224,32] = ~vexVVVV_YmmReg[224,32] & tmp[224,32]; + ZmmReg1 = zext(YmmReg1); } # BLENDPD 3-78 PAGE 648 LINE 35433 @@ -1475,30 +1509,30 @@ define pcodeop vmpsadbw_avx ; define pcodeop vorpd_avx ; :VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128; + ZmmReg1 = zext(XmmReg1); } # ORPD 4-168 PAGE 1288 LINE 66722 :VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256; + ZmmReg1 = zext(YmmReg1); } # ORPS 4-171 PAGE 1291 LINE 66846 define pcodeop vorps_avx ; :VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128; + ZmmReg1 = zext(XmmReg1); } # ORPS 4-171 PAGE 1291 LINE 66848 :VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256; + ZmmReg1 = zext(YmmReg1); } # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302 @@ -1561,24 +1595,53 @@ define pcodeop vpackuswb_avx ; define pcodeop vpaddb_avx ; :VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,8] = vexVVVV_XmmReg[0,8] + XmmReg2_m128[0,8]; + result[8,8] = vexVVVV_XmmReg[8,8] + XmmReg2_m128[8,8]; + result[16,8] = vexVVVV_XmmReg[16,8] + XmmReg2_m128[16,8]; + result[24,8] = vexVVVV_XmmReg[24,8] + XmmReg2_m128[24,8]; + result[32,8] = vexVVVV_XmmReg[32,8] + XmmReg2_m128[32,8]; + result[40,8] = vexVVVV_XmmReg[40,8] + XmmReg2_m128[40,8]; + result[48,8] = vexVVVV_XmmReg[48,8] + XmmReg2_m128[48,8]; + result[56,8] = vexVVVV_XmmReg[56,8] + XmmReg2_m128[56,8]; + result[64,8] = vexVVVV_XmmReg[64,8] + XmmReg2_m128[64,8]; + result[72,8] = vexVVVV_XmmReg[72,8] + XmmReg2_m128[72,8]; + result[80,8] = vexVVVV_XmmReg[80,8] + XmmReg2_m128[80,8]; + result[88,8] = vexVVVV_XmmReg[88,8] + XmmReg2_m128[88,8]; + result[96,8] = vexVVVV_XmmReg[96,8] + XmmReg2_m128[96,8]; + result[104,8] = vexVVVV_XmmReg[104,8] + XmmReg2_m128[104,8]; + result[112,8] = vexVVVV_XmmReg[112,8] + XmmReg2_m128[112,8]; + result[120,8] = vexVVVV_XmmReg[120,8] + XmmReg2_m128[120,8]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660 -define pcodeop vpaddw_avx ; :VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,16] = vexVVVV_XmmReg[0,16] + XmmReg2_m128[0,16]; + result[16,16] = vexVVVV_XmmReg[16,16] + XmmReg2_m128[16,16]; + result[32,16] = vexVVVV_XmmReg[32,16] + XmmReg2_m128[32,16]; + result[48,16] = vexVVVV_XmmReg[48,16] + XmmReg2_m128[48,16]; + result[64,16] = vexVVVV_XmmReg[64,16] + XmmReg2_m128[64,16]; + result[80,16] = vexVVVV_XmmReg[80,16] + XmmReg2_m128[80,16]; + result[96,16] = vexVVVV_XmmReg[96,16] + XmmReg2_m128[96,16]; + result[112,16] = vexVVVV_XmmReg[112,16] + XmmReg2_m128[112,16]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662 -define pcodeop vpaddd_avx ; :VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,32] = vexVVVV_XmmReg[0,32] + XmmReg2_m128[0,32]; + result[32,32] = vexVVVV_XmmReg[32,32] + XmmReg2_m128[32,32]; + result[64,32] = vexVVVV_XmmReg[64,32] + XmmReg2_m128[64,32]; + result[96,32] = vexVVVV_XmmReg[96,32] + XmmReg2_m128[96,32]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664 @@ -1885,24 +1948,6 @@ define pcodeop vpinsrb_avx ; ZmmReg1 = zext(tmp); } -# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324 -define pcodeop vpinsrd_avx ; -:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8 -{ - local tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 ); - ZmmReg1 = zext(tmp); -} - -# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327 -define pcodeop vpinsrq_avx ; -@ifdef IA64 -:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8 -{ - local tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 ); - ZmmReg1 = zext(tmp); -} -@endif - # PINSRW 4-296 PAGE 1416 LINE 73446 define pcodeop vpinsrw_avx ; :VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 @@ -2688,19 +2733,21 @@ define pcodeop vsqrtps_avx ; } # SQRTSD 4-638 PAGE 1758 LINE 91272 -define pcodeop vsqrtsd_avx ; :VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m64; + XmmReg1[0,64] = sqrt(vexVVVV_XmmReg[0,64]); + XmmReg1[64,64]= m[64,64]; + ZmmReg1 = zext(XmmReg1); } # SQRTSS 4-640 PAGE 1760 LINE 91367 -define pcodeop vsqrtss_avx ; :VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m32; + XmmReg1[0,32] = sqrt(vexVVVV_XmmReg[0,32]); + XmmReg1[32,96]= m[32,96]; + ZmmReg1 = zext(XmmReg1); } # STMXCSR 4-647 PAGE 1767 LINE 91697 diff --git a/Ghidra/Processors/x86/data/languages/avx2.sinc b/Ghidra/Processors/x86/data/languages/avx2.sinc index 5bba08c71d..b465d62d44 100644 --- a/Ghidra/Processors/x86/data/languages/avx2.sinc +++ b/Ghidra/Processors/x86/data/languages/avx2.sinc @@ -75,35 +75,95 @@ define pcodeop vpackuswb_avx2 ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68666 -define pcodeop vpaddb_avx2 ; :VPADDB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,8] = vexVVVV_YmmReg[0,8] + YmmReg2_m256[0,8]; + result[8,8] = vexVVVV_YmmReg[8,8] + YmmReg2_m256[8,8]; + result[16,8] = vexVVVV_YmmReg[16,8] + YmmReg2_m256[16,8]; + result[24,8] = vexVVVV_YmmReg[24,8] + YmmReg2_m256[24,8]; + result[32,8] = vexVVVV_YmmReg[32,8] + YmmReg2_m256[32,8]; + result[40,8] = vexVVVV_YmmReg[40,8] + YmmReg2_m256[40,8]; + result[48,8] = vexVVVV_YmmReg[48,8] + YmmReg2_m256[48,8]; + result[56,8] = vexVVVV_YmmReg[56,8] + YmmReg2_m256[56,8]; + result[64,8] = vexVVVV_YmmReg[64,8] + YmmReg2_m256[64,8]; + result[72,8] = vexVVVV_YmmReg[72,8] + YmmReg2_m256[72,8]; + result[80,8] = vexVVVV_YmmReg[80,8] + YmmReg2_m256[80,8]; + result[88,8] = vexVVVV_YmmReg[88,8] + YmmReg2_m256[88,8]; + result[96,8] = vexVVVV_YmmReg[96,8] + YmmReg2_m256[96,8]; + result[104,8] = vexVVVV_YmmReg[104,8] + YmmReg2_m256[104,8]; + result[112,8] = vexVVVV_YmmReg[112,8] + YmmReg2_m256[112,8]; + result[120,8] = vexVVVV_YmmReg[120,8] + YmmReg2_m256[120,8]; + result[128,8] = vexVVVV_YmmReg[128,8] + YmmReg2_m256[128,8]; + result[136,8] = vexVVVV_YmmReg[136,8] + YmmReg2_m256[136,8]; + result[144,8] = vexVVVV_YmmReg[144,8] + YmmReg2_m256[144,8]; + result[152,8] = vexVVVV_YmmReg[152,8] + YmmReg2_m256[152,8]; + result[160,8] = vexVVVV_YmmReg[160,8] + YmmReg2_m256[160,8]; + result[168,8] = vexVVVV_YmmReg[168,8] + YmmReg2_m256[168,8]; + result[176,8] = vexVVVV_YmmReg[176,8] + YmmReg2_m256[176,8]; + result[184,8] = vexVVVV_YmmReg[184,8] + YmmReg2_m256[184,8]; + result[192,8] = vexVVVV_YmmReg[192,8] + YmmReg2_m256[192,8]; + result[200,8] = vexVVVV_YmmReg[200,8] + YmmReg2_m256[200,8]; + result[208,8] = vexVVVV_YmmReg[208,8] + YmmReg2_m256[208,8]; + result[216,8] = vexVVVV_YmmReg[216,8] + YmmReg2_m256[216,8]; + result[224,8] = vexVVVV_YmmReg[224,8] + YmmReg2_m256[224,8]; + result[232,8] = vexVVVV_YmmReg[232,8] + YmmReg2_m256[232,8]; + result[240,8] = vexVVVV_YmmReg[240,8] + YmmReg2_m256[240,8]; + result[248,8] = vexVVVV_YmmReg[248,8] + YmmReg2_m256[248,8]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68668 -define pcodeop vpaddw_avx2 ; :VPADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,16] = vexVVVV_YmmReg[0,16] + YmmReg2_m256[0,16]; + result[16,16] = vexVVVV_YmmReg[16,16] + YmmReg2_m256[16,16]; + result[32,16] = vexVVVV_YmmReg[32,16] + YmmReg2_m256[32,16]; + result[48,16] = vexVVVV_YmmReg[48,16] + YmmReg2_m256[48,16]; + result[64,16] = vexVVVV_YmmReg[64,16] + YmmReg2_m256[64,16]; + result[80,16] = vexVVVV_YmmReg[80,16] + YmmReg2_m256[80,16]; + result[96,16] = vexVVVV_YmmReg[96,16] + YmmReg2_m256[96,16]; + result[112,16] = vexVVVV_YmmReg[112,16] + YmmReg2_m256[112,16]; + result[128,16] = vexVVVV_YmmReg[128,16] + YmmReg2_m256[128,16]; + result[144,16] = vexVVVV_YmmReg[144,16] + YmmReg2_m256[144,16]; + result[160,16] = vexVVVV_YmmReg[160,16] + YmmReg2_m256[160,16]; + result[176,16] = vexVVVV_YmmReg[176,16] + YmmReg2_m256[176,16]; + result[192,16] = vexVVVV_YmmReg[192,16] + YmmReg2_m256[192,16]; + result[208,16] = vexVVVV_YmmReg[208,16] + YmmReg2_m256[208,16]; + result[224,16] = vexVVVV_YmmReg[224,16] + YmmReg2_m256[224,16]; + result[240,16] = vexVVVV_YmmReg[240,16] + YmmReg2_m256[240,16]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68670 -define pcodeop vpaddd_avx2 ; :VPADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,32] = vexVVVV_YmmReg[0,32] + YmmReg2_m256[0,32]; + result[32,32] = vexVVVV_YmmReg[32,32] + YmmReg2_m256[32,32]; + result[64,32] = vexVVVV_YmmReg[64,32] + YmmReg2_m256[64,32]; + result[96,32] = vexVVVV_YmmReg[96,32] + YmmReg2_m256[96,32]; + result[128,32] = vexVVVV_YmmReg[128,32] + YmmReg2_m256[128,32]; + result[160,32] = vexVVVV_YmmReg[160,32] + YmmReg2_m256[160,32]; + result[192,32] = vexVVVV_YmmReg[192,32] + YmmReg2_m256[192,32]; + result[224,32] = vexVVVV_YmmReg[224,32] + YmmReg2_m256[224,32]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68672 -define pcodeop vpaddq_avx2 ; :VPADDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,64] = vexVVVV_YmmReg[0,64] + YmmReg2_m256[0,64]; + result[64,64] = vexVVVV_YmmReg[64,64] + YmmReg2_m256[64,64]; + result[128,64] = vexVVVV_YmmReg[128,64] + YmmReg2_m256[128,64]; + result[192,64] = vexVVVV_YmmReg[192,64] + YmmReg2_m256[192,64]; + + ZmmReg1 = zext(result); } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69045 diff --git a/Ghidra/Processors/x86/data/languages/avx2_manual.sinc b/Ghidra/Processors/x86/data/languages/avx2_manual.sinc index ad61779417..7fdaafa2d3 100644 --- a/Ghidra/Processors/x86/data/languages/avx2_manual.sinc +++ b/Ghidra/Processors/x86/data/languages/avx2_manual.sinc @@ -1,13 +1,15 @@ # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785 -define pcodeop vinserti128 ; -:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 { - local tmp:16 = XmmReg2_m128; - local cond0:16 = zext((imm8_0:1 & 0x1) == 0); - local cond1:16 = zext((imm8_0:1 & 0x1) == 1); - # ignoring all but the least significant bit - YmmReg1[0,128] = (cond0 * tmp) + (cond1 * vexVVVV_YmmReg[0,128]); - YmmReg1[128,128] = (cond0 * vexVVVV_YmmReg[128,128]) + (cond1 * tmp); - +:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0{ + local scr1l:16 = vexVVVV_YmmReg[0,128]; + local scr1h:16 = vexVVVV_YmmReg[128,128]; + local src2:16 = XmmReg2_m128; + local vcond:1 = (imm8_0:1 & 0x1) == 0; + local part1:16 = 0; + conditionalAssign(part1, vcond, src2, scr1l); + local part2:16 = 0; + conditionalAssign(part2, vcond, scr1h, src2); + YmmReg1[0,128] = part1; + YmmReg1[128,128] = part2; } # VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903 diff --git a/Ghidra/Processors/x86/data/languages/avx512.sinc b/Ghidra/Processors/x86/data/languages/avx512.sinc index 4c34492988..0b887ee2a2 100644 --- a/Ghidra/Processors/x86/data/languages/avx512.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512.sinc @@ -2140,11 +2140,10 @@ define pcodeop vmulss_avx512f ; } # ORPD 4-168 PAGE 1288 LINE 66724 -define pcodeop vorpd_avx512vl ; :VORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - XmmResult = vorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst ); + XmmResult = evexV5_XmmReg | XmmReg2_m128_m64bcst; XmmMask = XmmReg1; build XmmOpMask64; ZmmReg1 = zext(XmmResult); @@ -2154,29 +2153,27 @@ define pcodeop vorpd_avx512vl ; :VORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - YmmResult = vorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst ); + YmmResult = evexV5_YmmReg | YmmReg2_m256_m64bcst; YmmMask = YmmReg1; build YmmOpMask64; ZmmReg1 = zext(YmmResult); } # ORPD 4-168 PAGE 1288 LINE 66730 -define pcodeop vorpd_avx512dq ; :VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - ZmmResult = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); + ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m64bcst; ZmmMask = ZmmReg1; build ZmmOpMask64; ZmmReg1 = ZmmResult; } # ORPS 4-171 PAGE 1291 LINE 66850 -define pcodeop vorps_avx512vl ; :VORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - XmmResult = vorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst ); + XmmResult = evexV5_XmmReg | XmmReg2_m128_m32bcst; XmmMask = XmmReg1; build XmmOpMask32; ZmmReg1 = zext(XmmResult); @@ -2186,18 +2183,17 @@ define pcodeop vorps_avx512vl ; :VORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - YmmResult = vorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); + YmmResult = evexV5_YmmReg | YmmReg2_m256_m32bcst; YmmMask = YmmReg1; build YmmOpMask32; ZmmReg1 = zext(YmmResult); } # ORPS 4-171 PAGE 1291 LINE 66856 -define pcodeop vorps_avx512dq ; :VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - ZmmResult = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); + ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m32bcst; ZmmMask = ZmmReg1; build ZmmOpMask32; ZmmReg1 = ZmmResult; @@ -2717,20 +2713,20 @@ define pcodeop vpaddusw_avx512bw ; # PALIGNR 4-219 PAGE 1339 LINE 69495 define pcodeop vpalignr_avx512vl ; -:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128 ); + XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 ); XmmMask = XmmReg1; build XmmOpMask8; ZmmReg1 = zext(XmmResult); } # PALIGNR 4-219 PAGE 1339 LINE 69499 -:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256 ); + YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 ); YmmMask = YmmReg1; build YmmOpMask8; ZmmReg1 = zext(YmmResult); @@ -2738,15 +2734,16 @@ define pcodeop vpalignr_avx512vl ; # PALIGNR 4-219 PAGE 1339 LINE 69505 define pcodeop vpalignr_avx512bw ; -:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); + ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 ); ZmmMask = ZmmReg1; build ZmmOpMask8; ZmmReg1 = ZmmResult; } + # PAND 4-223 PAGE 1343 LINE 69684 define pcodeop vpandd_avx512vl ; :VPANDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst @@ -5816,70 +5813,6 @@ define pcodeop vpunpcklqdq_avx512f ; ZmmReg1 = ZmmResult; } -# PXOR 4-518 PAGE 1638 LINE 85503 -define pcodeop vpxord_avx512vl ; -:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - XmmResult = vpxord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst ); - XmmMask = XmmReg1; - build XmmOpMask32; - ZmmReg1 = zext(XmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85505 -:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - YmmResult = vpxord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); - YmmMask = YmmReg1; - build YmmOpMask32; - ZmmReg1 = zext(YmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85507 -define pcodeop vpxord_avx512f ; -:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - ZmmResult = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); - ZmmMask = ZmmReg1; - build ZmmOpMask32; - ZmmReg1 = ZmmResult; -} - -# PXOR 4-518 PAGE 1638 LINE 85514 -define pcodeop vpxorq_avx512vl ; -:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - XmmResult = vpxorq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst ); - XmmMask = XmmReg1; - build XmmOpMask64; - ZmmReg1 = zext(XmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85521 -:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - YmmResult = vpxorq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst ); - YmmMask = YmmReg1; - build YmmOpMask64; - ZmmReg1 = zext(YmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85523 -define pcodeop vpxorq_avx512f ; -:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - ZmmResult = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); - ZmmMask = ZmmReg1; - build ZmmOpMask64; - ZmmReg1 = ZmmResult; -} - # SHUFPD 4-617 PAGE 1737 LINE 90231 define pcodeop vshufpd_avx512vl ; :VSHUFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 @@ -6009,25 +5942,27 @@ define pcodeop vsqrtps_avx512f ; } # SQRTSD 4-638 PAGE 1758 LINE 91276 -define pcodeop vsqrtsd_avx512f ; -:VSQRTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VSQRTSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - XmmResult = vsqrtsd_avx512f( evexV5_XmmReg, XmmReg2_m64 ); + XmmResult[0,64] = sqrt(XmmReg2_m64[0,64]); XmmMask = XmmReg1; - build XmmOpMask64; - ZmmReg1 = zext(XmmResult); + conditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]); + XmmReg1[0,64] = XmmResult[0,64]; + XmmReg1[64,64]= evexV5_XmmReg[64,64]; + ZmmReg1 = zext(XmmReg1); } # SQRTSS 4-640 PAGE 1760 LINE 91371 -define pcodeop vsqrtss_avx512f ; -:VSQRTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VSQRTSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - XmmResult = vsqrtss_avx512f( evexV5_XmmReg, XmmReg2_m32 ); + XmmResult[0,32] = sqrt(XmmReg2_m32[0,32]); XmmMask = XmmReg1; - build XmmOpMask32; - ZmmReg1 = zext(XmmResult); + conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]); + XmmReg1[0,32] = XmmResult[0,32]; + XmmReg1[32,96]=evexV5_XmmReg[32,96]; + ZmmReg1 = zext(XmmReg1); } # SUBPD 4-656 PAGE 1776 LINE 92120 @@ -17646,11 +17581,10 @@ define pcodeop vsqrtph_avx512fp16 ; define pcodeop vsqrtsh_avx512fp16 ; :VSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 { - XmmResult = vsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 ); + XmmResult[0,16] = sqrt(XmmReg2_m16[0,16]); XmmMask = XmmReg1; - build XmmOpMask; conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]); - XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged + XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] = src1[127:16] ZmmReg1 = zext(XmmResult); } diff --git a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc index ef603b157d..27e2c70803 100644 --- a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc @@ -1582,4 +1582,65 @@ define pcodeop vpmovuswb_avx512bw ; YmmMask = m256; build YmmOpMask8; m256 = zext(YmmResult); -} \ No newline at end of file +} + +# PXOR 4-518 PAGE 1638 LINE 85503 +:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m32bcst; + XmmMask = XmmReg1; + build XmmOpMask32; + ZmmReg1 = zext(XmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85505 +:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m32bcst; + YmmMask = YmmReg1; + build YmmOpMask32; + ZmmReg1 = zext(YmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85507 +:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m32bcst; + ZmmMask = ZmmReg1; + build ZmmOpMask32; + ZmmReg1 = ZmmResult; +} + +# PXOR 4-518 PAGE 1638 LINE 85514 +:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m64bcst; + XmmMask = XmmReg1; + build XmmOpMask64; + ZmmReg1 = zext(XmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85521 +:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m64bcst; + YmmMask = YmmReg1; + build YmmOpMask64; + ZmmReg1 = zext(YmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85523 +:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m64bcst; + ZmmMask = ZmmReg1; + build ZmmOpMask64; + ZmmReg1 = ZmmResult; +} + diff --git a/Ghidra/Processors/x86/data/languages/avx_manual.sinc b/Ghidra/Processors/x86/data/languages/avx_manual.sinc index 9b84e34e1d..15ab16d5cc 100644 --- a/Ghidra/Processors/x86/data/languages/avx_manual.sinc +++ b/Ghidra/Processors/x86/data/languages/avx_manual.sinc @@ -192,6 +192,36 @@ ZmmReg1 = zext(XmmReg1); } +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324 +#define pcodeop vpinsrd_avx ; +:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8 +{ + local tmp:4 = rm32; + local cond0:1 = (imm8:1 & 0x3) == 0; + local cond1:1 = (imm8:1 & 0x3) == 1; + local cond2:1 = (imm8:1 & 0x3) == 2; + local cond3:1 = (imm8:1 & 0x3) == 3; + conditionalAssign(XmmReg1[ 0,32], cond0, tmp, vexVVVV_XmmReg[ 0,32]); + conditionalAssign(XmmReg1[32,32], cond0, tmp, vexVVVV_XmmReg[32,32]); + conditionalAssign(XmmReg1[64,32], cond0, tmp, vexVVVV_XmmReg[64,32]); + conditionalAssign(XmmReg1[96,32], cond0, tmp, vexVVVV_XmmReg[96,32]); + ZmmReg1 = zext(XmmReg1); +} + +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327 +#define pcodeop vpinsrq_avx ; +@ifdef IA64 +:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8 +{ + local tmp:8 = rm64; + local cond0:8 = zext((imm8:1 & 0x1) == 0); + local cond1:8 = zext((imm8:1 & 0x1) == 1); + # ignoring all but the least significant bit + XmmReg1[0,64] = (cond0 * tmp) + (cond1 * vexVVVV_XmmReg[0,64]); + XmmReg1[64,64] = (cond0 * vexVVVV_XmmReg[64,64]) + (cond1 * tmp); + ZmmReg1 = zext(XmmReg1); +} +@endif # PMOVMSKB 4-338 PAGE 1458 LINE 75651 :VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest diff --git a/Ghidra/Processors/x86/data/languages/fma.sinc b/Ghidra/Processors/x86/data/languages/fma.sinc index 930a0f4e27..297d3af2c1 100644 --- a/Ghidra/Processors/x86/data/languages/fma.sinc +++ b/Ghidra/Processors/x86/data/languages/fma.sinc @@ -1,740 +1,981 @@ # # x86 FMA instructions # +macro fmadd(dest, src1, src2, src3) { + dest = (src1 f* src2) f+ src3; +} +macro fmadd132(dest, src1, src2, src3) { + fmadd(dest, src1, src3, src2); +} -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101211 -define pcodeop vfmadd132pd_fma ; +macro fmadd213(dest, src1, src2, src3) { + fmadd(dest, src2, src1, src3); +} + +macro fmadd231(dest, src1, src2, src3) { + fmadd(dest, src2, src3, src1); +} + +macro fmsub(dest, src1, src2, src3) { + dest = (src1 f* src2) f- src3; +} + +macro fmsub132(dest, src1, src2, src3) { + fmsub(dest, src1, src3, src2); +} + +macro fmsub213(dest, src1, src2, src3) { + fmsub(dest, src2, src1, src3); +} + +macro fmsub231(dest, src1, src2, src3) { + fmsub(dest, src2, src3, src1); +} + +macro fnmadd(dest, src1, src2, src3) { + dest = f- (src1 f* src2) f+ src3; +} + +macro fnmadd132(dest, src1, src2, src3) { + fnmadd(dest, src1, src3, src2); +} + +macro fnmadd213(dest, src1, src2, src3) { + fnmadd(dest, src2, src1, src3); +} + +macro fnmadd231(dest, src1, src2, src3) { + fnmadd(dest, src2, src3, src1); +} + +macro fnmsub(dest, src1, src2, src3) { + dest = f- (src1 f* src2) f- src3; +} + +macro fnmsub132(dest, src1, src2, src3) { + fnmsub(dest, src1, src3, src2); +} + +macro fnmsub213(dest, src1, src2, src3) { + fnmsub(dest, src2, src1, src3); +} + +macro fnmsub231(dest, src1, src2, src3) { + fnmsub(dest, src2, src3, src1); +} + +# VFMADD132PD/VFMADD213PD/VFMADD231PD :VFMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101214 -define pcodeop vfmadd213pd_fma ; :VFMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101217 -define pcodeop vfmadd231pd_fma ; :VFMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101220 :VFMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101223 :VFMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101226 :VFMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101572 -define pcodeop vfmadd132ps_fma ; +# VFMADD132PS/VFMADD213PS/VFMADD231PS :VFMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101575 -define pcodeop vfmadd213ps_fma ; :VFMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101578 -define pcodeop vfmadd231ps_fma ; :VFMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101581 :VFMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101584 :VFMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587 -# WARNING: did not recognize VEX field 0 for "VFMADD231PS ymm1, ymm2, ymm3/m256" :VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101931 -define pcodeop vfmadd132sd_fma ; +# VFMADD132SD/VFMADD213SD/VFMADD231SD :VFMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101934 -define pcodeop vfmadd213sd_fma ; :VFMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101937 -define pcodeop vfmadd231sd_fma ; :VFMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102099 -define pcodeop vfmadd132ss_fma ; +# VFMADD132SS/VFMADD213SS/VFMADD231SS :VFMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102102 -define pcodeop vfmadd213ss_fma ; :VFMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102105 -define pcodeop vfmadd231ss_fma ; :VFMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102272 -define pcodeop vfmaddsub132pd_fma ; +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD :VFMADDSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102275 -define pcodeop vfmaddsub213pd_fma ; :VFMADDSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102278 -define pcodeop vfmaddsub231pd_fma ; :VFMADDSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102281 :VFMADDSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd132(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub132(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd132(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102284 :VFMADDSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd213(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub213(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd213(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102287 :VFMADDSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd231(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub231(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd231(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102711 -define pcodeop vfmaddsub132ps_fma ; +# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS :VFMADDSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd132(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub132(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd132(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102714 -define pcodeop vfmaddsub213ps_fma ; :VFMADDSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd213(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub213(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd213(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102717 -define pcodeop vfmaddsub231ps_fma ; :VFMADDSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd231(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub231(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd231(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102720 :VFMADDSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102723 :VFMADDSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102726 :VFMADDSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103141 -define pcodeop vfmsubadd132pd_fma ; -:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103144 -define pcodeop vfmsubadd213pd_fma ; -:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103147 -define pcodeop vfmsubadd231pd_fma ; -:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103150 -:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103153 -:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103156 -:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103581 -define pcodeop vfmsubadd132ps_fma ; -:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103584 -define pcodeop vfmsubadd213ps_fma ; -:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103587 -define pcodeop vfmsubadd231ps_fma ; -:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -{ - local tmp:16 = vfmsubadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103590 -:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103593 -:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103596 -:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -{ - local tmp:16 = vfmsubadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); -} - -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104019 -define pcodeop vfmsub132pd_fma ; +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104022 -define pcodeop vfmsub213pd_fma ; +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104025 -define pcodeop vfmsub231pd_fma ; +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104028 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104031 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104034 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD :VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104379 -define pcodeop vfmsub132ps_fma ; +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104382 -define pcodeop vfmsub213ps_fma ; +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104385 -define pcodeop vfmsub231ps_fma ; +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104388 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104391 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394 -# WARNING: did not recognize VEX field 0 for "VFMSUB231PS ymm1, ymm2, ymm3/m256" +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS :VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104738 -define pcodeop vfmsub132sd_fma ; +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD :VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104741 -define pcodeop vfmsub213sd_fma ; +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD :VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104744 -define pcodeop vfmsub231sd_fma ; +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD :VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104913 -define pcodeop vfmsub132ss_fma ; +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS :VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104916 -define pcodeop vfmsub213ss_fma ; +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS :VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104919 -define pcodeop vfmsub231ss_fma ; +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS :VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105088 -define pcodeop vfnmadd132pd_fma ; +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD +:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd132(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub132(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd132(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub132(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); +} + +:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd213(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub213(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd213(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub213(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); +} + +:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd231(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub231(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd231(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub231(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS +:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd132(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub132(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd132(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub132(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd213(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub213(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd213(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub213(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +{ + fmadd231(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub231(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd231(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub231(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); +} + +:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); +} + +:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); +} + +:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +{ + fmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105091 -define pcodeop vfnmadd213pd_fma ; +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105094 -define pcodeop vfnmadd231pd_fma ; +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105097 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105100 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105103 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105447 -define pcodeop vfnmadd132ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105450 -define pcodeop vfnmadd213ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105453 -define pcodeop vfnmadd231ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105456 +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105459 +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 :VFNMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462 -# WARNING: did not recognize VEX field 0 for "VFNMADD231PS ymm1, ymm2, ymm3/m256" +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105794 -define pcodeop vfnmadd132sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105797 -define pcodeop vfnmadd213sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105800 -define pcodeop vfnmadd231sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105966 -define pcodeop vfnmadd132ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105969 -define pcodeop vfnmadd213ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105972 -define pcodeop vfnmadd231ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106138 -define pcodeop vfnmsub132pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106141 -define pcodeop vfnmsub213pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106144 -define pcodeop vfnmsub231pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106147 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106150 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106153 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106487 -define pcodeop vfnmsub132ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106490 -define pcodeop vfnmsub213ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106493 -define pcodeop vfnmsub231ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106496 +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106499 +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502 -# WARNING: did not recognize VEX field 0 for "VFNMSUB231PS ymm1, ymm2, ymm3/m256" +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106832 -define pcodeop vfnmsub132sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106835 -define pcodeop vfnmsub213sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106838 -define pcodeop vfnmsub231sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107004 -define pcodeop vfnmsub132ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107007 -define pcodeop vfnmsub213ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107010 -define pcodeop vfnmsub231ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); }