From 44d8733f8c4da09fb99ca0f8199ebb3432a8a3e3 Mon Sep 17 00:00:00 2001 From: ghidra1 Date: Wed, 12 May 2021 09:09:15 -0400 Subject: [PATCH] GP-928 corrected missing operand for SPARC WR instruction --- .../assembler/sleigh/SparcAssemblyTest.java | 4 ++-- .../Processors/Sparc/data/languages/SparcV9.sinc | 15 ++++++++------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/SparcAssemblyTest.java b/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/SparcAssemblyTest.java index 5342b9c433..522b5e24e4 100644 --- a/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/SparcAssemblyTest.java +++ b/Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/SparcAssemblyTest.java @@ -27,7 +27,7 @@ public class SparcAssemblyTest extends AbstractAssemblyTest { @Test public void testAssemble_rd_Y_g2() { - assertOneCompatRestExact("rd Y,g2", "85:40:00:00"); + assertOneCompatRestExact("rd %Y,g2", "85:40:00:00"); } // Too many reserved/undefined bits: 524288 instructions to test @@ -38,6 +38,6 @@ public class SparcAssemblyTest extends AbstractAssemblyTest { @Test public void testAssemble_wr_g3_g0() { - assertOneCompatRestExact("wr g3,g0", "81:80:00:03"); + assertOneCompatRestExact("wr g0,g3,%Y", "81:80:00:03"); } } diff --git a/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc b/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc index 2b5ad895eb..9405a57b3f 100644 --- a/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc +++ b/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc @@ -850,16 +850,17 @@ attach variables [ rd_asr ] [ Y _ _ _ _ _ STICK STICK_CMPR asr26 asr27 asr28 asr29 asr30 asr31 ]; # ASR write registers -wrCCR: "%"^CCR is rd_asr=2 & CCR { } # packed CCR register displayed -wrASI: "%"^ASI is rd_asr=3 & ASI { } -wrFPRS: "%"^FPRS is rd_asr=6 & FPRS { } +wrCCR: "%"^CCR is rd_asr=2 & CCR { export CCR; } # packed CCR register displayed +wrASI: "%"^ASI is rd_asr=3 & ASI { export ASI; } +wrFPRS: "%"^FPRS is rd_asr=6 & FPRS { export FPRS; } +wrASR: "%"^rd_asr is rd_asr { export rd_asr; } #---------------WR ASR special register (SIR instruction must be defined after this instruction) # NOTE: the following ASR register numbers are not allowed: 1, 4, 5, 7..14 -:wr regorimm,wrCCR is op=0x2 & regorimm & op3=0x30 & rd_asr=2 & wrCCR { unpackflags(regorimm); } -:wr regorimm,wrASI is op=0x2 & regorimm & op3=0x30 & rd_asr=3 & wrASI { ASI = regorimm:1; } -:wr regorimm,wrFPRS is op=0x2 & regorimm & op3=0x30 & rd_asr=6 & wrFPRS { FPRS = regorimm:1; } -:wr regorimm,rd_asr is op=0x2 & regorimm & op3=0x30 & rd_asr { rd_asr = regorimm; } +:wr RS1,regorimm,wrCCR is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=2 & wrCCR { local tmp = RS1 ^ regorimm; unpackflags(tmp); } +:wr RS1,regorimm,wrASI is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=3 & wrASI { local tmp = RS1 ^ regorimm; wrASI = tmp:1; } +:wr RS1,regorimm,wrFPRS is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=6 & wrFPRS { local tmp = RS1 ^ regorimm; FPRS = tmp:1; } +:wr RS1,regorimm,wrASR is op=0x2 & RS1 & regorimm & op3=0x30 & wrASR { wrASR = RS1 ^ regorimm; } #---------------MISC sethidisp: "%hi("^hi^")" is udisp22 [hi=udisp22<<10;] { export *[const]:$(SIZE) hi; }