From 8371098d191bfd59414d833a0b0bc51bd46ed469 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 18 Jan 2024 15:19:52 -0500 Subject: [PATCH] GP-3787: Added CR operand to PowerPC VLE conditional branches --- .../PowerPC/data/languages/ppc.ldefs | 4 ++-- .../PowerPC/data/languages/ppc_vle.sinc | 19 +++++++++++++++---- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs index f61ea275e1..47444ba2dd 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs +++ b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs @@ -210,7 +210,7 @@ endian="big" size="32" variant="PowerQUICC-III-e500mc" - version="1.5" + version="1.6" slafile="ppc_32_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -225,7 +225,7 @@ endian="little" size="32" variant="PowerQUICC-III-e500mc" - version="1.5" + version="1.6" slafile="ppc_32_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc index f57d1d94bf..a6b72c40fa 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc @@ -21,7 +21,7 @@ CC32: "dnz" is BO_VLE=2 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; } CC32: "dz" is BO_VLE=3 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; } addrBD8: reloc is BD8_VLE [ reloc = inst_start + (BD8_VLE << 1);] { export *[ram]:4 reloc; } -addrBD15: reloc is BD15_VLE [ reloc = inst_start + (BD15_VLE << 1);] { export *[ram]:4 reloc; } +addrBD15: reloc is BD15_VLE [ reloc = inst_start + (BD15_VLE << 1);] { export *[ram]:4 reloc; } addrBD24: reloc is BD24_VLE [ reloc = inst_start + (BD24_VLE << 1);] { export *[ram]:4 reloc; } d8PlusRaAddress: S8IMM(A) is S8IMM & A {tmp:$(REGISTER_SIZE) = A+S8IMM; export tmp; } @@ -70,18 +70,29 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | # NOTE: For the conditional branches, the "official" mnemonics have just bc and bcl. # We use extended mnemonics so the display is understandable without having to cross- # reference multiple tables. -:e_b^CC32 addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32 { +:e_b^CC32 BI_CR_VLE, addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 { if (CC32 == 0) goto inst_next; goto addrBD15; } -:e_b^CC32^"l" addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32 { +:e_b^CC32^"l" BI_CR_VLE, addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 { if (CC32 == 0) goto inst_next; LR= inst_next; call [addrBD15]; } -:se_b^CC16 addrBD8 is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16 { +:e_b^CC32 addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=1 & CC32 { + if (CC32 == 0) goto inst_next; + goto addrBD15; +} + +:e_b^CC32^"l" addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=1 & CC32 { + if (CC32 == 0) goto inst_next; + LR= inst_next; + call [addrBD15]; +} + +:se_b^CC16 cr0, addrBD8 is $(ISVLE) & OP5_VLE=28 & addrBD8 & cr0 & CC16 { if (CC16 == 0) goto inst_next; goto addrBD8; }