From 5fe0f16e102eb0e9ca436ea2416ed0b8771dda96 Mon Sep 17 00:00:00 2001
From: mumbel <22204578+mumbel@users.noreply.github.com>
Date: Sat, 31 Oct 2020 20:47:40 -0500
Subject: [PATCH] c.fsw broken under double-precision

if FP is 64, should still handle single precision
---
 .../Processors/RISCV/certification.manifest   | 30 +++++++++----------
 .../RISCV/data/languages/riscv.rvc.sinc       |  2 +-
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/Ghidra/Processors/RISCV/certification.manifest b/Ghidra/Processors/RISCV/certification.manifest
index 0df1bf8e2f..aff3d4083a 100644
--- a/Ghidra/Processors/RISCV/certification.manifest
+++ b/Ghidra/Processors/RISCV/certification.manifest
@@ -1,12 +1,15 @@
 ##VERSION: 2.0
 Module.manifest||GHIDRA||||END|
 build.gradle||GHIDRA||||END|
-data/languages/riscv32.cspec||GHIDRA||||END|
-data/languages/riscv32.dwarf||GHIDRA||||END|
-data/languages/riscv32-fp.cspec||GHIDRA||||END|
-data/languages/riscv64.cspec||GHIDRA||||END|
-data/languages/riscv64.dwarf||GHIDRA||||END|
-data/languages/riscv64-fp.cspec||GHIDRA||||END|
+data/languages/RV32G.pspec||GHIDRA||||END|
+data/languages/RV32GC.pspec||GHIDRA||||END|
+data/languages/RV32I.pspec||GHIDRA||||END|
+data/languages/RV32IC.pspec||GHIDRA||||END|
+data/languages/RV32IMC.pspec||GHIDRA||||END|
+data/languages/RV64G.pspec||GHIDRA||||END|
+data/languages/RV64GC.pspec||GHIDRA||||END|
+data/languages/RV64I.pspec||GHIDRA||||END|
+data/languages/RV64IC.pspec||GHIDRA||||END|
 data/languages/riscv.csr.sinc||GHIDRA||||END|
 data/languages/riscv.custom.sinc||GHIDRA||||END|
 data/languages/riscv.ilp32d.slaspec||GHIDRA||||END|
@@ -38,15 +41,12 @@ data/languages/riscv.rvc.sinc||GHIDRA||||END|
 data/languages/riscv.rvv.sinc||GHIDRA||||END|
 data/languages/riscv.table.sinc||GHIDRA||||END|
 data/languages/riscv.zi.sinc||GHIDRA||||END|
-data/languages/RV32GC.pspec||GHIDRA||||END|
-data/languages/RV32G.pspec||GHIDRA||||END|
-data/languages/RV32IC.pspec||GHIDRA||||END|
-data/languages/RV32IMC.pspec||GHIDRA||||END|
-data/languages/RV32I.pspec||GHIDRA||||END|
-data/languages/RV64GC.pspec||GHIDRA||||END|
-data/languages/RV64G.pspec||GHIDRA||||END|
-data/languages/RV64IC.pspec||GHIDRA||||END|
-data/languages/RV64I.pspec||GHIDRA||||END|
+data/languages/riscv32-fp.cspec||GHIDRA||||END|
+data/languages/riscv32.cspec||GHIDRA||||END|
+data/languages/riscv32.dwarf||GHIDRA||||END|
+data/languages/riscv64-fp.cspec||GHIDRA||||END|
+data/languages/riscv64.cspec||GHIDRA||||END|
+data/languages/riscv64.dwarf||GHIDRA||||END|
 data/patterns/patterncontraints.xml||GHIDRA||||END|
 data/patterns/riscv_gc_patterns.xml||GHIDRA||||END|
 scripts/binutil.py||GHIDRA||||END|
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
index 6d5cd7dd72..fd021d3906 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
@@ -136,7 +136,7 @@
 @endif
 
 @if ADDRSIZE == "32"
-@if FPSIZE == "32"
+@if FPSIZE == "32" || FPSIZE == "64"
 # c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4) 
 :c.fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm
 {