From 671add87ab4b5a3aeb5583a226703ea00850979d Mon Sep 17 00:00:00 2001 From: Shawn Hoffman Date: Thu, 7 May 2026 16:03:00 -0700 Subject: [PATCH] hexagon_hvx: add V81 valign4 stub Adds a decode-only stub for V6_valign4. The six veqhf/veqsf qfloat-accumulating predicate forms that originally accompanied this are not added: upstream's hexagon_hvx2.sinc implements all of them with real p-code. --- Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc index 045754cd4d..43509bb90b 100644 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc @@ -6877,4 +6877,10 @@ define pcodeop scatter_release; scatter_release(VAlignMemAddrRxAIMu); } +# (hvx,1) valign4 -- "Vd = valign4(Vu, Vv, Rt8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 0 0 0 z z t t t P P 0 u u u u u 1 0 1 d d d d d + +:valign4 Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op2123=0x0 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) unimpl