diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
index a38313fe23..827eddb41a 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
@@ -11,13 +11,13 @@
 }
 
 # csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) 
-:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711
+:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711
 {
 	local tmprs1:$(XLEN) = rs1;
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	local newcsr:$(XLEN) = oldcsr & ~tmprs1;
 	csr = newcsr;
-	rdDst = oldcsr;
+	rd = oldcsr;
 }
 
 # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) 
@@ -30,19 +30,19 @@
 
 
 # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) 
-:csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
+:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	local tmp:$(XLEN) = op1519;
 	csr = oldcsr & ~tmp;
-	rdDst = oldcsr;
+	rd = oldcsr;
 }
 
 
 # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
-:csrr rdDst,csr is csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711
+:csrr rd,csr is csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711
 {
-	rdDst = csr:$(XLEN);
+	rd = csr:$(XLEN);
 }
 
 # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
@@ -53,11 +53,11 @@
 }
 
 # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) 
-:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711
+:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	csr = oldcsr | rs1;
-	rdDst  = oldcsr;
+	rd  = oldcsr;
 }
 
 # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) 
@@ -69,12 +69,12 @@
 }
 
 # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) 
-:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711
+:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	local tmp:$(XLEN) = op1519;
 	csr = oldcsr | tmp;
-	rdDst = oldcsr;
+	rd = oldcsr;
 }
 
 # csrw d,E,s 00001073 0000707f SIMPLE (0, 0) 
@@ -84,12 +84,12 @@
 }
 
 # csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) 
-:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1
+:csrrw rd,csr,rs1 is rs1 & csr & rd & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1
 {
 	local tmprs1:$(XLEN) = rs1;
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	csr = tmprs1;
-	rdDst = oldcsr;
+	rd = oldcsr;
 }
 
 # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) 
@@ -100,31 +100,31 @@
 }
 
 # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) 
-:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711
+:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711
 {
 	local oldcsr:$(XLEN) = csr:$(XLEN);
 	local val:$(XLEN) = op1519;
 	csr = val;
-	rdDst = oldcsr;
+	rd = oldcsr;
 }
 
 
 # frcsr d 00302073 fffff07f SIMPLE (0, 0) 
-:frcsr rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60
+:frcsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60
 {
-	rdDst = fcsr;
+	rd = fcsr;
 }
 
 # frflags d 00102073 fffff07f SIMPLE (0, 0) 
-:frflags rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20
+:frflags rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20
 {
-	rdDst = zext(fflags[0,5]);
+	rd = zext(fflags[0,5]);
 }
 
 # frrm d 00202073 fffff07f SIMPLE (0, 0) 
-:frrm rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40
+:frrm rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40
 {
-	rdDst = frm;
+	rd = frm;
 }
 
 # fscsr s 00301073 fff07fff SIMPLE (0, 0) 
@@ -135,9 +135,9 @@
 }
 
 # fscsr d,s 00301073 fff0707f SIMPLE (0, 0) 
-:fscsr rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3
+:fscsr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3
 {
-	rdDst = fcsr;
+	rd = fcsr;
 	fcsr = rs1;
 }
 
@@ -150,16 +150,16 @@
 }
 
 # fsflags d,s 00101073 fff0707f SIMPLE (0, 0) 
-:fsflags rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1
+:fsflags rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1
 {
-	rdDst = zext(fflags[0,5]);
+	rd = zext(fflags[0,5]);
 	fflags[0,5] = rs1[0,5];
 }
 
 # fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0) 
-:fsflagsi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1
+:fsflagsi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1
 {
-	rdDst = zext(fflags[0,5]);
+	rd = zext(fflags[0,5]);
 	local tmp:1 = op1519:1;
 	fflags[0,5] = tmp[0,5];
 }
@@ -180,16 +180,16 @@
 }
 
 # fsrm d,s 00201073 fff0707f SIMPLE (0, 0) 
-:fsrm rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2
+:fsrm rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2
 {
-	rdDst = zext(frm[0,3]);
+	rd = zext(frm[0,3]);
 	frm[0,3] = rs1[0,3];
 }
 
 # fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0) 
-:fsrmi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2
+:fsrmi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2
 {
-	rdDst = zext(frm[0,3]);
+	rd = zext(frm[0,3]);
 	local tmp:1 = op1519:1;
 	frm[0,3] = tmp[0,3];
 }
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
index 2cd1ab08e4..05d1692c7f 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
@@ -615,33 +615,30 @@ rs3: r2731 is r2731 { export r2731; }
 rs3: zero is zero & op2731=0 { export 0:$(XLEN); }
 
 rd: r0711 is r0711 { export r0711; }
-rd: zero is r0711 & zero & op0711=0 { local tempZero:$(XLEN) = 0; export tempZero; }
-rdDst: r0711 is r0711 { export r0711; }
-
+rd: zero is r0711=0 & zero { local tmp:$(XLEN) = 0; export tmp; }
 
 rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; }
-rs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); }
+rs1W: zero  is r1519 & zero & op1519=0 { export 0:$(WXLEN); }
 
 rs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; }
 rs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); }
 
-#TODO  dest may be bad, might need an assign macro
 rdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; }
-rdW: zero is r0711 & zero & op0711=0 { export 0:$(WXLEN); }
-
+rdW: zero is r0711=0 & zero { local tmp:$(WXLEN) = 0; export tmp; }
 
 
 #TODO  does this need to be in an if/endif
 @if ADDRSIZE == "64"
-rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; }
+rs1L: r1519 is r1519 { export r1519; }
 rs1L: zero is r1519 & zero & op1519=0 { export 0:8; }
 
-rs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; }
+rs2L: r2024 is r2024 { export r2024; }
 rs2L: zero is r2024 & zero & op2024=0 { export 0:8; }
 
-#TODO  dest may be bad, might need an assign macro
 rdL: r0711 is r0711 { export r0711; }
-rdL: zero is r0711 & zero & op0711=0 { export 0:8; }
+rdL: zero is r0711=0 & zero { local tmp:8 = 0; export tmp; }
+
+
 @endif