diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/pe/ExportDataDirectory.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/pe/ExportDataDirectory.java
index 54d14c39cf..01bb7df906 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/pe/ExportDataDirectory.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/pe/ExportDataDirectory.java
@@ -314,7 +314,7 @@ public class ExportDataDirectory extends DataDirectory implements StructConverte
 
 				// See if this function has an associated name exported for it.
 				for (int j = 0; j < numberOfNames; ++j) {
-					int jthOrdinalVal = reader.readShort(pointerToOrdinals + (j * 2));
+					int jthOrdinalVal = reader.readUnsignedShort(pointerToOrdinals + (j * 2));
 					if (jthOrdinalVal == i) {
 						int jthNameRVA = reader.readInt(pointerToNames + (j * 4));
 						int jthNamePtr = ntHeader.rvaToPointer(jthNameRVA);
diff --git a/Ghidra/Processors/MCS96/data/languages/MCS96.sinc b/Ghidra/Processors/MCS96/data/languages/MCS96.sinc
index b75988fac0..2ac6ab0650 100644
--- a/Ghidra/Processors/MCS96/data/languages/MCS96.sinc
+++ b/Ghidra/Processors/MCS96/data/languages/MCS96.sinc
@@ -617,11 +617,7 @@ macro setSignedShiftRightCarryFlag(shiftee,amount) {
 :CMPL dlreg, lreg                   is op8=0xc5; lreg; dlreg {
 	op1:4 = lreg;
 	tmp:4 = dlreg - op1;
-	$(N) = (tmp s< 0);
-	$(Z) = (tmp == 0);
-	$(C) = scarry(dlreg, op1);
-	$(V) = (((dlreg & ~op1 & ~tmp) | (~dlreg & op1 & tmp)) & 0x80000000 ) != 0;
-	$(VT) = $(VT) | $(V);
+	subtractFlags(dlreg, op1, tmp);
 }
 
 @endif
diff --git a/Ghidra/Processors/x86/data/languages/avx.sinc b/Ghidra/Processors/x86/data/languages/avx.sinc
index 962aee4b1c..59b3dd6f07 100644
--- a/Ghidra/Processors/x86/data/languages/avx.sinc
+++ b/Ghidra/Processors/x86/data/languages/avx.sinc
@@ -1871,14 +1871,14 @@ define pcodeop vpextrq_avx ;
 
 # PEXTRW 4-277 PAGE 1397 LINE 72478
 define pcodeop vpextrw_avx ;
-:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
+:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
 {
 	Reg32 = vpextrw_avx( XmmReg2, imm8:1 );
 	# TODO Reg64 = zext(Reg32)
 }
 
 # PEXTRW 4-277 PAGE 1397 LINE 72483
-:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
+:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
 {
 	Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 );
 	# TODO Reg64 = zext(Reg32)
diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc
index 7763d811f9..6f0be02112 100644
--- a/Ghidra/Processors/x86/data/languages/ia.sinc
+++ b/Ghidra/Processors/x86/data/languages/ia.sinc
@@ -4215,7 +4215,7 @@ define pcodeop swap_bytes;
 :NEG Rmr64      is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); }
 @endif
 
-:NOP            is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8)  { }
+:NOP            is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8 | rexWRXBprefix=0)  { }
 :NOP rm16       is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16  ...    { }
 :NOP rm32       is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32  ...    { }
 :NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ...    { }