diff --git a/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc b/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc
index 6c22719974..6da2a34e72 100644
--- a/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc
+++ b/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc
@@ -132,48 +132,27 @@ macro either_or1(res, cond, true, false)	# if condition is == 1
 
 macro shift_right_logic(res, var, shift_)
 {
-	local shift = (shift_ & 0x1f);
-	local mask = 0;
-
-	if(shift == 0)
-		goto <false>;
-
-	mask = var & (1 << (shift - 1));
+	local shift = shift_ & 0x1f;
+	local mask = (zext(shift != 0) * (var & (1 << (shift - 1)))) + (zext(shift == 0) * 0);
 	res = var >> shift;
-
-	<false>
 	set_OV0_S_Z(res);
 	$(CY) = ((mask != 0) && (shift != 0));
 }
 
 macro shift_right_arith(res, var, shift_)
 {
-	local shift = (shift_ & 0x1f);
-	local mask = 0;
-
-	if(shift == 0)
-		goto <false>;
-
-	mask = var & (1 << (shift - 1));
+	local shift = shift_ & 0x1f;
+	local mask = (zext(shift != 0) * (var & (1 << (shift - 1)))) + (zext(shift == 0) * 0);
 	res = var s>> shift;
-
-	<false>
 	set_OV0_S_Z(res);
 	$(CY) = ((mask != 0) && (shift != 0));
 }
 
 macro shift_left_logic(res, var, shift_) 
 {
-	local shift = (shift_ & 0x1f);
-	local mask = 0;
-
-	if(shift == 0)
-		goto <false>;
-
+	local shift = shift_ & 0x1f;
+	local mask = (zext(shift != 0) * (var & (1 << (32 - shift)))) + (zext(shift == 0) * 0);
 	res = var << shift;
-	mask = var & (1 << (32 - shift));
-
-	<false>
 	set_OV0_S_Z(res);
 	$(CY) = ((mask != 0) && (shift != 0));
 }
diff --git a/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc b/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc
index 7cf8e85d73..9320b6a2e7 100644
--- a/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc
+++ b/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc
@@ -255,8 +255,8 @@ define pcodeop __saturate;
 	$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
 	set_Z(R1115);
 	set_S(R1115);
-	either_or(R1115, (R1115 == R2731), mod, quot);	#if reg2 == reg3 the remainder is stored, if not the quotient is stored
-	R2731 = mod;
+	R1115 = quot;
+ 	R2731 = mod;
 }
 
 # DIVH reg1, reg2 - rrrrr000010RRRRR
@@ -271,24 +271,24 @@ define pcodeop __saturate;
 # DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000
 :divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731
 {
-	local quot:4 = sext(R1115:2 s/ R0004:2);
-	local mod:4 = sext(R1115:2 s% R0004:2);
+	local quot:4 = R1115 s/ sext(R0004:2);
+	local mod:4 = R1115 s% sext(R0004:2);
 	$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
 	set_Z(R1115);
 	set_S(R1115);
-	either_or(R1115, (R1115 == R2731), mod, quot);
+	R1115 = quot;
 	R2731 = mod;
 }
 
 # DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010
 :divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731
 {
-	local quot:4 = sext(R1115:2 / R0004:2);
-	local mod:4 = sext(R1115:2 % R0004:2);
+	local quot:4 = R1115 / sext(R0004:2);
+	local mod:4 = R1115 % sext(R0004:2);
 	$(OV) = (R0004 == 0);
 	set_Z(R1115);
 	set_S(R1115);
-	either_or(R1115, (R1115 == R2731), mod, quot);
+	R1115 = quot;
 	R2731 = mod;
 }
 
@@ -300,7 +300,7 @@ define pcodeop __saturate;
 	$(OV) = (R0004 == 0);
 	set_Z(R1115);
 	set_S(R1115);
-	either_or(R1115, (R1115 == R2731), mod, quot);
+	R1115 = quot;
 	R2731 = mod;
 }
 
diff --git a/Ghidra/Processors/V850/data/languages/V850.cspec b/Ghidra/Processors/V850/data/languages/V850.cspec
index d956aae7c1..0a04f7e6cd 100644
--- a/Ghidra/Processors/V850/data/languages/V850.cspec
+++ b/Ghidra/Processors/V850/data/languages/V850.cspec
@@ -40,9 +40,16 @@
       </output>
       
       <unaffected>
-        <register name="sp"/>
-        <register name="gp"/>
-        <register name="tp"/>
+        <register name="r20"/>
+        <register name="r21"/>
+        <register name="r22"/>
+        <register name="r23"/>
+        <register name="r24"/>
+        <register name="r25"/>
+        <register name="r26"/>
+        <register name="r27"/>
+        <register name="r28"/>
+        <register name="r29"/>
       </unaffected>
     
     </prototype>
diff --git a/Ghidra/Processors/V850/data/languages/V850.ldefs b/Ghidra/Processors/V850/data/languages/V850.ldefs
index 556c4add1f..d8adc0a4dd 100644
--- a/Ghidra/Processors/V850/data/languages/V850.ldefs
+++ b/Ghidra/Processors/V850/data/languages/V850.ldefs
@@ -10,7 +10,7 @@
             processorspec="V850.pspec"
             manualindexfile="../manuals/v850.idx"
             id="V850:LE:32:default">
-    <description>Renesas V850E2M</description>
+    <description>Renesas V850 family</description>
     <compiler name="default" spec="V850.cspec" id="default"/>
   </language>
 </language_definitions>
\ No newline at end of file