mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-09-28 17:11:11 -09:00
Candidate release of source code.
This commit is contained in:
Dan
0
Ghidra/Processors/6502/Module.manifest
Normal file
0
Ghidra/Processors/6502/Module.manifest
Normal file
8
Ghidra/Processors/6502/build.gradle
Normal file
8
Ghidra/Processors/6502/build.gradle
Normal file
@@ -0,0 +1,8 @@
|
||||
apply plugin: 'eclipse'
|
||||
eclipse.project.name = 'Processors 6502'
|
||||
|
||||
/*********************************************************************************
|
||||
* Imports
|
||||
*********************************************************************************/
|
||||
apply from: "$rootProject.projectDir/gradleScripts/processorUtils.gradle"
|
||||
|
||||
11
Ghidra/Processors/6502/certification.manifest
Normal file
11
Ghidra/Processors/6502/certification.manifest
Normal file
@@ -0,0 +1,11 @@
|
||||
##VERSION: 2.0
|
||||
.classpath||GHIDRA||||END|
|
||||
.project||GHIDRA||||END|
|
||||
Module.manifest||GHIDRA||||END|
|
||||
build.gradle||GHIDRA||||END|
|
||||
data/build.xml||GHIDRA||||END|
|
||||
data/languages/6502.cspec||GHIDRA||||END|
|
||||
data/languages/6502.ldefs||GHIDRA||||END|
|
||||
data/languages/6502.pspec||GHIDRA||||END|
|
||||
data/languages/6502.slaspec||GHIDRA||||END|
|
||||
data/manuals/6502.idx||GHIDRA||||END|
|
||||
73
Ghidra/Processors/6502/data/build.xml
Normal file
73
Ghidra/Processors/6502/data/build.xml
Normal file
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<!--
|
||||
+ Compile sleigh languages within this module.
|
||||
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
|
||||
+ From command line (requires ant install)
|
||||
+ - cd to data directory containing this file
|
||||
+ - run ant
|
||||
-->
|
||||
|
||||
<project name="privateBuildDeveloper" default="sleigh-compile">
|
||||
|
||||
<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
|
||||
|
||||
<property name="repo.dir" value="../../../.." />
|
||||
<property name="repo.marker.dir" value="${repo.dir}/.git" />
|
||||
|
||||
<condition property="devmode">
|
||||
<available file="${repo.marker.dir}" type="dir" />
|
||||
</condition>
|
||||
|
||||
<target name="build-sleigh-classpath-dev" if="devmode">
|
||||
|
||||
<property name="framework.path" value="${repo.dir}/../ghidra.git/Ghidra/Framework"/>
|
||||
<property name="libs.path" value="${repo.dir}/../ghidra.bin.git/ExternalLibraries/libsForRuntime"/>
|
||||
|
||||
<path id="sleigh.class.path">
|
||||
<pathelement location="${framework.path}/SoftwareModeling/bin"/>
|
||||
<pathelement location="${framework.path}/Generic/bin"/>
|
||||
<pathelement location="${framework.path}/Utility/bin"/>
|
||||
<fileset dir="${libs.path}">
|
||||
<include name="*.jar"/>
|
||||
</fileset>
|
||||
</path>
|
||||
|
||||
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
|
||||
|
||||
</target>
|
||||
|
||||
<target name="build-sleigh-classpath-dist" unless="devmode">
|
||||
<property name="framework.path" value="../../../Framework"/>
|
||||
|
||||
<path id="sleigh.class.path">
|
||||
<fileset dir="${framework.path}/SoftwareModeling/lib">
|
||||
<include name="*.jar"/>
|
||||
</fileset>
|
||||
<fileset dir="${framework.path}/Generic/lib">
|
||||
<include name="*.jar"/>
|
||||
</fileset>
|
||||
<fileset dir="${framework.path}/Utility/lib">
|
||||
<include name="*.jar"/>
|
||||
</fileset>
|
||||
</path>
|
||||
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
|
||||
|
||||
</target>
|
||||
|
||||
<target name="sleigh-compile" depends="build-sleigh-classpath-dist, build-sleigh-classpath-dev">
|
||||
|
||||
<fail unless="sleigh.compile.exists" />
|
||||
|
||||
<java classname="${sleigh.compile.class}"
|
||||
classpathref="sleigh.class.path"
|
||||
fork="true"
|
||||
failonerror="true">
|
||||
<jvmarg value="-Xmx2048M"/>
|
||||
<arg value="-a"/>
|
||||
<arg value="./languages"/>
|
||||
</java>
|
||||
|
||||
</target>
|
||||
|
||||
</project>
|
||||
34
Ghidra/Processors/6502/data/languages/6502.cspec
Normal file
34
Ghidra/Processors/6502/data/languages/6502.cspec
Normal file
@@ -0,0 +1,34 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<compiler_spec>
|
||||
<global>
|
||||
<range space="RAM"/>
|
||||
</global>
|
||||
<stackpointer register="SP" space="RAM" growth="negative"/>
|
||||
<returnaddress>
|
||||
<varnode space="stack" offset="1" size="2"/>
|
||||
</returnaddress>
|
||||
<default_proto>
|
||||
<prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
|
||||
<input>
|
||||
<pentry minsize="1" maxsize="1">
|
||||
<register name="A"/>
|
||||
</pentry>
|
||||
<pentry minsize="1" maxsize="1">
|
||||
<register name="X"/>
|
||||
</pentry>
|
||||
<pentry minsize="1" maxsize="1">
|
||||
<register name="Y"/>
|
||||
</pentry>
|
||||
</input>
|
||||
<output>
|
||||
<pentry minsize="1" maxsize="1">
|
||||
<register name="A"/>
|
||||
</pentry>
|
||||
</output>
|
||||
<unaffected>
|
||||
<register name="SP"/>
|
||||
</unaffected>
|
||||
</prototype>
|
||||
</default_proto>
|
||||
</compiler_spec>
|
||||
37
Ghidra/Processors/6502/data/languages/6502.ldefs
Normal file
37
Ghidra/Processors/6502/data/languages/6502.ldefs
Normal file
@@ -0,0 +1,37 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<language_definitions>
|
||||
|
||||
<language processor="6502"
|
||||
endian="little"
|
||||
size="16"
|
||||
variant="default"
|
||||
version="1.0"
|
||||
slafile="6502.sla"
|
||||
processorspec="6502.pspec"
|
||||
manualindexfile="../manuals/6502.idx"
|
||||
id="6502:LE:16:default">
|
||||
<description>6502 Microcontroller Family</description>
|
||||
<compiler name="default" spec="6502.cspec" id="default"/>
|
||||
<external_name tool="IDA-PRO" name="m6502"/>
|
||||
<external_name tool="IDA-PRO" name="m65c02"/>
|
||||
</language>
|
||||
|
||||
<!-- The following entry has a very misleading language id but
|
||||
can not be removed since it may have already been referenced.
|
||||
This entry has been marked deprecated to avoid its use in the future.
|
||||
-->
|
||||
<language deprecated="true"
|
||||
processor="6502"
|
||||
endian="little"
|
||||
size="16"
|
||||
variant="default"
|
||||
version="1.0"
|
||||
slafile="6502.sla"
|
||||
processorspec="6502.pspec"
|
||||
id="6502:BE:16:default">
|
||||
<description>6502 Microcontroller Family</description>
|
||||
<compiler name="default" spec="6502.cspec" id="default"/>
|
||||
</language>
|
||||
|
||||
</language_definitions>
|
||||
47
Ghidra/Processors/6502/data/languages/6502.pspec
Normal file
47
Ghidra/Processors/6502/data/languages/6502.pspec
Normal file
@@ -0,0 +1,47 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<processor_spec>
|
||||
<programcounter register="PC"/>
|
||||
|
||||
<volatile outputop="write" inputop="read">
|
||||
<range space="RAM" first="0x0" last="0x20"/>
|
||||
</volatile>
|
||||
|
||||
<default_symbols>
|
||||
<symbol name="PORTA" address="0"/>
|
||||
<symbol name="PORTB" address="1"/>
|
||||
<symbol name="PORTC" address="2"/>
|
||||
<symbol name="PORTD" address="3"/>
|
||||
<symbol name="DDRA" address="4"/>
|
||||
<symbol name="DDRB" address="5"/>
|
||||
<symbol name="DDRC" address="6"/>
|
||||
<symbol name="DDRD" address="7"/>
|
||||
<symbol name="SPCR" address="A"/>
|
||||
<symbol name="SPSR" address="B"/>
|
||||
<symbol name="SPDR" address="C"/>
|
||||
<symbol name="BAUD" address="D"/>
|
||||
<symbol name="SCCR1" address="E"/>
|
||||
<symbol name="SCCR2" address="F"/>
|
||||
<symbol name="SCSR" address="10"/>
|
||||
<symbol name="SCDAT" address="11"/>
|
||||
<symbol name="TCR" address="12"/>
|
||||
<symbol name="TSR" address="13"/>
|
||||
<symbol name="ICHR" address="14"/>
|
||||
<symbol name="ICLR" address="15"/>
|
||||
<symbol name="OCHR" address="16"/>
|
||||
<symbol name="OCLR" address="17"/>
|
||||
<symbol name="CHR" address="18"/>
|
||||
<symbol name="CLR" address="19"/>
|
||||
<symbol name="ACHR" address="1A"/>
|
||||
<symbol name="ACLR" address="1B"/>
|
||||
<symbol name="NMI" address="FFFA" entry="true" type="code_ptr"/>
|
||||
<symbol name="RES" address="FFFC" entry="true" type="code_ptr"/>
|
||||
<symbol name="IRQ" address="FFFE" entry="true" type="code_ptr"/>
|
||||
</default_symbols>
|
||||
|
||||
<default_memory_blocks>
|
||||
<memory_block name="IO" start_address="0" length="0x20" initialized="false"/>
|
||||
<memory_block name="LOW_RAM" start_address="0x20" length="0xff" initialized="false"/>
|
||||
<memory_block name="STACK" start_address="0x0100" length="0x01ff" initialized="false"/>
|
||||
</default_memory_blocks>
|
||||
</processor_spec>
|
||||
477
Ghidra/Processors/6502/data/languages/6502.slaspec
Normal file
477
Ghidra/Processors/6502/data/languages/6502.slaspec
Normal file
@@ -0,0 +1,477 @@
|
||||
# sleigh specification file for MOS 6502
|
||||
|
||||
define endian=little;
|
||||
define alignment=1;
|
||||
|
||||
define space RAM type=ram_space size=2 default;
|
||||
define space register type=register_space size=1;
|
||||
|
||||
define register offset=0x00 size=1 [ A X Y P ];
|
||||
define register offset=0x20 size=2 [ PC SP ];
|
||||
define register offset=0x20 size=1 [ PCL PCH S SH ];
|
||||
define register offset=0x30 size=1 [ N V B D I Z C ]; # status bits
|
||||
|
||||
#TOKENS
|
||||
|
||||
define token opbyte (8)
|
||||
op = (0,7)
|
||||
|
||||
aaa = (5,7)
|
||||
bbb = (2,4)
|
||||
cc = (0,1)
|
||||
;
|
||||
|
||||
define token data8 (8)
|
||||
imm8 = (0,7)
|
||||
rel = (0,7) signed
|
||||
;
|
||||
|
||||
define token data (16)
|
||||
imm16 = (0,15)
|
||||
;
|
||||
|
||||
macro popSR() {
|
||||
local ccr = *:1 SP;
|
||||
N = ccr[7,1];
|
||||
V = ccr[6,1];
|
||||
B = ccr[4,1];
|
||||
D = ccr[3,1];
|
||||
I = ccr[3,1];
|
||||
Z = ccr[1,1];
|
||||
C = ccr[0,1];
|
||||
}
|
||||
|
||||
macro pushSR() {
|
||||
local ccr:1 = 0xff;
|
||||
ccr[7,1] = N;
|
||||
ccr[6,1] = V;
|
||||
ccr[4,1] = B;
|
||||
ccr[3,1] = D;
|
||||
ccr[3,1] = I;
|
||||
ccr[1,1] = Z;
|
||||
ccr[0,1] = C;
|
||||
*:1 (SP) = ccr;
|
||||
SP = SP -1;
|
||||
}
|
||||
|
||||
macro resultFlags(value) {
|
||||
Z = (value == 0);
|
||||
N = (value s< 0);
|
||||
}
|
||||
|
||||
macro subtraction_flags1(register, operand, result) {
|
||||
local complement_register = ~register;
|
||||
|
||||
V = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0;
|
||||
N = (result s< 0);
|
||||
Z = (result == 0);
|
||||
C = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0;
|
||||
}
|
||||
|
||||
|
||||
################################################################
|
||||
# Psuedo Instructions
|
||||
################################################################
|
||||
|
||||
define pcodeop readIRQ;
|
||||
|
||||
################################################################
|
||||
REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; }
|
||||
|
||||
|
||||
OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = imm8 + zext(X); tmp:2 = *:2 addr; export *:1 tmp; }
|
||||
OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
|
||||
OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
|
||||
OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
|
||||
OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
|
||||
OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
|
||||
OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
|
||||
OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
|
||||
|
||||
|
||||
OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
|
||||
OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
|
||||
OP2: A is bbb=2 & A { export A; }
|
||||
OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
|
||||
OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
|
||||
OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
|
||||
|
||||
OP2ST: OP2 is OP2 { export OP2; }
|
||||
OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = imm8 + zext(Y); export *:1 tmp; }
|
||||
|
||||
OP2LD: OP2 is OP2 { export OP2; }
|
||||
OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = imm8 + zext(Y); export *:1 tmp; }
|
||||
OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
|
||||
|
||||
|
||||
ADDR8: imm8 is imm8 { export *:1 imm8; }
|
||||
ADDR16: imm16 is imm16 { export *:1 imm16; }
|
||||
ADDRI: imm16 is imm16 { tmp:2 = imm16; export *:2 tmp; }
|
||||
|
||||
|
||||
# Instructions
|
||||
|
||||
|
||||
:ADC OP1 is (cc=1 & aaa=3) ... & OP1
|
||||
{
|
||||
local op1 = OP1;
|
||||
local tmpC = C;
|
||||
|
||||
C = carry(A, op1);
|
||||
|
||||
A = A + op1 + tmpC;
|
||||
|
||||
resultFlags(A);
|
||||
V = C;
|
||||
}
|
||||
|
||||
:AND OP1 is (cc=1 & aaa=1) ... & OP1
|
||||
{
|
||||
A = A & OP1;
|
||||
resultFlags(A);
|
||||
}
|
||||
|
||||
:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2
|
||||
{
|
||||
local tmp = OP2;
|
||||
C = tmp >> 7;
|
||||
tmp = tmp << 1;
|
||||
OP2 = tmp;
|
||||
resultFlags(tmp);
|
||||
}
|
||||
|
||||
:BCC REL is op=0x90; REL
|
||||
{
|
||||
if (C == 0) goto REL;
|
||||
}
|
||||
|
||||
:BCS REL is op=0xB0; REL
|
||||
{
|
||||
if (C) goto REL;
|
||||
}
|
||||
|
||||
:BEQ REL is op=0xF0; REL
|
||||
{
|
||||
if (Z) goto REL;
|
||||
}
|
||||
|
||||
:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2
|
||||
{
|
||||
local value = A & OP2;
|
||||
resultFlags(value);
|
||||
}
|
||||
|
||||
:BMI REL is op=0x30; REL
|
||||
{
|
||||
if (N) goto REL;
|
||||
}
|
||||
|
||||
:BNE REL is op=0xD0; REL
|
||||
{
|
||||
if (Z == 0) goto REL;
|
||||
}
|
||||
|
||||
:BPL REL is op=0x10; REL
|
||||
{
|
||||
if (N == 0) goto REL;
|
||||
}
|
||||
|
||||
:BRK is op=0x00
|
||||
{
|
||||
goto inst_start;
|
||||
}
|
||||
|
||||
:BVC REL is op=0x50; REL
|
||||
{
|
||||
if (V == 0) goto REL;
|
||||
}
|
||||
|
||||
:BVS REL is op=0x70; REL
|
||||
{
|
||||
if (V) goto REL;
|
||||
}
|
||||
|
||||
:CLC is op=0x18
|
||||
{
|
||||
C = 0;
|
||||
}
|
||||
|
||||
:CLD is op=0xD8
|
||||
{
|
||||
D = 0;
|
||||
}
|
||||
|
||||
:CLI is op=0x58
|
||||
{
|
||||
I = 0;
|
||||
}
|
||||
|
||||
:CLV is op=0xB8
|
||||
{
|
||||
V = 0;
|
||||
}
|
||||
|
||||
:CMP OP1 is (cc=1 & aaa=6) ... & OP1
|
||||
{
|
||||
local op1 = OP1;
|
||||
local tmp = A - op1;
|
||||
resultFlags(tmp);
|
||||
C = (A < op1);
|
||||
}
|
||||
|
||||
:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2
|
||||
{
|
||||
local op1 = OP2;
|
||||
local tmp = X - op1;
|
||||
resultFlags(tmp);
|
||||
C = (A < op1);
|
||||
}
|
||||
|
||||
:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2
|
||||
{
|
||||
local op1 = OP2;
|
||||
local tmp = Y - op1;
|
||||
resultFlags(tmp);
|
||||
C = (A < op1);
|
||||
}
|
||||
|
||||
:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2
|
||||
{
|
||||
local tmp = OP2 - 1;
|
||||
OP2 = tmp;
|
||||
resultFlags(tmp);
|
||||
}
|
||||
|
||||
:DEX is op=0xCA
|
||||
{
|
||||
X = X - 1;
|
||||
resultFlags(X);
|
||||
}
|
||||
|
||||
|
||||
:DEY is op=0x88
|
||||
{
|
||||
Y = Y -1;
|
||||
resultFlags(Y);
|
||||
}
|
||||
|
||||
:EOR OP1 is (cc=1 & aaa=2) ... & OP1
|
||||
{
|
||||
local op1 = OP1;
|
||||
A = A ^ op1;
|
||||
resultFlags(A);
|
||||
}
|
||||
|
||||
:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2
|
||||
{
|
||||
local tmp = OP2 + 1;
|
||||
OP2 = tmp;
|
||||
resultFlags(tmp);
|
||||
}
|
||||
|
||||
:INY is op=0xC8
|
||||
{
|
||||
Y = Y + 1;
|
||||
resultFlags(Y);
|
||||
}
|
||||
|
||||
:INX is op=0xE8
|
||||
{
|
||||
X = X + 1;
|
||||
resultFlags(X);
|
||||
}
|
||||
|
||||
:JMP ADDR16 is (op=0x4C); ADDR16
|
||||
{
|
||||
goto ADDR16;
|
||||
}
|
||||
|
||||
:JMP ADDRI is (op=0x6c); ADDRI
|
||||
{
|
||||
goto [ADDRI];
|
||||
}
|
||||
|
||||
:JSR ADDR16 is op=0x20; ADDR16
|
||||
{
|
||||
*:2 (SP-1) = inst_next;
|
||||
SP=SP-2;
|
||||
call ADDR16;
|
||||
}
|
||||
|
||||
:LDA OP1 is (cc=1 & aaa=5) ... & OP1
|
||||
{
|
||||
A = OP1;
|
||||
resultFlags(A);
|
||||
}
|
||||
|
||||
:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2
|
||||
{
|
||||
Y = OP2;
|
||||
resultFlags(Y);
|
||||
}
|
||||
|
||||
:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD
|
||||
{
|
||||
X = OP2LD;
|
||||
resultFlags(X);
|
||||
}
|
||||
|
||||
:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2
|
||||
{
|
||||
local tmp = OP2;
|
||||
C = tmp & 1;
|
||||
tmp = tmp >> 1;
|
||||
OP2 = tmp;
|
||||
Z = (tmp == 0);
|
||||
N = 0;
|
||||
}
|
||||
|
||||
:NOP is op=0xEA
|
||||
{
|
||||
}
|
||||
|
||||
:ORA OP1 is (cc=1 & aaa=0) ... & OP1
|
||||
{
|
||||
A = A | OP1;
|
||||
resultFlags(A);
|
||||
}
|
||||
|
||||
:PHP is op=0x8
|
||||
{
|
||||
pushSR();
|
||||
}
|
||||
|
||||
:PLP is op=0x28
|
||||
{
|
||||
popSR();
|
||||
}
|
||||
|
||||
:PHA is op=0x48
|
||||
{
|
||||
*:1 (SP) = A;
|
||||
SP = SP - 1;
|
||||
}
|
||||
|
||||
:PLA is op=0x68
|
||||
{
|
||||
SP = SP + 1;
|
||||
A = *:1 (SP);
|
||||
}
|
||||
|
||||
:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2
|
||||
{
|
||||
local tmpC = C;
|
||||
local op2 = OP2;
|
||||
C = op2 >> 7;
|
||||
local result = op2 << 1;
|
||||
result = result | tmpC;
|
||||
OP2 = result;
|
||||
resultFlags(result);
|
||||
}
|
||||
|
||||
:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2
|
||||
{
|
||||
local tmpC = C << 7;
|
||||
local tmp = OP2;
|
||||
C = tmp & 1;
|
||||
tmp = tmp >> 1;
|
||||
tmp = tmp | tmpC;
|
||||
OP2 = tmp;
|
||||
resultFlags(tmp);
|
||||
}
|
||||
:RTI is op=0x40
|
||||
{
|
||||
popSR();
|
||||
SP = SP+1;
|
||||
|
||||
SP = SP+1;
|
||||
tmp:2 = *:2 SP;
|
||||
SP = SP+1;
|
||||
|
||||
return [tmp];
|
||||
}
|
||||
|
||||
:RTS is op=0x60
|
||||
{
|
||||
SP = SP+1;
|
||||
tmp:2 = *:2 SP;
|
||||
SP = SP+1;
|
||||
|
||||
return [tmp];
|
||||
}
|
||||
|
||||
:SBC OP1 is (cc=1 & aaa=7) ... & OP1
|
||||
{
|
||||
local op1 = OP1;
|
||||
local result = A - op1 - C;
|
||||
|
||||
subtraction_flags1(A, op1, result);
|
||||
A = result;
|
||||
|
||||
# resultFlags(tmp);
|
||||
# C = ((A <= op1) * C) | (A < op1);
|
||||
# A = tmp;
|
||||
}
|
||||
|
||||
:SEC is op=0x38
|
||||
{
|
||||
C = 1;
|
||||
}
|
||||
|
||||
:SED is op=0xF8
|
||||
{
|
||||
D = 1;
|
||||
}
|
||||
|
||||
:SEI is op=0x78
|
||||
{
|
||||
I = 1;
|
||||
}
|
||||
|
||||
:STA OP1 is (cc=1 & aaa=4) ... & OP1
|
||||
{
|
||||
OP1 = A;
|
||||
resultFlags(A);
|
||||
}
|
||||
|
||||
:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST
|
||||
{
|
||||
OP2ST = X;
|
||||
resultFlags(X);
|
||||
}
|
||||
|
||||
:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2
|
||||
{
|
||||
OP2 = Y;
|
||||
resultFlags(Y);
|
||||
}
|
||||
|
||||
:TAX is op=0xAA
|
||||
{
|
||||
X = A;
|
||||
}
|
||||
|
||||
:TAY is op=0xA8
|
||||
{
|
||||
Y = A;
|
||||
}
|
||||
|
||||
:TSX is op=0xBA
|
||||
{
|
||||
X = S;
|
||||
}
|
||||
|
||||
:TXA is op=0x8A
|
||||
{
|
||||
A = X;
|
||||
}
|
||||
|
||||
:TXS is op=0x9A
|
||||
{
|
||||
S = X;
|
||||
}
|
||||
|
||||
:TYA is op=0x98
|
||||
{
|
||||
A = Y;
|
||||
}
|
||||
57
Ghidra/Processors/6502/data/manuals/6502.idx
Normal file
57
Ghidra/Processors/6502/data/manuals/6502.idx
Normal file
@@ -0,0 +1,57 @@
|
||||
@mcs6500_family_programming_manual.pdf [MCS 6500 Microcomputer Family Programming Manual, January 1976]
|
||||
ADC, 205
|
||||
AND, 205
|
||||
ASL, 206
|
||||
BCC, 206
|
||||
BCS, 207
|
||||
BEQ, 207
|
||||
BIT, 208
|
||||
BMI, 208
|
||||
BNE, 209
|
||||
BPL, 209
|
||||
BRK, 210
|
||||
BVC, 210
|
||||
BVS, 211
|
||||
CLC, 211
|
||||
CLD, 212
|
||||
CLI, 212
|
||||
CLV, 213
|
||||
CMP, 213
|
||||
CPX, 214
|
||||
CPY, 214
|
||||
DEC, 215
|
||||
DEX, 215
|
||||
DEY, 216
|
||||
EOR, 216
|
||||
INC, 217
|
||||
INX, 217
|
||||
INY, 218
|
||||
JMP, 218
|
||||
JSR, 219
|
||||
LDA, 219
|
||||
LDX, 220
|
||||
LDY, 220
|
||||
LSR, 221
|
||||
NOP, 221
|
||||
ORA, 222
|
||||
PHA, 222
|
||||
PHP, 223
|
||||
PLA, 223
|
||||
PLP, 224
|
||||
ROL, 224
|
||||
ROR, 225
|
||||
RTI, 225
|
||||
RTS, 225
|
||||
SBC, 226
|
||||
SEC, 226
|
||||
SED, 227
|
||||
SEI, 227
|
||||
STA, 228
|
||||
STX, 228
|
||||
STY, 229
|
||||
TAX, 229
|
||||
TAY, 230
|
||||
TSX, 231
|
||||
TXA, 231
|
||||
TXS, 231
|
||||
TYA, 230
|
||||
Reference in New Issue
Block a user