From 7a8a9534ee2ed1d768e89fc9612bb03aa04301e3 Mon Sep 17 00:00:00 2001
From: Alexey Esaulenko <esaulenka@gmail.com>
Date: Sun, 14 Mar 2021 23:10:28 +0300
Subject: [PATCH] PowerPC: additional MPC55xx float-point instructions

---
 .../Processors/PowerPC/certification.manifest |   1 +
 .../data/languages/SPE_FloatMulAdd.sinc       | 101 ++++++++++++++++++
 .../data/languages/ppc_64_isa_vle_be.slaspec  |   1 +
 3 files changed, 103 insertions(+)
 create mode 100644 Ghidra/Processors/PowerPC/data/languages/SPE_FloatMulAdd.sinc

diff --git a/Ghidra/Processors/PowerPC/certification.manifest b/Ghidra/Processors/PowerPC/certification.manifest
index ad290208f0..d97e6d9b66 100644
--- a/Ghidra/Processors/PowerPC/certification.manifest
+++ b/Ghidra/Processors/PowerPC/certification.manifest
@@ -7,6 +7,7 @@ data/languages/SPEF_SCR.sinc||GHIDRA||||END|
 data/languages/SPE_APU.sinc||GHIDRA||||END|
 data/languages/SPE_EFSD.sinc||GHIDRA||||END|
 data/languages/SPE_EFV.sinc||GHIDRA||||END|
+data/languages/SPE_FloatMulAdd.sinc||GHIDRA||||END|
 data/languages/Scalar_SPFP.sinc||GHIDRA||||END|
 data/languages/altivec.sinc||GHIDRA||||END|
 data/languages/evx.sinc||GHIDRA||||END|
diff --git a/Ghidra/Processors/PowerPC/data/languages/SPE_FloatMulAdd.sinc b/Ghidra/Processors/PowerPC/data/languages/SPE_FloatMulAdd.sinc
new file mode 100644
index 0000000000..cecabd8e83
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/SPE_FloatMulAdd.sinc
@@ -0,0 +1,101 @@
+
+# Additional SPE Instructions for Devices that Support VLE
+# Freescale engineering bulletin EB689
+# https://www.nxp.com/docs/en/engineering-bulletin/EB689.pdf
+
+# additional SPE instructions that are implemented on devices with an e200z3 or e200z6 core that supports VLE
+# - Vector Floating-Point Single-Precision Multiply-Add
+# - Vector Floating-Point Single-Precision Multiply-Substract
+# - Vector Floating-Point Single-Precision Negative Multiply-Add
+# - Vector Floating-Point Single-Precision Negative Multiply-Substract
+# - Floating-Point Single-Precision Multiply-Add
+# - Floating-Point Single-Precision Multiply-Substract
+# - Floating-Point Single-Precision Negative Multiply-Add
+# - Floating-Point Single-Precision Negative Multiply-Substract
+
+
+
+# evfsmadd rD,rA,rB
+# Vector Floating-Point Single-Precision Multiply-Add
+:evfsmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x282
+{
+	local tmpAL:4 = A:4; local tmpAH:4 = A(4);
+	local tmpBL:4 = B:4; local tmpBH:4 = B(4);
+	local tmpDL:4 = D:4; local tmpDH:4 = D(4);
+
+	tmpDL = ((tmpAL f* tmpBL) f+ tmpDL);
+	tmpDH = ((tmpAH f* tmpBH) f+ tmpDH);
+	D = (zext(tmpDH) << 32) | zext(tmpDL);
+}
+
+# evfsmsub rD,rA,rB
+# Vector Floating-Point Single-Precision Multiply-Substract
+:evfsmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x283
+{
+	local tmpAL:4 = A:4; local tmpAH:4 = A(4);
+	local tmpBL:4 = B:4; local tmpBH:4 = B(4);
+	local tmpDL:4 = D:4; local tmpDH:4 = D(4);
+
+	tmpDL = ((tmpAL f* tmpBL) f- tmpDL);
+	tmpDH = ((tmpAH f* tmpBH) f- tmpDH);
+	D = (zext(tmpDH) << 32) | zext(tmpDL);
+}
+
+# evfsnmadd
+# Vector Floating-Point Single-Precision Negative Multiply-Add
+:evfsnmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x28A
+{
+	local tmpAL:4 = A:4; local tmpAH:4 = A(4);
+	local tmpBL:4 = B:4; local tmpBH:4 = B(4);
+	local tmpDL:4 = D:4; local tmpDH:4 = D(4);
+
+	tmpDL = f- ((tmpAL f* tmpBL) f+ tmpDL);
+	tmpDH = f- ((tmpAH f* tmpBH) f+ tmpDH);
+	D = (zext(tmpDH) << 32) | zext(tmpDL);
+}
+
+# evfsnmsub
+# Vector Floating-Point Single-Precision Negative Multiply-Substract
+:evfsnmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x28B
+{
+	local tmpAL:4 = A:4; local tmpAH:4 = A(4);
+	local tmpBL:4 = B:4; local tmpBH:4 = B(4);
+	local tmpDL:4 = D:4; local tmpDH:4 = D(4);
+
+	tmpDL = f- ((tmpAL f* tmpBL) f- tmpDL);
+	tmpDH = f- ((tmpAH f* tmpBH) f- tmpDH);
+	D = (zext(tmpDH) << 32) | zext(tmpDL);
+}
+
+# efsmadd rD,rA,rB
+# Floating-Point Single-Precision Multiply-Add
+:efsmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C2
+{
+	local lo:4 = (A:4 f* B:4) f+ D:4;
+	D = (D & 0xFFFFFFFF00000000) | zext(lo);
+}
+
+# efsmsub rD,rA,rB
+# Floating-Point Single-Precision Multiply-Substract
+:efsmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C3
+{
+	local lo:4 = (A:4 f* B:4) f- D:4;
+	D = (D & 0xFFFFFFFF00000000) | zext(lo);
+}
+
+# efsnmadd rD,rA,rB
+# Floating-Point Single-Precision Negative Multiply-Add
+:efsnmadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2CA
+{
+	local lo:4 = f- ((A:4 f* B:4) f+ D:4);
+	D = (D & 0xFFFFFFFF00000000) | zext(lo);
+}
+
+# efsnmsub rD,rA,rB
+# Floating-Point Single-Precision Negative Multiply-Substract
+:efsnmsub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2CB
+{
+	local lo:4 = f- ((A:4 f* B:4) f- D:4);
+	D = (D & 0xFFFFFFFF00000000) | zext(lo);
+}
+
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec
index 8a81dc5fec..06e22cb5ca 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec
@@ -30,5 +30,6 @@
 @include "SPEF_SCR.sinc"
 @include "SPE_EFSD.sinc"
 @include "SPE_EFV.sinc"
+@include "SPE_FloatMulAdd.sinc"
 # OR
 #@include "altivec.sinc"