From 9be2a25cdb42d417879546e4a2ff6df4eeb5e6cb Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 6 Feb 2023 16:57:54 +0000 Subject: [PATCH 1/2] GP-3078: Corrected x86-64 mov offset instruction variant --- Ghidra/Processors/x86/data/languages/ia.sinc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index ca9a1a90af..e54fad29dd 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -936,6 +936,8 @@ moffs32: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 @ifdef IA64 moffs64: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:8 imm64; } moffs64: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:8 tmp; } +moffs64: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:8 imm32; } +moffs64: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:8 = segWide + imm32; export *:8 tmp; } @endif # TODO: segment register offset in 64bit might not be right From 34d080f933921ceab38186943d4ec8274db5ae59 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 6 Feb 2023 18:00:43 +0000 Subject: [PATCH 2/2] GP-3079: Corrected pcode for x86 fbld instruction --- Ghidra/Processors/x86/data/languages/ia.sinc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index ca9a1a90af..59aa59621d 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -4071,9 +4071,10 @@ define pcodeop f2xm1; :FIADD spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=0 ... & spec_m32 { ST0 = ST0 f+ int2float(spec_m32); } :FIADD spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=0 ... & spec_m16 { ST0 = ST0 f+ int2float(spec_m16); } -:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { spec_m80 = ST0; fpop(); } +define pcodeop convert_bcd; +:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { fdec(); ST0 = convert_bcd(spec_m80); } -:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = ST0; fpop(); } +:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = convert_bcd(ST0); fpop(); } :FCHS is vexMode=0 & byte=0xD9; byte=0xE0 { ST0 = f- ST0; }