From ef6469d8cc497623f2aacdbce10cb25e576a02be Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 19 Dec 2023 10:23:06 +0800 Subject: [PATCH 1/2] GP-0 Add missing csr77 to LoongArch --- Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc index f44179a22e..1827d43817 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -143,7 +143,7 @@ define register offset=$(CSR_OFFSET) size=$(REGSIZE) [ save0 save1 save2 save3 save4 save5 save6 save7 save8 save9 save10 save11 save12 save13 save14 save15 tid tcfg tval cntc ticlr csr69 csr70 csr71 - csr72 csr73 csr74 csr75 csr76 csr78 csr79 + csr72 csr73 csr74 csr75 csr76 csr77 csr78 csr79 csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87 csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95 llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103 From 554b7f198e89f1018ed424d4499eda9a1247fe85 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 19 Dec 2023 10:23:31 +0800 Subject: [PATCH 2/2] GP-0 Fix csrxchg definition for LoongArch --- .../Loongarch/data/languages/loongarch32_instructions.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc index 9e7479d3f3..5d18bee31d 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc @@ -1154,8 +1154,8 @@ csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { :csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { local csrval:$(REGSIZE) = csr; local mask = RJsrc; - csr = RD & mask; - RD = csrval & mask; + csr = (RD & mask) | (csrval & ~mask); + RD = csrval; } :csrrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr {