diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/CharacterScriptUtils.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/CharacterScriptUtils.java
index e4ce602b85..5bfb23cc5b 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/CharacterScriptUtils.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/CharacterScriptUtils.java
@@ -29,9 +29,9 @@ public class CharacterScriptUtils {
 
 	/**
 	 * The {@link UnicodeScript} value that represents the "ANY" choice.  This is a bit of a hack
-	 * and re-uses the INHERITED enum value for this purpose.
+	 * and re-uses the enum value for this purpose.
 	 */
-	public static final UnicodeScript ANY_SCRIPT_ALIAS = UnicodeScript.INHERITED;
+	public static final UnicodeScript ANY_SCRIPT_ALIAS = UnicodeScript.UNKNOWN;
 
 	/**
 	 * Premade examples of characters from each specified script, using info from
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/EncodedStringsDialog.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/EncodedStringsDialog.java
index 560be1f79c..0c47de5707 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/EncodedStringsDialog.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/EncodedStringsDialog.java
@@ -1063,7 +1063,11 @@ public class EncodedStringsDialog extends DialogComponentProvider {
 
 	private ComboBoxModel<UnicodeScript> getScriptListModel(EncodedStringsFilterStats stats) {
 		List<UnicodeScript> scripts = new ArrayList<>(stats.foundScriptCounts.keySet());
-		Collections.sort(scripts, (us1, us2) -> us1.name().compareTo(us2.name()));
+		Collections.sort(scripts, (us1, us2) -> {
+			int us1Count = stats.foundScriptCounts.get(us1);
+			int us2Count = stats.foundScriptCounts.get(us2);
+			return Integer.compare(us2Count, us1Count); // descending
+		});
 		scripts.add(0, CharacterScriptUtils.ANY_SCRIPT_ALIAS);
 
 		return new DefaultComboBoxModel<>(new Vector<>(scripts));
diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/StringInfo.java b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/StringInfo.java
index 6a175c88aa..2dfb1b8f3f 100644
--- a/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/StringInfo.java
+++ b/Ghidra/Features/Base/src/main/java/ghidra/app/plugin/core/strings/StringInfo.java
@@ -48,7 +48,12 @@ public record StringInfo(
 		s.codePoints().forEach(codePoint -> {
 			try {
 				UnicodeScript script = Character.UnicodeScript.of(codePoint);
-				scripts.add(script);
+				if (script == UnicodeScript.UNKNOWN) {
+					features.add(StringInfoFeature.CODEC_ERROR); // TODO: are we mis-using this enum to signal bad character?
+				}
+				else {
+					scripts.add(script);
+				}
 
 				if (codePoint == StringUtilities.UNICODE_REPLACEMENT) {
 					features.add(StringInfoFeature.CODEC_ERROR);
diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc
index 9e7479d3f3..5d18bee31d 100644
--- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc
+++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc
@@ -1154,8 +1154,8 @@ csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] {
 :csrxchg  RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr {
 	local csrval:$(REGSIZE) = csr;
 	local mask = RJsrc;
-	csr = RD & mask;
-	RD = csrval & mask;
+	csr = (RD & mask) | (csrval & ~mask);
+	RD = csrval;
 }
 
 :csrrd  RD, csr is op24_31=0x4 & RD & op5_9=0 & csr {
diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc
index f44179a22e..1827d43817 100644
--- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc
+++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc
@@ -143,7 +143,7 @@ define register offset=$(CSR_OFFSET) size=$(REGSIZE) [
 	save0     save1     save2     save3     save4     save5     save6     save7
 	save8     save9     save10    save11    save12    save13    save14    save15
 	tid       tcfg      tval      cntc      ticlr     csr69     csr70     csr71
-	csr72     csr73     csr74     csr75     csr76     csr78     csr79
+	csr72     csr73     csr74     csr75     csr76     csr77	    csr78     csr79
 	csr80     csr81     csr82     csr83     csr84     csr85     csr86     csr87
 	csr88     csr89     csr90     csr91     csr92     csr93     csr94     csr95
 	llbctl    csr97     csr98     csr99     csr100    csr101    csr102    csr103
diff --git a/Ghidra/Processors/PowerPC/certification.manifest b/Ghidra/Processors/PowerPC/certification.manifest
index 6ccaccdc57..7734824f8b 100644
--- a/Ghidra/Processors/PowerPC/certification.manifest
+++ b/Ghidra/Processors/PowerPC/certification.manifest
@@ -14,6 +14,7 @@ data/languages/evx.sinc||GHIDRA||||END|
 data/languages/g2.sinc||GHIDRA||||END|
 data/languages/lmwInstructions.sinc||GHIDRA||||END|
 data/languages/lswInstructions.sinc||GHIDRA||||END|
+data/languages/mulhwInstructions.sinc||GHIDRA||||END|
 data/languages/old/oldPPC.lang||GHIDRA||||END|
 data/languages/old/oldPPC.trans||GHIDRA||||END|
 data/languages/ppc.dwarf||GHIDRA||||END|
diff --git a/Ghidra/Processors/PowerPC/data/languages/4xx.sinc b/Ghidra/Processors/PowerPC/data/languages/4xx.sinc
index 392e96c77b..be352d4023 100644
--- a/Ghidra/Processors/PowerPC/data/languages/4xx.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/4xx.sinc
@@ -5,3 +5,129 @@
     S = dataCacheRead(RA_OR_ZERO,B);
 }
 
+# ========================================================================
+
+# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
+# CMT: Determine Leftmost Zero Byte
+# FORM: X-form
+# binutils: 476.d: 1a4: 7c 83 28 9c     dlmzb   r3,r4,r5
+# binutils: titan.d: 158:       7c 22 00 9c     dlmzb   r2,r1,r0
+define pcodeop DetermineLeftmostZeroByte;
+:dlmzb  S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0 
+{
+   # search from left for the first occurrence of null byte
+
+   # low 32 bits of RS concatenated with low 32 bits of RB
+@ifdef BIT_64
+   tmpD:8 = zext( S:4 );
+@else
+   tmpD:8 = zext( S );
+@endif
+
+   tmpD = tmpD << 32;
+
+@ifdef BIT_64
+   tmpD = tmpD | zext( B:4 );
+@else
+   tmpD = tmpD | zext( B );
+@endif
+
+   tmpX:8 = 0;
+
+   <unmatched>
+
+   if ( tmpX == 8 ) goto <done_searching>;
+      tmpX = tmpX + 1;
+
+   if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
+
+   <done_searching>
+
+   # place byte number in register A and low 7 bits of XER
+@ifdef BIT_64
+   A = tmpX;
+   XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
+@else
+   A = tmpX:4;
+   XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
+@endif
+
+}
+
+# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
+# CMT: Determine Leftmost Zero Byte
+# FORM: X-form
+# binutils: 476.d: 1a8:     7c 83 28 9d     dlmzb\.  r3,r4,r5
+# binutils: titan.d: 15c:   7c 22 00 9d     dlmzb\.  r2,r1,r0
+define pcodeop  DetermineLeftmostZeroByte1;
+:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1 
+{
+   # search from left for the first occurrence of null byte
+
+   # low 32 bits of RS concatenated with low 32 bits of RB
+@ifdef BIT_64
+   tmpD:8 = zext( S:4 );
+@else
+   tmpD:8 = zext( S );
+@endif
+
+   tmpD = tmpD << 32;
+
+@ifdef BIT_64
+   tmpD = tmpD | zext( B:4 );
+@else
+   tmpD = tmpD | zext( B );
+@endif
+
+   tmpX:8 = 0;
+   tmpY:8 = 0;
+
+   <unmatched>
+
+   if ( tmpX == 8 ) goto <done_searching>;
+   tmpX = tmpX + 1;
+
+   if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
+
+   # matched
+   tmpY = 1;
+
+   <done_searching>
+
+   # place byte number in register A and low 7 bits of XER
+@ifdef BIT_64
+   A = tmpX;
+   XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
+@else
+   A = tmpX:4;
+   XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
+@endif
+
+   # Rc section
+
+   # Set bit 35 of CR to SO
+   cr0 = (cr0 & 0xe) | zext( xer_so & 1);
+
+
+   # Set bits 32:34 of CR
+   if ( tmpY != 1 ) goto <no_match>;
+
+   if ( tmpX >= 5 ) goto <high_bytes>;
+      cr0 = ( cr0 & 0x1 ) | 4;
+      goto <finished>;
+
+   <high_bytes>
+      cr0 =  ( cr0 & 0x1 ) | 8;
+      goto <finished>;
+
+   <no_match>
+      cr0 = ( cr0 & 0x1 ) | 2;
+   <finished>
+}
+
+#icread 0,r0           0x7c 00 07 cc
+:icread RA_OR_ZERO,B		is OP=31 & BITS_21_25=0 & B & XOP_1_10=998 & BIT_0=0 & RA_OR_ZERO
+{
+	ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
+	instructionCacheRead(ea);	
+}
\ No newline at end of file
diff --git a/Ghidra/Processors/PowerPC/data/languages/mulhwInstructions.sinc b/Ghidra/Processors/PowerPC/data/languages/mulhwInstructions.sinc
new file mode 100644
index 0000000000..6663f0ff67
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/mulhwInstructions.sinc
@@ -0,0 +1,583 @@
+#macchw r0,r0,r0	0x10 00 01 58
+:macchw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=0
+{
+        D = macchw(D, A, B);
+}
+
+#macchw. r0,r0,r0	0x10 00 01 59
+:macchw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=1
+{
+        D = macchw(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwo r0,r0,r0	0x10 00 05 58
+:macchwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=0
+{
+        D = macchw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#macchwo. r0,r0,r0	0x10 00 05 59
+:macchwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=1
+{
+        D = macchw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#macchws r0,r0,r0	0x10 00 01 d8
+:macchws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=0
+{
+        D = macchws(D, A, B);
+}
+
+#macchws. r0,r0,r0	0x10 00 01 d9
+:macchws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=1
+{
+        D = macchws(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwso r0,r0,r0	0x10 00 05 d8
+:macchwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=0
+{
+        D = macchws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#macchwso. r0,r0,r0	0x10 00 05 d9
+:macchwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1
+{
+        D = macchws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwsu r0,r0,r0	0x10 00 01 98
+:macchwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=0
+{
+        D = macchwsu(D, A, B);
+}
+
+#macchwsu. r0,r0,r0	0x10 00 01 99
+:macchwsu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=1
+{
+        D = macchwsu(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwsuo r0,r0,r0	0x10 00 05 98
+:macchwsuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=0
+{
+        D = macchwsu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#macchwsuo. r0,r0,r0	0x10 00 05 99
+:macchwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=1
+{
+        D = macchwsu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwu r0,r0,r0	0x10 00 01 18
+:macchwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=0
+{
+        D = macchwu(D, A, B);
+}
+
+#macchwu. r0,r0,r0	0x10 00 01 19
+:macchwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=1
+{
+        D = macchwu(D, A, B);
+	cr0flags(D);	
+}
+
+#macchwuo r0,r0,r0	0x10 00 05 18
+:macchwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=0
+{
+        D = macchwu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#macchwuo. r0,r0,r0	0x10 00 05 19
+:macchwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=1
+{
+        D = macchwu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+
+#machhw r0,r0,r0	0x10 00 00 58
+:machhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=0
+{
+        D = machhw(D, A, B);
+}
+
+#machhw. r0,r0,r0	0x10 00 00 59
+:machhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=1
+{
+        D = machhw(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwo r0,r0,r0	0x10 00 04 58
+:machhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=0
+{
+        D = machhw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#machhwo. r0,r0,r0	0x10 00 04 59
+:machhwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=1
+{
+        D = machhw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#machhws r0,r0,r0	0x10 00 00 d8
+:machhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=0
+{
+        D = machhws(D, A, B);
+}
+
+#machhws. r0,r0,r0	0x10 00 00 d9
+:machhws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=1
+{
+        D = machhws(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwso r0,r0,r0	0x10 00 04 d8
+:machhwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=0
+{
+        D = machhws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#machhwso. r0,r0,r0	0x10 00 04 d9
+:machhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=1
+{
+        D = machhws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwsu r0,r0,r0	0x10 00 00 98
+:machhwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=0
+{
+        D = machhwsu(D, A, B);
+}
+
+#machhwsu. r0,r0,r0	0x10 00 00 99
+:machhwsu. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=1
+{
+        D = machhwsu(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwsuo r0,r0,r0	0x10 00 04 98
+:machhwsuo D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=0
+{
+        D = machhwsu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#machhwsuo. r0,r0,r0	0x10 00 04 99
+:machhwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=1
+{
+        D = machhwsu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwu r0,r0,r0	0x10 00 00 18
+:machhwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=0
+{
+        D = machhwu(D, A, B);
+}
+
+#machhwu. r0,r0,r0	0x10 00 00 19
+:machhwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=1
+{
+        D = machhwu(D, A, B);
+	cr0flags(D);	
+}
+
+#machhwuo r0,r0,r0	0x10 00 04 18
+:machhwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=0
+{
+        D = machhwu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#machhwuo. r0,r0,r0	0x10 00 04 19
+:machhwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=1
+{
+        D = machhwu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+
+#maclhw r0,r0,r0	0x10 00 03 58
+:maclhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=0
+{
+        D = maclhw(D, A, B);
+}
+
+#maclhw. r0,r0,r0	0x10 00 03 59
+:maclhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=1
+{
+        D = maclhw(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwo r0,r0,r0	0x10 00 07 58
+:maclhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=0
+{
+        D = maclhw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#maclhwo. r0,r0,r0	0x10 00 07 59
+:maclhwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=1
+{
+        D = maclhw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhws r0,r0,r0	0x10 00 03 d8
+:maclhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=0
+{
+        D = maclhws(D, A, B);
+}
+
+#maclhws. r0,r0,r0	0x10 00 03 d9
+:maclhws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=1
+{
+        D = maclhws(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwso r0,r0,r0	0x10 00 07 d8
+:maclhwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=0
+{
+        D = maclhws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#maclhwso. r0,r0,r0	0x10 00 07 d9
+:maclhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=1
+{
+        D = maclhws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwsu r0,r0,r0	0x10 00 03 98
+:maclhwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=0
+{
+        D = maclhwsu(D, A, B);
+}
+
+#maclhwsu. r0,r0,r0	0x10 00 03 99
+:maclhwsu. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=1
+{
+        D = maclhwsu(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwsuo r0,r0,r0	0x10 00 07 98
+:maclhwsuo D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=0
+{
+        D = maclhwsu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#maclhwsuo. r0,r0,r0	0x10 00 07 99
+:maclhwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=1
+{
+        D = maclhwsu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwu r0,r0,r0	0x10 00 03 18
+:maclhwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=0
+{
+        D = maclhwu(D, A, B);
+}
+
+#maclhwu. r0,r0,r0	0x10 00 03 19
+:maclhwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=1
+{
+        D = maclhwu(D, A, B);
+	cr0flags(D);	
+}
+
+#maclhwuo r0,r0,r0	0x10 00 07 18
+:maclhwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=0
+{
+        D = maclhwu(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#maclhwuo. r0,r0,r0	0x10 00 07 19
+:maclhwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=1
+{
+        D = maclhwu(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#mulchw r0,r0,r0	0x10 00 01 50
+:mulchw D,A,B		is OP=4 & D & A & B & XOP_1_10=168 & Rc=0
+{
+        D = mulchw(D, A, B);
+}
+
+#mulchw. r0,r0,r0	0x10 00 01 51
+:mulchw. D,A,B		is OP=4 & D & A & B & XOP_1_10=168 & Rc=1
+{
+        D = mulchw(D, A, B);
+	cr0flags(D);	
+}
+
+#mulchwu r0,r0,r0	0x10 00 01 10
+:mulchwu D,A,B		is OP=4 & D & A & B & XOP_1_10=136 & Rc=0
+{
+        D = mulchwu(D, A, B);
+}
+
+#mulchwu. r0,r0,r0	0x10 00 01 11
+:mulchwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=136 & Rc=1
+{
+        D = mulchwu(D, A, B);
+	cr0flags(D);	
+}
+
+#mulhhw r0,r0,r0	0x10 00 00 50
+:mulhhw D,A,B		is OP=4 & D & A & B & XOP_1_10=40 & Rc=0
+{
+        D = mulhhw(D, A, B);
+}
+
+#mulhhw. r0,r0,r0	0x10 00 00 51
+:mulhhw. D,A,B		is OP=4 & D & A & B & XOP_1_10=40 & Rc=1
+{
+        D = mulhhw(D, A, B);
+	cr0flags(D);	
+}
+
+#mulhhwu r0,r0,r0	0x10 00 00 10
+:mulhhwu D,A,B		is OP=4 & D & A & B & XOP_1_10=8 & Rc=0
+{
+        D = mulhhwu(D, A, B);
+}
+
+#mulhhwu. r0,r0,r0	0x10 00 00 11
+:mulhhwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=8 & Rc=1
+{
+        D = mulhhwu(D, A, B);
+	cr0flags(D);	
+}
+
+#mullhw r0,r0,r0	0x10 00 03 50
+:mullhw D,A,B		is OP=4 & D & A & B & XOP_1_10=424 & Rc=0
+{
+        D = mullhw(D, A, B);
+}
+
+#mullhw. r0,r0,r0	0x10 00 03 51
+:mullhw. D,A,B		is OP=4 & D & A & B & XOP_1_10=424 & Rc=1
+{
+        D = mullhw(D, A, B);
+	cr0flags(D);	
+}
+
+# mulhwu r0,r0,r0	0x10 00 03 10
+:mullhwu D,A,B		is OP=4 & D & A & B & XOP_1_10=392 & Rc=0
+{
+		D = mullhwu(D, A, B);
+}
+
+#mullhwu. r0,r0,r0	0x10 00 03 11
+:mullhwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=392 & Rc=1
+{
+        D = mullhwu(D, A, B);
+	cr0flags(D);	
+}
+
+#nmacchw r0,r0,r0	0x10 00 01 5c
+:nmacchw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=0
+{
+        D = nmacchw(D, A, B);
+}
+
+#nmacchw. r0,r0,r0	0x10 00 01 5d
+:nmacchw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=1
+{
+        D = nmacchw(D, A, B);
+	cr0flags(D);	
+}
+
+#nmacchwo r0,r0,r0	0x10 00 05 5c
+:nmacchwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=0
+{
+        D = nmacchw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmacchwo. r0,r0,r0	0x10 00 05 5d
+:nmacchwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=1
+{
+        D = nmacchw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#nmacchws r0,r0,r0	0x10 00 01 dc
+:nmacchws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=0
+{
+        D = nmacchws(D, A, B);
+}
+
+#nmacchws. r0,r0,r0	0x10 00 01 dd
+:nmacchws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=1
+{
+        D = nmacchws(D, A, B);
+	cr0flags(D);	
+}
+
+#nmacchwso r0,r0,r0	0x10 00 05 dc
+:nmacchwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=0
+{
+        D = nmacchws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmacchwso. r0,r0,r0	0x10 00 05 dd
+:nmacchwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=1
+{
+        D = nmacchws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#nmachhw r0,r0,r0	0x10 00 00 5c
+:nmachhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=0
+{
+        D = nmachhw(D, A, B);
+}
+
+#nmachhw. r0,r0,r0	0x10 00 00 5d
+:nmachhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=1
+{
+        D = nmachhw(D, A, B);
+	cr0flags(D);	
+}
+
+#nmachhwo r0,r0,r0	0x10 00 04 5c
+:nmachhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=0
+{
+        D = nmachhw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmachhwo. r0,r0,r0	0x10 00 04 5d
+:nmachhwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=1
+{
+        D = nmachhw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#nmachhws r0,r0,r0	0x10 00 00 dc
+:nmachhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=0
+{
+        D = nmachhws(D, A, B);
+}
+
+#nmachhws. r0,r0,r0	0x10 00 00 dd
+:nmachhws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=1
+{
+        D = nmachhws(D, A, B);
+	cr0flags(D);	
+}
+
+#nmachhwso r0,r0,r0	0x10 00 04 dc
+:nmachhwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=0
+{
+        D = nmachhws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmachhwso. r0,r0,r0	0x10 00 04 dd
+:nmachhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=1
+{
+        D = nmachhws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#nmaclhw r0,r0,r0	0x10 00 03 5c
+:nmaclhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=0
+{
+        D = nmaclhw(D, A, B);
+}
+
+#nmaclhw. r0,r0,r0	0x10 00 03 5d
+:nmaclhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=1
+{
+        D = nmaclhw(D, A, B);
+	cr0flags(D);	
+}
+
+#nmaclhwo r0,r0,r0	0x10 00 07 5c
+:nmaclhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=0
+{
+        D = nmaclhw(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmaclhwo. r0,r0,r0	0x10 00 07 5d
+:nmaclhwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=1
+{
+        D = nmaclhw(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
+
+#nmaclhws r0,r0,r0	0x10 00 03 dc
+:nmaclhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=0
+{
+        D = nmaclhws(D, A, B);
+}
+
+#nmaclhws. r0,r0,r0	0x10 00 03 dd
+:nmaclhws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=1
+{
+        D = nmaclhws(D, A, B);
+	cr0flags(D);	
+}
+
+#nmaclhwso r0,r0,r0	0x10 00 07 dc
+:nmaclhwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=0
+{
+        D = nmaclhws(D, A, B);
+        xer_mac_update(D, A, B);
+}
+
+#nmaclhwso. r0,r0,r0	0x10 00 07 dd
+:nmaclhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=1
+{
+        D = nmaclhws(D, A, B);
+        xer_mac_update(D, A, B);
+	cr0flags(D);	
+}
\ No newline at end of file
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
index abaf61fa89..f61ea275e1 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
@@ -5,7 +5,7 @@
             endian="big"
             size="32"
             variant="default"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_be.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -21,7 +21,7 @@
             endian="little"
             size="32"
             variant="default"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_le.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -37,7 +37,7 @@
             endian="big"
             size="64"
             variant="default"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -53,7 +53,7 @@
             endian="big"
             size="32"
             variant="64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -69,7 +69,7 @@
             endian="little"
             size="32"
             variant="64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_le.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -86,7 +86,7 @@
             endian="little"
             size="64"
             variant="default"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_le.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -101,7 +101,7 @@
             endian="big"
             size="32"
             variant="4xx"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_4xx_be.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -116,7 +116,7 @@
             endian="little"
             size="32"
             variant="4xx"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_4xx_le.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -132,7 +132,7 @@
             endian="big"
             size="32"
             variant="MPC8270"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_quicciii_be.sla"
             processorspec="ppc_32_mpc8270.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -147,7 +147,7 @@
             endian="big"
             size="32"
             variant="PowerQUICC-III"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_quicciii_be.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -162,7 +162,7 @@
             endian="little"
             size="32"
             variant="PowerQUICC-III"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_quicciii_le.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -178,7 +178,7 @@
             endian="big"
             size="32"
             variant="PowerQUICC-III-e500"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_e500_be.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -194,7 +194,7 @@
             endian="little"
             size="32"
             variant="PowerQUICC-III-e500"
-            version="1.5"
+            version="1.6"
             slafile="ppc_32_e500_le.sla"
             processorspec="ppc_32.pspec"
             manualindexfile="../manuals/PowerPC.idx"
@@ -240,7 +240,7 @@
             endian="big"
             size="32"
             variant="PowerISA-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -256,7 +256,7 @@
             endian="little"
             size="32"
             variant="PowerISA-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_le.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -273,7 +273,7 @@
             endian="big"
             size="32"
             variant="PowerISA-Altivec-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_altivec_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -289,7 +289,7 @@
             endian="little"
             size="32"
             variant="PowerISA-Altivec-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_altivec_le.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -306,7 +306,7 @@
             endian="big"
             size="64"
             variant="PowerISA-Altivec"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_altivec_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -321,7 +321,7 @@
             endian="little"
             size="64"
             variant="PowerISA-Altivec"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_altivec_le.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -336,7 +336,7 @@
             endian="big"
             size="32"
             variant="PowerISA-VLE-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_vle_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
@@ -351,7 +351,7 @@
             endian="big"
             size="32"
             variant="PowerISA-VLE-Altivec-64-32addr"
-            version="1.5"
+            version="1.6"
             slafile="ppc_64_isa_altivec_vle_be.sla"
             processorspec="ppc_64.pspec"
             manualindexfile="../manuals/PowerISA.idx"
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
index 0c41fa70a7..4b1e5e1a05 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
@@ -2053,13 +2053,6 @@
 }
 @endif
 
-#icread 0,r0           0x7c 00 07 cc
-:icread RA_OR_ZERO,B		is OP=31 & BITS_21_25=0 & B & XOP_1_10=998 & BIT_0=0 & RA_OR_ZERO
-{
-	ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
-	instructionCacheRead(ea);	
-}
-
 #lbz	r0,3(0)		0x88 00 00 03
 #lbz	r0,3(r2)	0x88 02 00 03
 :lbz	D,dPlusRaOrZeroAddress	is $(NOTVLE) & OP=34 & D & dPlusRaOrZeroAddress
@@ -2350,608 +2343,11 @@ define pcodeop lswxOp;
 @endif
 }
 
-#macchw r0,r0,r0	0x10 00 01 58
-:macchw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=0
-{
-        D = macchw(D, A, B);
-}
-
-#macchw. r0,r0,r0	0x10 00 01 59
-:macchw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=1
-{
-        D = macchw(D, A, B);
-	cr0flags(D);	
-}
-
-#macchwo r0,r0,r0	0x10 00 05 58
-:macchwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=0
-{
-        D = macchw(D, A, B);
-        xer_mac_update(D, A, B);
-}
 
 @ifndef NoLegacyIntegerMultiplyAccumulate
-#macchwo. r0,r0,r0	0x10 00 05 59
-:macchwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=1
-{
-        D = macchw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
+@include "mulhwInstructions.sinc"
 @endif
 
-#macchws r0,r0,r0	0x10 00 01 d8
-:macchws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=0
-{
-        D = macchws(D, A, B);
-}
-
-#macchws. r0,r0,r0	0x10 00 01 d9
-:macchws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=1
-{
-        D = macchws(D, A, B);
-	cr0flags(D);	
-}
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#macchwso r0,r0,r0	0x10 00 05 d8
-:macchwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=0
-{
-        D = macchws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-@endif
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#macchwso. r0,r0,r0	0x10 00 05 d9
-:macchwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1
-{
-        D = macchws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-@endif
-
-#macchwsu r0,r0,r0	0x10 00 01 98
-:macchwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=0
-{
-        D = macchwsu(D, A, B);
-}
-
-#macchwsu. r0,r0,r0	0x10 00 01 99
-:macchwsu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=1
-{
-        D = macchwsu(D, A, B);
-	cr0flags(D);	
-}
-
-#macchwsuo r0,r0,r0	0x10 00 05 98
-:macchwsuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=0
-{
-        D = macchwsu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#macchwsuo. r0,r0,r0	0x10 00 05 99
-:macchwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=1
-{
-        D = macchwsu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#macchwu r0,r0,r0	0x10 00 01 18
-:macchwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=0
-{
-        D = macchwu(D, A, B);
-}
-
-#macchwu. r0,r0,r0	0x10 00 01 19
-:macchwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=1
-{
-        D = macchwu(D, A, B);
-	cr0flags(D);	
-}
-
-#macchwuo r0,r0,r0	0x10 00 05 18
-:macchwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=0
-{
-        D = macchwu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#macchwuo. r0,r0,r0	0x10 00 05 19
-:macchwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=1
-{
-        D = macchwu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-
-#machhw r0,r0,r0	0x10 00 00 58
-:machhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=0
-{
-        D = machhw(D, A, B);
-}
-
-#machhw. r0,r0,r0	0x10 00 00 59
-:machhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=1
-{
-        D = machhw(D, A, B);
-	cr0flags(D);	
-}
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#machhwo r0,r0,r0	0x10 00 04 58
-:machhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=0
-{
-        D = machhw(D, A, B);
-        xer_mac_update(D, A, B);
-}
-@endif
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#machhwo. r0,r0,r0	0x10 00 04 59
-:machhwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=1
-{
-        D = machhw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-@endif
-
-#machhws r0,r0,r0	0x10 00 00 d8
-:machhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=0
-{
-        D = machhws(D, A, B);
-}
-
-#machhws. r0,r0,r0	0x10 00 00 d9
-:machhws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=1
-{
-        D = machhws(D, A, B);
-	cr0flags(D);	
-}
-
-#machhwso r0,r0,r0	0x10 00 04 d8
-:machhwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=0
-{
-        D = machhws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#machhwso. r0,r0,r0	0x10 00 04 d9
-:machhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=1
-{
-        D = machhws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#machhwsu r0,r0,r0	0x10 00 00 98
-:machhwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=0
-{
-        D = machhwsu(D, A, B);
-}
-
-#machhwsu. r0,r0,r0	0x10 00 00 99
-:machhwsu. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=1
-{
-        D = machhwsu(D, A, B);
-	cr0flags(D);	
-}
-
-#machhwsuo r0,r0,r0	0x10 00 04 98
-:machhwsuo D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=0
-{
-        D = machhwsu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#machhwsuo. r0,r0,r0	0x10 00 04 99
-:machhwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=1
-{
-        D = machhwsu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#machhwu r0,r0,r0	0x10 00 00 18
-:machhwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=0
-{
-        D = machhwu(D, A, B);
-}
-
-#machhwu. r0,r0,r0	0x10 00 00 19
-:machhwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=1
-{
-        D = machhwu(D, A, B);
-	cr0flags(D);	
-}
-
-#machhwuo r0,r0,r0	0x10 00 04 18
-:machhwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=0
-{
-        D = machhwu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#machhwuo. r0,r0,r0	0x10 00 04 19
-:machhwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=1
-{
-        D = machhwu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-
-#maclhw r0,r0,r0	0x10 00 03 58
-:maclhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=0
-{
-        D = maclhw(D, A, B);
-}
-
-#maclhw. r0,r0,r0	0x10 00 03 59
-:maclhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=1
-{
-        D = maclhw(D, A, B);
-	cr0flags(D);	
-}
-
-#maclhwo r0,r0,r0	0x10 00 07 58
-:maclhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=0
-{
-        D = maclhw(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#maclhwo. r0,r0,r0	0x10 00 07 59
-:maclhwo. D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=1
-{
-        D = maclhw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#maclhws r0,r0,r0	0x10 00 03 d8
-:maclhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=0
-{
-        D = maclhws(D, A, B);
-}
-
-#maclhws. r0,r0,r0	0x10 00 03 d9
-:maclhws. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=1
-{
-        D = maclhws(D, A, B);
-	cr0flags(D);	
-}
-
-#maclhwso r0,r0,r0	0x10 00 07 d8
-:maclhwso D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=0
-{
-        D = maclhws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#maclhwso. r0,r0,r0	0x10 00 07 d9
-:maclhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=1
-{
-        D = maclhws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#maclhwsu r0,r0,r0	0x10 00 03 98
-:maclhwsu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=0
-{
-        D = maclhwsu(D, A, B);
-}
-
-#maclhwsu. r0,r0,r0	0x10 00 03 99
-:maclhwsu. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=1
-{
-        D = maclhwsu(D, A, B);
-	cr0flags(D);	
-}
-
-#maclhwsuo r0,r0,r0	0x10 00 07 98
-:maclhwsuo D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=0
-{
-        D = maclhwsu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#maclhwsuo. r0,r0,r0	0x10 00 07 99
-:maclhwsuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=1
-{
-        D = maclhwsu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#maclhwu r0,r0,r0	0x10 00 03 18
-:maclhwu D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=0
-{
-        D = maclhwu(D, A, B);
-}
-@endif
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#maclhwu. r0,r0,r0	0x10 00 03 19
-:maclhwu. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=1
-{
-        D = maclhwu(D, A, B);
-	cr0flags(D);	
-}
-@endif
-
-#maclhwuo r0,r0,r0	0x10 00 07 18
-:maclhwuo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=0
-{
-        D = maclhwu(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#maclhwuo. r0,r0,r0	0x10 00 07 19
-:maclhwuo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=1
-{
-        D = maclhwu(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#mulchw r0,r0,r0	0x10 00 01 50
-:mulchw D,A,B		is OP=4 & D & A & B & XOP_1_10=168 & Rc=0
-{
-        D = mulchw(D, A, B);
-}
-
-#mulchw. r0,r0,r0	0x10 00 01 51
-:mulchw. D,A,B		is OP=4 & D & A & B & XOP_1_10=168 & Rc=1
-{
-        D = mulchw(D, A, B);
-	cr0flags(D);	
-}
-
-#mulchwu r0,r0,r0	0x10 00 01 10
-:mulchwu D,A,B		is OP=4 & D & A & B & XOP_1_10=136 & Rc=0
-{
-        D = mulchwu(D, A, B);
-}
-
-#mulchwu. r0,r0,r0	0x10 00 01 11
-:mulchwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=136 & Rc=1
-{
-        D = mulchwu(D, A, B);
-	cr0flags(D);	
-}
-
-#mulhhw r0,r0,r0	0x10 00 00 50
-:mulhhw D,A,B		is OP=4 & D & A & B & XOP_1_10=40 & Rc=0
-{
-        D = mulhhw(D, A, B);
-}
-
-#mulhhw. r0,r0,r0	0x10 00 00 51
-:mulhhw. D,A,B		is OP=4 & D & A & B & XOP_1_10=40 & Rc=1
-{
-        D = mulhhw(D, A, B);
-	cr0flags(D);	
-}
-
-#mulhhwu r0,r0,r0	0x10 00 00 10
-:mulhhwu D,A,B		is OP=4 & D & A & B & XOP_1_10=8 & Rc=0
-{
-        D = mulhhwu(D, A, B);
-}
-
-#mulhhwu. r0,r0,r0	0x10 00 00 11
-:mulhhwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=8 & Rc=1
-{
-        D = mulhhwu(D, A, B);
-	cr0flags(D);	
-}
-
-#mullhw r0,r0,r0	0x10 00 03 50
-:mullhw D,A,B		is OP=4 & D & A & B & XOP_1_10=424 & Rc=0
-{
-        D = mullhw(D, A, B);
-}
-
-#mullhw. r0,r0,r0	0x10 00 03 51
-:mullhw. D,A,B		is OP=4 & D & A & B & XOP_1_10=424 & Rc=1
-{
-        D = mullhw(D, A, B);
-	cr0flags(D);	
-}
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-# mulhwu r0,r0,r0	0x10 00 03 10
-:mullhwu D,A,B		is OP=4 & D & A & B & XOP_1_10=392 & Rc=0
-{
-		D = mullhwu(D, A, B);
-}
-@endif
-
-@ifndef NoLegacyIntegerMultiplyAccumulate
-#mullhwu. r0,r0,r0	0x10 00 03 11
-:mullhwu. D,A,B		is OP=4 & D & A & B & XOP_1_10=392 & Rc=1
-{
-        D = mullhwu(D, A, B);
-	cr0flags(D);	
-}
-@endif
-
-#nmacchw r0,r0,r0	0x10 00 01 5c
-:nmacchw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=0
-{
-        D = nmacchw(D, A, B);
-}
-
-#nmacchw. r0,r0,r0	0x10 00 01 5d
-:nmacchw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=1
-{
-        D = nmacchw(D, A, B);
-	cr0flags(D);	
-}
-
-#nmacchwo r0,r0,r0	0x10 00 05 5c
-:nmacchwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=0
-{
-        D = nmacchw(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmacchwo. r0,r0,r0	0x10 00 05 5d
-:nmacchwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=1
-{
-        D = nmacchw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#nmacchws r0,r0,r0	0x10 00 01 dc
-:nmacchws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=0
-{
-        D = nmacchws(D, A, B);
-}
-
-#nmacchws. r0,r0,r0	0x10 00 01 dd
-:nmacchws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=1
-{
-        D = nmacchws(D, A, B);
-	cr0flags(D);	
-}
-
-#nmacchwso r0,r0,r0	0x10 00 05 dc
-:nmacchwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=0
-{
-        D = nmacchws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmacchwso. r0,r0,r0	0x10 00 05 dd
-:nmacchwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=1
-{
-        D = nmacchws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#nmachhw r0,r0,r0	0x10 00 00 5c
-:nmachhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=0
-{
-        D = nmachhw(D, A, B);
-}
-
-#nmachhw. r0,r0,r0	0x10 00 00 5d
-:nmachhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=1
-{
-        D = nmachhw(D, A, B);
-	cr0flags(D);	
-}
-
-#nmachhwo r0,r0,r0	0x10 00 04 5c
-:nmachhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=0
-{
-        D = nmachhw(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmachhwo. r0,r0,r0	0x10 00 04 5d
-:nmachhwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=1
-{
-        D = nmachhw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#nmachhws r0,r0,r0	0x10 00 00 dc
-:nmachhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=0
-{
-        D = nmachhws(D, A, B);
-}
-
-#nmachhws. r0,r0,r0	0x10 00 00 dd
-:nmachhws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=1
-{
-        D = nmachhws(D, A, B);
-	cr0flags(D);	
-}
-
-#nmachhwso r0,r0,r0	0x10 00 04 dc
-:nmachhwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=0
-{
-        D = nmachhws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmachhwso. r0,r0,r0	0x10 00 04 dd
-:nmachhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=1
-{
-        D = nmachhws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#nmaclhw r0,r0,r0	0x10 00 03 5c
-:nmaclhw D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=0
-{
-        D = nmaclhw(D, A, B);
-}
-
-#nmaclhw. r0,r0,r0	0x10 00 03 5d
-:nmaclhw. D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=1
-{
-        D = nmaclhw(D, A, B);
-	cr0flags(D);	
-}
-
-#nmaclhwo r0,r0,r0	0x10 00 07 5c
-:nmaclhwo D,A,B		is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=0
-{
-        D = nmaclhw(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmaclhwo. r0,r0,r0	0x10 00 07 5d
-:nmaclhwo. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=1
-{
-        D = nmaclhw(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
-#nmaclhws r0,r0,r0	0x10 00 03 dc
-:nmaclhws D,A,B		is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=0
-{
-        D = nmaclhws(D, A, B);
-}
-
-#nmaclhws. r0,r0,r0	0x10 00 03 dd
-:nmaclhws. D,A,B	is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=1
-{
-        D = nmaclhws(D, A, B);
-	cr0flags(D);	
-}
-
-#nmaclhwso r0,r0,r0	0x10 00 07 dc
-:nmaclhwso D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=0
-{
-        D = nmaclhws(D, A, B);
-        xer_mac_update(D, A, B);
-}
-
-#nmaclhwso. r0,r0,r0	0x10 00 07 dd
-:nmaclhwso. D,A,B	is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=1
-{
-        D = nmaclhws(D, A, B);
-        xer_mac_update(D, A, B);
-	cr0flags(D);	
-}
-
 #mcrf cr0,cr0	0x4c 00 00 00
 :mcrf CRFD,CRFS		is $(NOTVLE) & OP=19 & CRFD & BITS_21_22=0 & CRFS & BITS_0_17=0 
 {
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
index 523ec943b2..ce9a52cc89 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
@@ -784,126 +784,6 @@ define pcodeop MoveFromDeviceControlRegisterUserModeIndexed;
 }
 
 
-# ========================================================================
-
-# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
-# CMT: Determine Leftmost Zero Byte
-# FORM: X-form
-# binutils: 476.d: 1a4: 7c 83 28 9c     dlmzb   r3,r4,r5
-# binutils: titan.d: 158:       7c 22 00 9c     dlmzb   r2,r1,r0
-define pcodeop DetermineLeftmostZeroByte;
-:dlmzb  S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0 
-{
-   # search from left for the first occurrence of null byte
-
-   # low 32 bits of RS concatenated with low 32 bits of RB
-@ifdef BIT_64
-   tmpD:8 = zext( S:4 );
-@else
-   tmpD:8 = zext( S );
-@endif
-
-   tmpD = tmpD << 32;
-
-@ifdef BIT_64
-   tmpD = tmpD | zext( B:4 );
-@else
-   tmpD = tmpD | zext( B );
-@endif
-
-   tmpX:8 = 0;
-
-   <unmatched>
-
-   if ( tmpX == 8 ) goto <done_searching>;
-      tmpX = tmpX + 1;
-
-   if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
-
-   <done_searching>
-
-   # place byte number in register A and low 7 bits of XER
-@ifdef BIT_64
-   A = tmpX;
-   XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
-@else
-   A = tmpX:4;
-   XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
-@endif
-
-}
-
-# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist]
-# CMT: Determine Leftmost Zero Byte
-# FORM: X-form
-# binutils: 476.d: 1a8:     7c 83 28 9d     dlmzb\.  r3,r4,r5
-# binutils: titan.d: 15c:   7c 22 00 9d     dlmzb\.  r2,r1,r0
-define pcodeop  DetermineLeftmostZeroByte1;
-:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1 
-{
-   # search from left for the first occurrence of null byte
-
-   # low 32 bits of RS concatenated with low 32 bits of RB
-@ifdef BIT_64
-   tmpD:8 = zext( S:4 );
-@else
-   tmpD:8 = zext( S );
-@endif
-
-   tmpD = tmpD << 32;
-
-@ifdef BIT_64
-   tmpD = tmpD | zext( B:4 );
-@else
-   tmpD = tmpD | zext( B );
-@endif
-
-   tmpX:8 = 0;
-   tmpY:8 = 0;
-
-   <unmatched>
-
-   if ( tmpX == 8 ) goto <done_searching>;
-   tmpX = tmpX + 1;
-
-   if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
-
-   # matched
-   tmpY = 1;
-
-   <done_searching>
-
-   # place byte number in register A and low 7 bits of XER
-@ifdef BIT_64
-   A = tmpX;
-   XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX;
-@else
-   A = tmpX:4;
-   XER = ( XER & 0xFFFFFF80 ) | tmpX:4;
-@endif
-
-   # Rc section
-
-   # Set bit 35 of CR to SO
-   cr0 = (cr0 & 0xe) | zext( xer_so & 1);
-
-
-   # Set bits 32:34 of CR
-   if ( tmpY != 1 ) goto <no_match>;
-
-   if ( tmpX >= 5 ) goto <high_bytes>;
-      cr0 = ( cr0 & 0x1 ) | 4;
-      goto <finished>;
-
-   <high_bytes>
-      cr0 =  ( cr0 & 0x1 ) | 8;
-      goto <finished>;
-
-   <no_match>
-      cr0 = ( cr0 & 0x1 ) | 2;
-   <finished>
-}
-
 # ========================================================================
 
 # PowerISA II: 4.6.5 Floating-Point Move Instructions