From 9be2a25cdb42d417879546e4a2ff6df4eeb5e6cb Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 6 Feb 2023 16:57:54 +0000 Subject: [PATCH] GP-3078: Corrected x86-64 mov offset instruction variant --- Ghidra/Processors/x86/data/languages/ia.sinc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index ca9a1a90af..e54fad29dd 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -936,6 +936,8 @@ moffs32: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 @ifdef IA64 moffs64: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:8 imm64; } moffs64: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:8 tmp; } +moffs64: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:8 imm32; } +moffs64: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:8 = segWide + imm32; export *:8 tmp; } @endif # TODO: segment register offset in 64bit might not be right