From 9d03c3a5f78557aeba64e12daf247bc4ad944176 Mon Sep 17 00:00:00 2001
From: mumbel <22204578+mumbel@users.noreply.github.com>
Date: Thu, 12 Sep 2019 17:30:40 -0500
Subject: [PATCH] se_cmpli fix

Previous attempt at se_cmpli fix incorrectly applied a 5 bit mask
OIMM = UI5_VLE + 1, resulting in values 1-32
---
 Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
index 6036b40fb9..ddba890258 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -591,7 +591,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 
 :se_cmpli RX_VLE,OIMM		is $(ISVLE) & OP6_VLE=8 & BIT9_VLE=1 & RX_VLE & OIMM {
 	tmpA:4 = RX_VLE:4;
-	tmpB:4 = OIMM:4 & 0x1f;
+	tmpB:4 = OIMM:4;
 	cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);			
 }