diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc index aff8f018f7..219eb5fbc5 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -14,7 +14,7 @@ # The RM field is bits 22 and 23 of FPSCR @define FPSCR_RMODE "fpscr[21,2]" -zero: "#0" is c0000 { tmp:8 = 0; export tmp; } +zero: "#0" is c0000 { export 0:8; } @if defined(SIMD) @@ -270,82 +270,82 @@ Sd2: Sd is Sd { export Sd; } @endif # VFPv2 || VFPv3 -udt: "s" is TMode=0 & c2424=0 { tmp:1 = 0; export tmp; } -udt: "u" is TMode=0 & c2424=1 { tmp:1 = 1; export tmp; } -udt: "s" is TMode=1 & thv_c2828=0 { tmp:1 = 0; export tmp; } -udt: "u" is TMode=1 & thv_c2828=1 { tmp:1 = 1; export tmp; } +udt: "s" is TMode=0 & c2424=0 { export 0:1; } +udt: "u" is TMode=0 & c2424=1 { export 1:1; } +udt: "s" is TMode=1 & thv_c2828=0 { export 0:1; } +udt: "u" is TMode=1 & thv_c2828=1 { export 1:1; } -udt7: "s" is TMode=0 & c0707=0 { tmp:1 = 0; export tmp; } -udt7: "u" is TMode=0 & c0707=1 { tmp:1 = 1; export tmp; } -udt7: "s" is TMode=1 & thv_c0707=0 { tmp:1 = 0; export tmp; } -udt7: "u" is TMode=1 & thv_c0707=1 { tmp:1 = 1; export tmp; } +udt7: "s" is TMode=0 & c0707=0 { export 0:1; } +udt7: "u" is TMode=0 & c0707=1 { export 1:1; } +udt7: "s" is TMode=1 & thv_c0707=0 { export 0:1; } +udt7: "u" is TMode=1 & thv_c0707=1 { export 1:1; } -fdt: "u" is TMode=0 & c0808=0 { tmp:1 = 0; export tmp; } -fdt: "f" is TMode=0 & c0808=1 { tmp:1 = 1; export tmp; } -fdt: "u" is TMode=1 & thv_c0808=0 { tmp:1 = 0; export tmp; } -fdt: "f" is TMode=1 & thv_c0808=1 { tmp:1 = 1; export tmp; } +fdt: "u" is TMode=0 & c0808=0 { export 0:1; } +fdt: "f" is TMode=0 & c0808=1 { export 1:1; } +fdt: "u" is TMode=1 & thv_c0808=0 { export 0:1; } +fdt: "f" is TMode=1 & thv_c0808=1 { export 1:1; } -esize2021: "8" is TMode=0 & c2021=0 { tmp:4 = 1; export tmp; } -esize2021: "16" is TMode=0 & c2021=1 { tmp:4 = 2; export tmp; } -esize2021: "32" is TMode=0 & c2021=2 { tmp:4 = 4; export tmp; } -esize2021: "64" is TMode=0 & c2021=3 { tmp:4 = 8; export tmp; } -esize2021: "8" is TMode=1 & thv_c2021=0 { tmp:4 = 1; export tmp; } -esize2021: "16" is TMode=1 & thv_c2021=1 { tmp:4 = 2; export tmp; } -esize2021: "32" is TMode=1 & thv_c2021=2 { tmp:4 = 4; export tmp; } -esize2021: "64" is TMode=1 & thv_c2021=3 { tmp:4 = 8; export tmp; } +esize2021: "8" is TMode=0 & c2021=0 { export 1:4; } +esize2021: "16" is TMode=0 & c2021=1 { export 2:4; } +esize2021: "32" is TMode=0 & c2021=2 { export 4:4; } +esize2021: "64" is TMode=0 & c2021=3 { export 8:4; } +esize2021: "8" is TMode=1 & thv_c2021=0 { export 1:4; } +esize2021: "16" is TMode=1 & thv_c2021=1 { export 2:4; } +esize2021: "32" is TMode=1 & thv_c2021=2 { export 4:4; } +esize2021: "64" is TMode=1 & thv_c2021=3 { export 8:4; } -esize2021x2: "16" is TMode=0 & c2021=0 { tmp:4 = 2; export tmp; } -esize2021x2: "32" is TMode=0 & c2021=1 { tmp:4 = 4; export tmp; } -esize2021x2: "64" is TMode=0 & c2021=2 { tmp:4 = 8; export tmp; } -esize2021x2: "16" is TMode=1 & thv_c2021=0 { tmp:4 = 2; export tmp; } -esize2021x2: "32" is TMode=1 & thv_c2021=1 { tmp:4 = 4; export tmp; } -esize2021x2: "64" is TMode=1 & thv_c2021=2 { tmp:4 = 8; export tmp; } +esize2021x2: "16" is TMode=0 & c2021=0 { export 2:4; } +esize2021x2: "32" is TMode=0 & c2021=1 { export 4:4; } +esize2021x2: "64" is TMode=0 & c2021=2 { export 8:4; } +esize2021x2: "16" is TMode=1 & thv_c2021=0 { export 2:4; } +esize2021x2: "32" is TMode=1 & thv_c2021=1 { export 4:4; } +esize2021x2: "64" is TMode=1 & thv_c2021=2 { export 8:4; } -esize1819: "8" is TMode=0 & c1819=0 { tmp:4 = 1; export tmp; } -esize1819: "16" is TMode=0 & c1819=1 { tmp:4 = 2; export tmp; } -esize1819: "32" is TMode=0 & c1819=2 { tmp:4 = 4; export tmp; } -esize1819: "64" is TMode=0 & c1819=3 { tmp:4 = 8; export tmp; } -esize1819: "8" is TMode=1 & thv_c1819=0 { tmp:4 = 1; export tmp; } -esize1819: "16" is TMode=1 & thv_c1819=1 { tmp:4 = 2; export tmp; } -esize1819: "32" is TMode=1 & thv_c1819=2 { tmp:4 = 4; export tmp; } -esize1819: "64" is TMode=1 & thv_c1819=3 { tmp:4 = 8; export tmp; } +esize1819: "8" is TMode=0 & c1819=0 { export 1:4; } +esize1819: "16" is TMode=0 & c1819=1 { export 2:4; } +esize1819: "32" is TMode=0 & c1819=2 { export 4:4; } +esize1819: "64" is TMode=0 & c1819=3 { export 8:4; } +esize1819: "8" is TMode=1 & thv_c1819=0 { export 1:4; } +esize1819: "16" is TMode=1 & thv_c1819=1 { export 2:4; } +esize1819: "32" is TMode=1 & thv_c1819=2 { export 4:4; } +esize1819: "64" is TMode=1 & thv_c1819=3 { export 8:4; } -esize1819x2: "16" is TMode=0 & c1819=0 { tmp:4 = 2; export tmp; } -esize1819x2: "32" is TMode=0 & c1819=1 { tmp:4 = 4; export tmp; } -esize1819x2: "64" is TMode=0 & c1819=2 { tmp:4 = 8; export tmp; } -esize1819x2: "16" is TMode=1 & thv_c1819=0 { tmp:4 = 2; export tmp; } -esize1819x2: "32" is TMode=1 & thv_c1819=1 { tmp:4 = 4; export tmp; } -esize1819x2: "64" is TMode=1 & thv_c1819=2 { tmp:4 = 8; export tmp; } +esize1819x2: "16" is TMode=0 & c1819=0 { export 2:4; } +esize1819x2: "32" is TMode=0 & c1819=1 { export 4:4; } +esize1819x2: "64" is TMode=0 & c1819=2 { export 8:4; } +esize1819x2: "16" is TMode=1 & thv_c1819=0 { export 2:4; } +esize1819x2: "32" is TMode=1 & thv_c1819=1 { export 4:4; } +esize1819x2: "64" is TMode=1 & thv_c1819=2 { export 8:4; } -esize1819x3: "8" is TMode=0 & c1819=0 { tmp:4 = 1; export tmp; } -esize1819x3: "16" is TMode=0 & c1819=1 { tmp:4 = 2; export tmp; } -esize1819x3: "32" is TMode=0 & c1819=2 { tmp:4 = 4; export tmp; } -esize1819x3: "8" is TMode=1 & thv_c1819=0 { tmp:4 = 1; export tmp; } -esize1819x3: "16" is TMode=1 & thv_c1819=1 { tmp:4 = 2; export tmp; } -esize1819x3: "32" is TMode=1 & thv_c1819=2 { tmp:4 = 4; export tmp; } +esize1819x3: "8" is TMode=0 & c1819=0 { export 1:4; } +esize1819x3: "16" is TMode=0 & c1819=1 { export 2:4; } +esize1819x3: "32" is TMode=0 & c1819=2 { export 4:4; } +esize1819x3: "8" is TMode=1 & thv_c1819=0 { export 1:4; } +esize1819x3: "16" is TMode=1 & thv_c1819=1 { export 2:4; } +esize1819x3: "32" is TMode=1 & thv_c1819=2 { export 4:4; } -esize1011: "8" is TMode=0 & c1011=0 { tmp:4 = 1; export tmp; } -esize1011: "16" is TMode=0 & c1011=1 { tmp:4 = 2; export tmp; } -esize1011: "32" is TMode=0 & c1011=2 { tmp:4 = 4; export tmp; } -esize1011: "64" is TMode=0 & c1011=3 { tmp:4 = 8; export tmp; } -esize1011: "8" is TMode=1 & thv_c1011=0 { tmp:4 = 1; export tmp; } -esize1011: "16" is TMode=1 & thv_c1011=1 { tmp:4 = 2; export tmp; } -esize1011: "32" is TMode=1 & thv_c1011=2 { tmp:4 = 4; export tmp; } -esize1011: "64" is TMode=1 & thv_c1011=3 { tmp:4 = 8; export tmp; } +esize1011: "8" is TMode=0 & c1011=0 { export 1:4; } +esize1011: "16" is TMode=0 & c1011=1 { export 2:4; } +esize1011: "32" is TMode=0 & c1011=2 { export 4:4; } +esize1011: "64" is TMode=0 & c1011=3 { export 8:4; } +esize1011: "8" is TMode=1 & thv_c1011=0 { export 1:4; } +esize1011: "16" is TMode=1 & thv_c1011=1 { export 2:4; } +esize1011: "32" is TMode=1 & thv_c1011=2 { export 4:4; } +esize1011: "64" is TMode=1 & thv_c1011=3 { export 8:4; } -esize0607: "8" is TMode=0 & c0607=0 { tmp:4 = 1; export tmp; } -esize0607: "16" is TMode=0 & c0607=1 { tmp:4 = 2; export tmp; } -esize0607: "32" is TMode=0 & c0607=2 { tmp:4 = 4; export tmp; } -esize0607: "64" is TMode=0 & c0607=3 { tmp:4 = 8; export tmp; } # see VLD4 (single 4-element structure to all lanes) -esize0607: "8" is TMode=1 & thv_c0607=0 { tmp:4 = 1; export tmp; } -esize0607: "16" is TMode=1 & thv_c0607=1 { tmp:4 = 2; export tmp; } -esize0607: "32" is TMode=1 & thv_c0607=2 { tmp:4 = 4; export tmp; } -esize0607: "64" is TMode=1 & thv_c0607=3 { tmp:4 = 8; export tmp; } # see VLD4 (single 4-element structure to all lanes) +esize0607: "8" is TMode=0 & c0607=0 { export 1:4; } +esize0607: "16" is TMode=0 & c0607=1 { export 2:4; } +esize0607: "32" is TMode=0 & c0607=2 { export 4:4; } +esize0607: "64" is TMode=0 & c0607=3 { export 8:4; } # see VLD4 (single 4-element structure to all lanes) +esize0607: "8" is TMode=1 & thv_c0607=0 { export 1:4; } +esize0607: "16" is TMode=1 & thv_c0607=1 { export 2:4; } +esize0607: "32" is TMode=1 & thv_c0607=2 { export 4:4; } +esize0607: "64" is TMode=1 & thv_c0607=3 { export 8:4; } # see VLD4 (single 4-element structure to all lanes) -fesize2021: "16" is TMode=0 & c2020=1 { tmp:4 = 4; export tmp; } -fesize2021: "32" is TMode=0 & c2020=0 { tmp:4 = 2; export tmp; } -fesize2021: "16" is TMode=1 & thv_c2020=1 { tmp:4 = 4; export tmp; } -fesize2021: "32" is TMode=1 & thv_c2020=0 { tmp:4 = 2; export tmp; } +fesize2021: "16" is TMode=0 & c2020=1 { export 4:4; } +fesize2021: "32" is TMode=0 & c2020=0 { export 2:4; } +fesize2021: "16" is TMode=1 & thv_c2020=1 { export 4:4; } +fesize2021: "32" is TMode=1 & thv_c2020=0 { export 2:4; } define pcodeop VFPExpandImmediate; @@ -1046,8 +1046,8 @@ macro FloatVectorCompare(op1,op2,nanx) { @if defined(VFPv2) || defined(VFPv3) -nanx: "e" is c0707=1 { tmp:1 = 1; export tmp; } -nanx: is c0707=0 { tmp:1 = 0; export tmp; } +nanx: "e" is c0707=1 { export 1:1; } +nanx: is c0707=0 { export 0:1; } :vcmp^nanx^COND^".f32" Sd,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1010 & c0606=1 & c0404=0) | ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1010 & thv_c0606=1 & thv_c0404=0) ) & Sd & nanx & Sm @@ -1183,9 +1183,9 @@ define pcodeop VectorUnsignedToFloat; # roundMode: "r" is TMode=0 & c0707=0 { tmp:1 = $(FPSCR_RMODE); export tmp; } -roundMode: is TMode=0 & c0707=1 { tmp:1 = 3; export tmp; } # Round towards zero +roundMode: is TMode=0 & c0707=1 { export 3:1; } # Round towards zero roundMode: "r" is TMode=1 & thv_c0707=0 { tmp:1 = $(FPSCR_RMODE); export tmp; } -roundMode: is TMode=1 & thv_c0707=1 { tmp:1 = 3; export tmp; } # Round towards zero +roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero :vcvt^roundMode^COND^".s32.f32" Sd,Sm is COND & ( ($(AMODE) & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | ($(TMODE_E) & thv_c2327=0x1b & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & Sd & Sm & roundMode @@ -1818,42 +1818,25 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } # VLD1 (multiple single elements) # -vld1Dd: Dreg is Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) +buildVld1DdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] { - replicate1to8(*:1 mult_addr, Dreg); + Dreg = * mult_addr; } -vld1Dd: Dreg is Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) +buildVld1DdList: Dreg,buildVld1DdList is Dreg & buildVld1DdList [ counter=counter-1; regNum=regNum+1; ] { - replicate2to8(*:2 mult_addr, Dreg); -} -vld1Dd: Dreg is Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) -{ - replicate4to8(*:4 mult_addr, Dreg); -} -vld1Dd: Dreg is Dreg & ((TMode=0 & c0607=3) | (TMode=1 & thv_c0607=3)) -{ - Dreg = *:8 mult_addr; -} - - - -buildVld1DdList: is counter=0 { } -buildVld1DdList: vld1Dd is vld1Dd & counter=1 [ counter=0; regNum=regNum+1; ] { } -buildVld1DdList: vld1Dd,buildVld1DdList is vld1Dd & buildVld1DdList & esize0607 [ counter=counter-1; regNum=regNum+1; ] -{ - build vld1Dd; - mult_addr = mult_addr + esize0607; + Dreg = * mult_addr; + mult_addr = mult_addr + 8; build buildVld1DdList; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=7 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=10 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=6 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { tmp:4 = 3; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=2 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { tmp:4 = 4; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { tmp:4 = 3; export tmp; } -vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { tmp:4 = 4; export tmp; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=7 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=10 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=6 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=2 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; } @define Vld1DdList "(c0811=2 | c0811=6 | c0811=7 | c0811=10)" @define thv_Vld1DdList "(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)" @@ -1991,8 +1974,8 @@ buildVld1DdList3: vld1Dd3,buildVld1DdList3 is vld1Dd3 & buildVld1DdList3 [ coun build buildVld1DdList3; } -vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } +vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } vld1Align3: is c0404=0 { } vld1Align3: "@16" is c0404=1 & c0607=1 { } @@ -2041,8 +2024,8 @@ thv_vld1RnReplicate: is VRn & thv_c0607=2 export val; } -thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } +thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } thv_vld1Align3: is thv_c0404=0 { } thv_vld1Align3: "@16" is thv_c0404=1 & thv_c0607=1 { } @@ -2151,12 +2134,12 @@ buildVld2DdListB: is counter2=0 { } buildVld2DdListB: Dreg2 is Dreg2 & counter2=1 & esize0607 [ counter2=0; reg2Num=reg2Num+1; ] { } buildVld2DdListB: Dreg2,buildVld2DdListB is Dreg2 & buildVld2DdListB & esize0607 [ counter2=counter2-1; reg2Num=reg2Num+1; ] { } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 2; export tmp; } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 2; export tmp; } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 4; export tmp; } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 2; export tmp; } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 2; export tmp; } -vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; tmp:4 = 4; export tmp; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; } @define Vld2DdList "(c0811=3 | c0811=8 | c0811=9)" @define thv_Vld2DdList "(thv_c0811=3 | thv_c0811=8 | thv_c0811=9)" @@ -2934,15 +2917,15 @@ define pcodeop VectorSetElement; @if defined(SIMD) -vmovSize: 8 is TMode=0 & c2222=1 { tmp:1 = 1; export tmp; } -vmovSize: 16 is TMode=0 & c2222=0 & c0505=1 { tmp:1 = 2; export tmp; } -vmovSize: 8 is TMode=1 & thv_c2222=1 { tmp:1 = 1; export tmp; } -vmovSize: 16 is TMode=1 & thv_c2222=0 & thv_c0505=1 { tmp:1 = 2; export tmp; } +vmovSize: 8 is TMode=0 & c2222=1 { export 1:1; } +vmovSize: 16 is TMode=0 & c2222=0 & c0505=1 { export 2:1; } +vmovSize: 8 is TMode=1 & thv_c2222=1 { export 1:1; } +vmovSize: 16 is TMode=1 & thv_c2222=0 & thv_c0505=1 { export 2:1; } @if defined(VFPv2) || defined(VFPv3) || defined(SIMD) -vmovSize: 32 is TMode=0 & c2222=0 & c0506=0 { tmp:1 = 4; export tmp; } -vmovSize: 32 is TMode=1 & thv_c2222=0 & thv_c0506=0 { tmp:1 = 4; export tmp; } +vmovSize: 32 is TMode=0 & c2222=0 & c0506=0 { export 4:1; } +vmovSize: 32 is TMode=1 & thv_c2222=0 & thv_c0506=0 { export 4:1; } @endif # VFPv2 || VFPv3 || SIMD @@ -3996,136 +3979,52 @@ define pcodeop VectorReciprocalSquareRootStep; # VST1 (multiple single elements) # -vst1Dd: Dreg is Dreg & c0607=0 +buildVst1DdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] { - local tmpDreg = Dreg; - local val:1 = tmpDreg:1; - local tmp8:8 = 0; - replicate1to8(val, tmp8); - *:8 mult_addr = tmp8; + * mult_addr = Dreg; } -vst1Dd: Dreg is Dreg & c0607=1 +buildVst1DdList: Dreg,buildVst1DdList is Dreg & buildVst1DdList [ counter=counter-1; regNum=regNum+1; ] { - local tmpDreg = Dreg; - local val:2 = tmpDreg:2; - local tmp8:8 = 0; - replicate2to8(val, tmp8); - *:8 mult_addr = tmp8; -} -vst1Dd: Dreg is Dreg & c0607=2 -{ - local tmpDreg = Dreg; - local val:4 = tmpDreg:4; - local tmp8:8 = 0; - replicate4to8(val, tmp8); - *:8 mult_addr = tmp8; -} -vst1Dd: Dreg is Dreg & c0607=3 -{ - *:8 mult_addr = Dreg; -} - -buildVst1DdList: is counter=0 { } -buildVst1DdList: vst1Dd is vst1Dd & counter=1 [ counter=0; regNum=regNum+1; ] { } -buildVst1DdList: vst1Dd,buildVst1DdList is vst1Dd & buildVst1DdList & esize0607 [ counter=counter-1; regNum=regNum+1; ] -{ - build vst1Dd; - mult_addr = mult_addr + esize0607; + * mult_addr = Dreg; + mult_addr = mult_addr + 8; build buildVst1DdList; } -vst1DdList: "{"^buildVst1DdList^"}" is c0811=7 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -vst1DdList: "{"^buildVst1DdList^"}" is c0811=10 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } -vst1DdList: "{"^buildVst1DdList^"}" is c0811=6 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { tmp:4 = 3; export tmp; } -vst1DdList: "{"^buildVst1DdList^"}" is c0811=2 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { tmp:4 = 4; export tmp; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=7 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=10 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=6 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=2 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; } -@define Vst1DdList "(c0811=2 | c0811=6 | c0811=7 | c0811=10) & vst1DdList" +@define Vst1DdList "(c0811=2 | c0811=6 | c0811=7 | c0811=10)" +@define T_Vst1DdList "(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)" -:vst1.^esize0607 vst1DdList,RnAligned45 is $(AMODE) & cond=15 & c2327=8 & c2021=0 & RnAligned45 & esize0607 & c0003=15 & $(Vst1DdList) +:vst1.^esize0607 vst1DdList,RnAligned45 is ( ($(AMODE) & cond=15 & c2327=8 & c2021=0 & c0003=15 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=15 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList { mult_addr = RnAligned45; build vst1DdList; } -:vst1.^esize0607 vst1DdList,RnAligned45^"!" is $(AMODE) & cond=15 & c2327=8 & c2021=0 & RnAligned45 & esize0607 & c0003=13 & $(Vst1DdList) +:vst1.^esize0607 vst1DdList,RnAligned45^"!" is ( ($(AMODE) & cond=15 & c2327=8 & c2021=0 & c0003=13 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=13 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList { mult_addr = RnAligned45; build vst1DdList; RnAligned45 = RnAligned45 + (8 * vst1DdList); } -:vst1.^esize0607 vst1DdList,RnAligned45,VRm is $(AMODE) & cond=15 & c2327=8 & c2021=0 & RnAligned45 & esize0607 & VRm & $(Vst1DdList) +:vst1.^esize0607 vst1DdList,RnAligned45,VRm is ( ($(AMODE) & cond=15 & c2327=8 & c2021=0 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & VRm & vst1DdList { mult_addr = RnAligned45; build vst1DdList; RnAligned45 = RnAligned45 + VRm; } -thv_vst1Dd: Dreg is Dreg & thv_c0607=0 -{ - local tmpDreg = Dreg; - local val:1 = tmpDreg:1; - local tmp8:8 = 0; - replicate1to8(val, tmp8); - *:8 mult_addr = tmp8; -} -thv_vst1Dd: Dreg is Dreg & thv_c0607=1 -{ - local tmpDreg = Dreg; - local val:2 = tmpDreg:2; - local tmp8:8 = 0; - replicate2to8(val, tmp8); - *:8 mult_addr = tmp8; -} -thv_vst1Dd: Dreg is Dreg & thv_c0607=2 -{ - local tmpDreg = Dreg; - local val:4 = tmpDreg:4; - local tmp8:8 = 0; - replicate4to8(val, tmp8); - *:8 mult_addr = tmp8; -} -thv_vst1Dd: Dreg is Dreg & thv_c0607=3 -{ - *:8 mult_addr = Dreg; -} - -thv_buildVst1DdList: is counter=0 { } -thv_buildVst1DdList: thv_vst1Dd is thv_vst1Dd & counter=1 [ counter=0; regNum=regNum+1; ] { } -thv_buildVst1DdList: thv_vst1Dd,thv_buildVst1DdList is thv_vst1Dd & thv_buildVst1DdList & esize0607 [ counter=counter-1; regNum=regNum+1; ] -{ - build thv_vst1Dd; - mult_addr = mult_addr + esize0607; - build thv_buildVst1DdList; -} - -thv_vst1DdList: "{"^thv_buildVst1DdList^"}" is thv_c0811=7 & thv_D22 & thv_c1215 & thv_buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { tmp:4 = 1; export tmp; } -thv_vst1DdList: "{"^thv_buildVst1DdList^"}" is thv_c0811=10 & thv_D22 & thv_c1215 & thv_buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { tmp:4 = 2; export tmp; } -thv_vst1DdList: "{"^thv_buildVst1DdList^"}" is thv_c0811=6 & thv_D22 & thv_c1215 & thv_buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { tmp:4 = 3; export tmp; } -thv_vst1DdList: "{"^thv_buildVst1DdList^"}" is thv_c0811=2 & thv_D22 & thv_c1215 & thv_buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { tmp:4 = 4; export tmp; } - -@define T_Vst1DdList "(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10) & thv_vst1DdList" - -:vst1.^esize0607 thv_vst1DdList,RnAligned45 is $(TMODE_F) &thv_c2327=18 & thv_c2021=0 & RnAligned45 & esize0607 & thv_c0003=15 & $(T_Vst1DdList) -{ - mult_addr = RnAligned45; - build thv_vst1DdList; -} - -:vst1.^esize0607 thv_vst1DdList,RnAligned45^"!" is $(TMODE_F) &thv_c2327=18 & thv_c2021=0 & RnAligned45 & esize0607 & thv_c0003=13 & $(T_Vst1DdList) -{ - mult_addr = RnAligned45; - build thv_vst1DdList; - RnAligned45 = RnAligned45 + (8 * thv_vst1DdList); -} - -:vst1.^esize0607 thv_vst1DdList,RnAligned45,VRm is $(TMODE_F) &thv_c2327=18 & thv_c2021=0 & RnAligned45 & esize0607 & VRm & $(T_Vst1DdList) -{ - mult_addr = RnAligned45; - build thv_vst1DdList; - RnAligned45 = RnAligned45 + VRm; -} - ####### # VST1 (single element to one lane) # @@ -4294,12 +4193,12 @@ buildVst2DdListB: is counter2=0 { } buildVst2DdListB: Dreg2 is Dreg2 & counter2=1 & esize0607 [ counter2=0; reg2Num=reg2Num+1; ] { } buildVst2DdListB: Dreg2,buildVst2DdListB is Dreg2 & buildVst2DdListB & esize0607 [ counter2=counter2-1; reg2Num=reg2Num+1; ] { } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 2; export tmp; } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 2; export tmp; } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 4; export tmp; } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 2; export tmp; } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 2; export tmp; } -vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; tmp:4 = 4; export tmp; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; } @define Vst2DdList "(c0811=3 | c0811=8 | c0811=9)" @@ -4720,14 +4619,14 @@ buildVtblDdList: Dreg,buildVtblDdList is Dreg & buildVtblDdList [ counter=count build buildVtblDdList; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=0 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=1; ] { tmp:4 = 1; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=1 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=2; ] { tmp:4 = 2; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=2 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=3; ] { tmp:4 = 3; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=3 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=4; ] { tmp:4 = 4; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=0 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=1; ] { tmp:4 = 1; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=1 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=2; ] { tmp:4 = 2; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=2 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=3; ] { tmp:4 = 3; export tmp; } -vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=3 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=4; ] { tmp:4 = 4; export tmp; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=0 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=1; ] { export 1:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=1 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=2; ] { export 2:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=2 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=3; ] { export 3:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=3 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=4; ] { export 4:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=0 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=1; ] { export 1:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=1 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=2; ] { export 2:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=2 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=3; ] { export 3:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=3 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=4; ] { export 4:4; } :vtbl.8 VRd,vtblDdList,VRm is ( ($(AMODE) & cond=15 & c2327=7 & c2021=3 & c1011=2 & c0606=0 & c0404=0) |