mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-28 17:11:11 -09:00
Code Issues Packages Projects Releases Wiki Activity

GP-2812: Corrected issue with ARMv5/v4 not setting ARMcond and possible regression issues for ARMv5t/v4t

Browse Source
This commit is contained in:
ghidorahrex
2022-11-10 15:22:21 -05:00
committed by ghidra1
parent b5537b91e5
commit a0babb47e7
3 changed files with 26 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
Ghidra/Processors/ARM/data/languages/ARM.ldefs
View File

@@ -5,7 +5,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v8" variant="v8"
version="1.105" version="1.106"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -29,7 +29,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v8T" variant="v8T"
version="1.105" version="1.106"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec" processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -49,7 +49,7 @@
instructionEndian="little" instructionEndian="little"
size="32" size="32"
variant="v8LEInstruction" variant="v8LEInstruction"
version="1.105" version="1.106"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -64,7 +64,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v8" variant="v8"
version="1.105" version="1.106"
slafile="ARM8_be.sla" slafile="ARM8_be.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -87,7 +87,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v8T" variant="v8T"
version="1.105" version="1.106"
slafile="ARM8_be.sla" slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec" processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -104,7 +104,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v7" variant="v7"
version="1.105" version="1.106"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -124,7 +124,7 @@
instructionEndian="little" instructionEndian="little"
size="32" size="32"
variant="v7LEInstruction" variant="v7LEInstruction"
version="1.105" version="1.106"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -139,7 +139,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v7" variant="v7"
version="1.105" version="1.106"
slafile="ARM7_be.sla" slafile="ARM7_be.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -157,7 +157,7 @@
endian="little" endian="little"
size="32" size="32"
variant="Cortex" variant="Cortex"
version="1.105" version="1.106"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec" processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -177,7 +177,7 @@
endian="big" endian="big"
size="32" size="32"
variant="Cortex" variant="Cortex"
version="1.105" version="1.106"
slafile="ARM7_be.sla" slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec" processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -196,7 +196,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v6" variant="v6"
version="1.105" version="1.106"
slafile="ARM6_le.sla" slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec" processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -216,7 +216,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v6" variant="v6"
version="1.105" version="1.106"
slafile="ARM6_be.sla" slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec" processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -236,7 +236,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v5t" variant="v5t"
version="1.105" version="1.106"
slafile="ARM5t_le.sla" slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -254,7 +254,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v5t" variant="v5t"
version="1.105" version="1.106"
slafile="ARM5t_be.sla" slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -272,7 +272,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v5" variant="v5"
version="1.105" version="1.106"
slafile="ARM5_le.sla" slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -304,7 +304,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v4t" variant="v4t"
version="1.105" version="1.106"
slafile="ARM4t_le.sla" slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -321,7 +321,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v4t" variant="v4t"
version="1.105" version="1.106"
slafile="ARM4t_be.sla" slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -338,7 +338,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v4" variant="v4"
version="1.105" version="1.106"
slafile="ARM4_le.sla" slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@@ -358,7 +358,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v4" variant="v4"
version="1.105" version="1.106"
slafile="ARM4_be.sla" slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"

7
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
View File

@@ -1024,11 +1024,8 @@ RtGotoCheck: is Rt1215 {}
# #
@if defined(VERSION_6T2) || defined(VERSION_7) # Ensure that the condition check phase has been completed
# Ensure that the recursive rule for ARMcond is applied for assembly
with : ARMcondCk=1 { with : ARMcondCk=1 {
@endif
:adc^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x105 & Rm0305 & Rd0002 & CheckInIT_CZNO :adc^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x105 & Rm0305 & Rd0002 & CheckInIT_CZNO
{ {
@@ -5291,6 +5288,6 @@ Pcrel: [cloc,Rm0003] is Rm0003 & thc0404=1 [ cloc = inst_next; ]
{ {
HintYield(); HintYield();
} }
@endif #VERSION_6T2 || VERSION_7
} # End with : ARMcondCk=1 } # End with : ARMcondCk=1
@endif # VERSION_6T2 || VERSION_7

15
Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
View File

@@ -1522,19 +1522,13 @@ SRSMode: "sys" is srsMode=23 & c0004 { export *[const]:1 c0004; }
SRSMode: "#"^srsMode is srsMode { export *[const]:1 srsMode; } SRSMode: "#"^srsMode is srsMode { export *[const]:1 srsMode; }
@endif # VERSION_6 @endif # VERSION_6
# Add a hat instruction to set the ARMcond context variable which # Perform ARMcond check phase and set ARMcond context variable
# tells whether this is a legal conditional instruction (for v7 and :^instruction is $(AMODE) & ARMcondCk=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {}
# later).
@if defined(VERSION_6T2) || defined(VERSION_7)
:^instruction is ARMcondCk=0 & itmode=0 & TMode=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {}
:^instruction is ARMcondCk=0 & instruction [ ARMcondCk=1; ARMcond=0; ] {} :^instruction is ARMcondCk=0 & instruction [ ARMcondCk=1; ARMcond=0; ] {}
# Ensure one of the recursive rules above is applied for assembly # Ensure that the condition check phase has been completed
with : ARMcondCk=1 { with : ARMcondCk=1 {
@endif
################################################# #################################################
# #
# Include the SIMD/VFP instructions before the # Include the SIMD/VFP instructions before the
@@ -6466,6 +6460,5 @@ armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; }
#} #}
@if defined(VERSION_6T2) || defined(VERSION_7)
} # End with : ARMcondCk=1 } # End with : ARMcondCk=1
@endif