From a25e48399ee6900cf6aa73ab2b54e0a67bfc9d1e Mon Sep 17 00:00:00 2001 From: Christian Zietz Date: Wed, 4 Mar 2020 06:35:09 +0000 Subject: [PATCH] 68000: Rework fix for MOVE USP,x and MOVE x,USP --- Ghidra/Processors/68000/data/languages/68000.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/68000/data/languages/68000.sinc b/Ghidra/Processors/68000/data/languages/68000.sinc index d76c81ae84..773ee2c4c6 100644 --- a/Ghidra/Processors/68000/data/languages/68000.sinc +++ b/Ghidra/Processors/68000/data/languages/68000.sinc @@ -1084,8 +1084,8 @@ macro shiftCXFlags(cntreg) { :move eaw,"CCR" is (opbig=0x44 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { unpackflags(eaw); } :move SR,eaw is SR; (opbig=0x40 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { packflags(SR); eaw = SR; } :move eaw,SR is SR; (opbig=0x46 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { SR = eaw; unpackflags(SR); } -:move "USP",regan is opbig=0x4e & op37=13 & regan { regan = SP; } -:move regan,"USP" is opbig=0x4e & op37=12 & regan { SP = regan; } +:move USP,regan is opbig=0x4e & op37=13 & regan & USP { regan = USP; } +:move regan,USP is opbig=0x4e & op37=12 & regan & USP { USP = regan; } :movea.w eaw,reg9an is (op=3 & reg9an & mode2=1)... & eaw { reg9an = sext(eaw); } :movea.l eal,reg9an is (op=2 & reg9an & mode2=1)... & eal { reg9an = eal; }