diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc
index 4517dee68f..fdf3ea0e3a 100644
--- a/Ghidra/Processors/x86/data/languages/ia.sinc
+++ b/Ghidra/Processors/x86/data/languages/ia.sinc
@@ -3766,14 +3766,23 @@ define pcodeop ibhf;
 :IRETQ          is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf            { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); return [RIP]; }
 @endif
 
-# Use the gcc binutils style for branch hints
-bh: ", pn" is segover=1 {} # HWNT Branch Not Taken hint (prefix 2E)
-bh: ", pt" is segover=3 {} # HST  Branch Taken hint (prefix 3E)
-bh: is epsilon {}
-:J^cc rel8^bh      is vexMode=0 & row=7 & cc & bh; rel8                                          { if (cc) goto rel8; }
-:J^cc rel16^bh     is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf & bh; row=8 & cc; rel16  { if (cc) goto rel16; }
-:J^cc rel32^bh     is vexMode=0 & opsize=1 & byte=0xf & bh; row=8 & cc; rel32                    { if (cc) goto rel32; }
-:J^cc rel32^bh     is vexMode=0 & opsize=2 & byte=0xf & bh; row=8 & cc; rel32                    { if (cc) goto rel32; }
+# HWNT Branch Not Taken hint (prefix 2E)
+# HST  Branch Taken hint (prefix 3E)
+jccRel8:  rel8   is  rel8  { export rel8; }
+jccRel8:  rel8, "bn"   is segover=1 & rel8  { export rel8; }
+jccRel8:  rel8, "bt"   is segover=3 & rel8  { export rel8; }
+jccRel16: rel16  is rel16 { export rel16; }
+jccRel16: rel16, "bn"  is segover=1 & rel16 { export rel16; }
+jccRel16: rel16, "bt"  is segover=3 & rel16 { export rel16; }
+jccRel32: rel32  is rel32 { export rel32; }
+jccRel32: rel32, "bn"  is segover=1 & rel32 { export rel32; }
+jccRel32: rel32, "bt"  is segover=3 & rel32 { export rel32; }
+
+:J^cc jccRel8      is vexMode=0 & row=7 & cc; jccRel8                                          { if (cc) goto jccRel8; }
+:J^cc jccRel16     is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; row=8 & cc; jccRel16  { if (cc) goto jccRel16; }
+:J^cc jccRel32     is vexMode=0 & opsize=1 & byte=0xf; row=8 & cc; jccRel32                    { if (cc) goto jccRel32; }
+:J^cc jccRel32     is vexMode=0 & opsize=2 & byte=0xf; row=8 & cc; jccRel32                    { if (cc) goto jccRel32; }
+
 # The following is vexMode=0 & picked up by the line above.  rel32 works for both 32 and 64 bit
 #@ifdef IA64
 #:J^cc rel32     is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; row=8 & cc; rel32     { if (cc) goto rel32; }