From a3de4f73de90f0b2c1282e4c8bce5cc8ec0d0f92 Mon Sep 17 00:00:00 2001
From: CmP-lt <61097734+CmP-lt@users.noreply.github.com>
Date: Wed, 9 Feb 2022 06:43:32 +0200
Subject: [PATCH] Fix detection of ARM vraddhn instruction

---
 Ghidra/Processors/ARM/data/languages/ARMneon.sinc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
index bc92a96e18..df1af1b7ad 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
@@ -1784,7 +1784,7 @@ extImm: "#"^thv_c0811	is TMode=1 & thv_c0811	{ tmp:1 = thv_c0811; export tmp; }
 }
 
 
-:vraddhn.i^esize2021x2 Dd,Qn,Qm    is (($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3  & c0811=4 & Q6=0 & c0404=0) |
+:vraddhn.i^esize2021x2 Dd,Qn,Qm    is (($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3  & c0811=4 & Q6=0 & c0404=0) |
 	                                   ($(TMODE_F) & thv_c2327=0x1f & thv_c2021<3  & thv_c0811=4 & thv_Q6=0 & thv_c0404=0) ) & Qm & esize2021x2 & Qn & Dd
 {
 	Dd = VectorRoundAddAndNarrow(Qn,Qm,esize2021x2);