diff --git a/Ghidra/Processors/PIC/data/languages/pic16.ldefs b/Ghidra/Processors/PIC/data/languages/pic16.ldefs
index af82b20edb..94d988f255 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16.ldefs
+++ b/Ghidra/Processors/PIC/data/languages/pic16.ldefs
@@ -14,7 +14,6 @@
     <compiler name="default" spec="pic16.cspec" id="default"/>
     <external_name tool="IDA-PRO" name="pic16cxx"/>
   </language>
-  <!-- TODO: Need PIC-16F manual and index -->
   <language processor="PIC-16"
             endian="little"
             size="16"
diff --git a/Ghidra/Processors/PIC/data/languages/pic16.pspec b/Ghidra/Processors/PIC/data/languages/pic16.pspec
index 4133f95795..b7ae40d668 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16.pspec
+++ b/Ghidra/Processors/PIC/data/languages/pic16.pspec
@@ -10,6 +10,9 @@
   	<tracked_set space="CODE">
   		<set name="SkipNext" val="0"/>
   	</tracked_set>
+  	<tracked_set space="CODE">
+  		<set name="RP" val="0"/>
+  	</tracked_set>
   	<tracked_set space="CODE" first="0x0" last="0x1ff">
   	  	<set name="PCLATH" val="0"/>
   	</tracked_set>
@@ -40,6 +43,12 @@
   <default_symbols>
     <symbol name="Reset" address="CODE:0000" entry="true"/>
     <symbol name="Interrupt" address="CODE:0004" entry="true"/>
+    
+    <symbol name="PORTA" address="DATA:05" entry="false"/>
+    <symbol name="PORTB" address="DATA:06" entry="false"/>
+    <symbol name="PORTC" address="DATA:07" entry="false"/>
+    <symbol name="PORTD" address="DATA:08" entry="false"/>
+    <symbol name="PORTE" address="DATA:09" entry="false"/>
     <symbol name="PIR1" address="DATA:0C" entry="false"/>
     <symbol name="PIR2" address="DATA:0D" entry="false"/>
     <symbol name="TMR1L" address="DATA:0E" entry="false"/>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16.sinc b/Ghidra/Processors/PIC/data/languages/pic16.sinc
index d7144dae17..ea4b6fadff 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16.sinc
+++ b/Ghidra/Processors/PIC/data/languages/pic16.sinc
@@ -2,28 +2,6 @@
 # PIC-16 Main Section
 #   includes constants, memory space and common register space definitions
 #
-
-# STATUS bit definitions
-@define STATUS_IRP_BIT	7
-@define STATUS_RP0_BIT	5
-@define STATUS_Z_BIT	2
-@define STATUS_DC_BIT	1
-@define STATUS_C_BIT	0
-
-# STATUS bit masks used for setting
-@define STATUS_IRP_MASK 0x80
-@define STATUS_RP_MASK	0x60
-@define STATUS_Z_MASK	0x04
-@define STATUS_DC_MASK	0x02
-@define STATUS_C_MASK	0x01
-
-# STATUS bit masks used for clearing
-@define STATUS_IRP_CLEARMASK 0x7F
-@define STATUS_RP_CLEARMASK	0x9F
-@define STATUS_Z_CLEARMASK	0xFB
-@define STATUS_DC_CLEARMASK	0xFD
-@define STATUS_C_CLEARMASK	0xFE
-
 define endian=little;
 define alignment=2;
 
@@ -50,18 +28,37 @@ define register offset=0x0002 size=1 [ STKPTR ];
 define register offset=0x0003 size=1 [ W SkipNext ];
 
 # Status bit registers (these do not really exist and must get reflected into the STATUS byte register)
-@if PROCESSOR == "PIC_16"
 define register offset=0x0007 size=1 [ IRP RP ];
-@elif PROCESSOR == "PIC_16F"
-define register offset=0x0007 size=1 [ IRP RP ];
-@endif
 
 @define C  "STATUS[0,1]"
 @define DC "STATUS[1,1]"
 @define Z  "STATUS[2,1]"
 @define PD "STATUS[3,1]"
 @define TO "STATUS[4,1]"
-@define PA0 "STATUS[5,1]"
+@define RP "STATUS[5,2]"
+@define IRP "STATUS[7,1]"
+
+# STATUS bit definitions
+@define STATUS_IRP_BIT	7
+@define STATUS_RP_BIT	5
+@define STATUS_Z_BIT	2
+@define STATUS_DC_BIT	1
+@define STATUS_C_BIT	0
+
+# STATUS bit masks used for setting
+@define STATUS_IRP_MASK 0x80
+@define STATUS_RP_MASK	0x60
+@define STATUS_Z_MASK	0x04
+@define STATUS_DC_MASK	0x02
+@define STATUS_C_MASK	0x01
+
+# STATUS bit masks used for clearing
+@define STATUS_IRP_CLEARMASK 0x7F
+@define STATUS_RP_CLEARMASK	0x9F
+@define STATUS_Z_CLEARMASK	0xFB
+@define STATUS_DC_CLEARMASK	0xFD
+@define STATUS_C_CLEARMASK	0xFE
+
 
 #
 # WARNING! - Reflection of these DATA-based registers with the corresponding register
@@ -80,16 +77,16 @@ define register offset=0x0007 size=1 [ IRP RP ];
 #
 @if PROCESSOR == "PIC_16"
 define DATA offset=0x0000 size=1 [
-	INDF	TMR0	PCL		STATUS	FSR		PORTA	PORTB	PORTC	PORTD	PORTE	PCLATH	INTCON	PIR1	PIR2	TMR1L	TMR1H
+#PIC16 FRM		INDF	TMR0	PCL		STATUS	FSR		PORTA	PORTB	PORTC	PORTD	PORTE	PCLATH	INTCON	PIR1	PIR2	TMR1L	TMR1H
+				INDF	_       PCL		STATUS  FSR		_       _       _       _       _       PCLATH  INTCON	_		_       _       _
 ];
-
 @elif PROCESSOR == "PIC_16F"
 define DATA offset=0x0000 size=1 [
-	INDF0	INDF1	PCL	STATUS	FSR0L	FSR0H	FSR1L	FSR1H	BSR	WREG	PCLATH	INTCON	_	_	_	_
+#PIC16LF1554	INDF0	INDF1	PCL		STATUS	FSR0L	FSR0H	FSR1L	FSR1H	BSR		WREG	PCLATH	INTCON	_		_		_		_
+#PIC16LF1559	INDF0	INDF1	PCL		STATUS	FSR0L	FSR0H	FSR1L	FSR1H	BSR		WREG	PCLATH	INTCON	_		_		_		_
+				INDF0	INDF1	PCL		STATUS	FSR0L	FSR0H	FSR1L	FSR1H	BSR		WREG	PCLATH	INTCON	_		_		_		_
 ];
-
 define DATA offset=0x0004 size=2 [ FSR0  FSR1 ];
-
 @endif
 
 # Additional Data Bank data registers are defined in the .PSPEC file.
diff --git a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
index 4bec48f478..efbddbbbc6 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
+++ b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
@@ -46,7 +46,7 @@ define context contextreg
 
 @if PROCESSOR == "PIC_16"
 attach variables [ fregCore ] [
-	INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON _ _ _ _
+	INDF 	_ 		PCL 	STATUS 	FSR 	_		_		_		_ 	_	PCLATH	INTCON	_ _ _ _
 ];
 
 @elif PROCESSOR == "PIC_16F"
@@ -180,14 +180,14 @@ srcREG: fv		is uf7=0x7 & lf7  [fv = 0x70 + lf7; ]								{
 
 # File register index (f7=0): INDF use implies indirect data access using FSR value and IRP bit in STATUS reg
 @if PROCESSOR == "PIC_16"
-srcREG: fregCore		is f7=0 & fregCore									{ 
+srcREG: INDF		is f7=0 & INDF								{ 
 	addr:2 = (zext(IRP) << 8) + zext(FSR);
 	export *[DATA]:1 addr; 
 }
-srcREG: fregCore		is f7=1	& fregCore								{ 
-     rpval:2 = zext(RP == 1) + zext(RP == 2);
-	 addr:2 = (zext(rpval) << 7) + 1;
-	 export *[DATA]:1 addr;
+srcREG: lf7		is f7=1	& lf7								{ 
+	rpval:2 = zext(RP == 1) + zext(RP == 3);
+    addr:2 = (zext(rpval) << 7) + 1;
+	export *[DATA]:1 addr;
 }
 @elif PROCESSOR == "PIC_16F"
 srcREG: fregCore		is f7=0 & fregCore									{