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GP-6591: PIC-18 destReg banked register disassembly fix

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ghidorahrex
2026-03-19 16:07:09 +00:00
parent 661ba5c1c9
commit aeba87ccee
1 changed files with 7 additions and 2 deletions
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9
Ghidra/Processors/PIC/data/languages/pic18_instructions.sinc
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@@ -348,6 +348,11 @@ srcREG: "PC" is a=0 & f8=0xf9 {
export PCL; export PCL;
} }
dfLoc: f8 is a=1 & f8 { # (Banked mode)
addr:2 = (zext(BSR) << 8) + f8;
export *[DATA]:1 addr;
}
dfLoc: f8 is a=0 & f8_57=0x0 & f8 { export *[DATA]:1 f8; } # 0x00-0x1f (Access mode) dfLoc: f8 is a=0 & f8_57=0x0 & f8 { export *[DATA]:1 f8; } # 0x00-0x1f (Access mode)
dfLoc: f8 is a=0 & f8_57=0x1 & f8 { export *[DATA]:1 f8; } # 0x20-0x3f (Access mode) dfLoc: f8 is a=0 & f8_57=0x1 & f8 { export *[DATA]:1 f8; } # 0x20-0x3f (Access mode)
dfLoc: f8 is a=0 & f8_57=0x2 & f8 { export *[DATA]:1 f8; } # 0x40-0x5f (Access mode) dfLoc: f8 is a=0 & f8_57=0x2 & f8 { export *[DATA]:1 f8; } # 0x40-0x5f (Access mode)
@@ -468,8 +473,8 @@ dfLoc: freg is a=0 & f8=0xdb & freg {
# Destination operand representation (w: W register is destination; f: specified fREG is destination) # Destination operand representation (w: W register is destination; f: specified fREG is destination)
# Destination register (either srcREG or WREG) # Destination register (either srcREG or WREG)
destREG: "0" is d=0 { export WREG; } destREG: "w" is d=0 { export WREG; }
destREG: "1" is d=1 & dfLoc { export dfLoc; } destREG: "f" is d=1 & dfLoc { export dfLoc; }
# Source File Registers specified by a 12-bit absolute offsets within 32-bit instriction # Source File Registers specified by a 12-bit absolute offsets within 32-bit instriction
srcREG32: fs is fs { export *[DATA]:1 fs; } # 0x000-0xeff srcREG32: fs is fs { export *[DATA]:1 fs; } # 0x000-0xeff