From b514a2c9ecd2965e1a90cd6a84e43cb2d5526b1d Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 24 Oct 2019 07:18:18 -0400 Subject: [PATCH] GT-3254: PPC VLE Corrected signed immediate offset calculation (fixes #1160) --- Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc | 1 - Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc index 7e60e72591..15d5af3eb0 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc @@ -1002,7 +1002,6 @@ define token instr(32) IMM_11_15_VLE=(11,14) IMM_16_20_VLE=(16,20) IMM_21_25_VLE=(21,25) - SIMM_0_10_VLE=(0,10) signed SIMM_11_14_VLE=(11,14) signed SIMM_21_25_VLE=(21,25) signed SCL_VLE=(8,9) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc index f692d3b56c..81e927ee45 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc @@ -44,7 +44,7 @@ SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFF << ((SCL_VLE*8) SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFFFFFFFFFF << ((SCL_VLE*8) + 8)) | (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:8 val;} @endif -SIMM16: val is SIMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | SIMM_0_10_VLE ;] { export *[const]:2 val; } +SIMM16: val is IMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } SIMM20: val is IMM_0_10_VLE & IMM_16_20_VLE & SIMM_11_14_VLE [ val = (SIMM_11_14_VLE << 16 ) | (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } IMM16: val is IMM_0_10_VLE & IMM_21_25_VLE [ val = (IMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }