From b7937a39d564d73b35e053a2896cb90f032154da Mon Sep 17 00:00:00 2001 From: ghidra1 Date: Thu, 27 Aug 2026 16:43:04 -0400 Subject: [PATCH] GP-7110 Additional Hexagon fixes --- .../Hexagon/data/languages/hexagon.sinc | 14 +-- .../Hexagon/data/languages/hexagon_float.sinc | 112 ++++++++---------- .../Hexagon/data/languages/hexagon_hvx.sinc | 108 +++++++++-------- .../Hexagon/data/languages/hexagon_hvx2.sinc | 2 +- 4 files changed, 117 insertions(+), 119 deletions(-) diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc index 692db0a4f1..b97e5756a7 100755 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc @@ -2357,15 +2357,16 @@ ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P - i i i i i i - - d d d d d -:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) +:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) { - Rd5 = PacketPC; + Rd5 = PacketPC + Uimm32_0712x; build EndPacket; } -:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) +# Simplification when adding zero constant to packet PC +:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) { - Rd5 = PacketPC + Uimm32_0712x; + Rd5 = PacketPC; build EndPacket; } @@ -13428,11 +13429,6 @@ define pcodeop pmpyw; build EndPacket; } -# (v2,6) resume -- "resume ( Rs32 )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 1 - - - - - - # (v5,8) popcount -- "Rd32 = popcount ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc index 071d6d1178..00d6e1de3b 100644 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc @@ -1,26 +1,13 @@ # # Floating Point Instructions -# Added with V5x: -# convert_sf2d, convert_sf2df, convert_sf2ud, convert_sf2uw, convert_sf2w -# convert_d2sf, convert_ud2sf, convert_uw2sf, convert_w2sf -# convert_df2d, convert_df2sf, convert_df2ud, convert_df2uw, convert_df2w -# convert_d2df, convert_ud2df, convert_uw2df, convert_w2df -# sfadd, sfclass, sfcmp.*, sffixupd, sffixupn, sffixupr, sfmake, sfmax, sfmin, sfmpy, sfsub -# dfclass, dfcmp.*, dfmake -# Added with V65: -# sfinvsqrta, sfrecipa -# Added with V66: -# dfadd, dfsub -# Added with V67: -# dfmax, dfmin, dfmpyfix, dfmpyhh, dfmpylh, dfmpyll # -# See bottom of this file for additional instruction patterns found within QEMU source code. -# Use of the undocumented double-precission floating instructions are disabled by default -# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to -# to enable the use of these undocumented instructions which will disable the use of -# corresponding V6 instructions which conflict. +# NOTE: See bottom of this file for additional instruction patterns found within QEMU source code. +# Use of the undocumented double-precission floating instructions are disabled by default +# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to +# to enable the use of these undocumented instructions which will disable the use of +# corresponding V6 instructions which conflict. # -# NOTE:The SLEIGH built-in float operators (float2float, int2float, float2int) use IEEE-754 +# NOTE: The SLEIGH built-in float operators (float2float, int2float, float2int) use IEEE-754 # round-to-nearest-even by default. Hexagon's USR register (bits 2:0 = RND) controls the # rounding mode, and bits in USR capture FP exception status. For decompilation purposes the # default rounding mode is acceptable. For emulation, programs that rely on non-default @@ -423,6 +410,28 @@ define pcodeop sffixupr; build EndPacket; } +# (v5,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P - - - - - - 0 e e d d d d d + +define pcodeop sfinvsqrta; # Rd = float inverse square root approximation of Rs +define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation + +:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) { + + # NOTE: Per PRM 80-N2040-60 p.594, Rd and Pe are only written when + # invsqrt_common(Rs) returns true (i.e. Rs is a normal-range value). + # For special inputs (NaN, infinity, zero, denormal) the writes are + # suppressed; that conditional is not modelled here. + + Rd5 = sfinvsqrta(rs5); + pu0506_ = sfinvsqrtaPred(rs5); + build EndPacket; + <> + pu0506 = pu0506_; +} + # (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :neg" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -535,8 +544,18 @@ define pcodeop sffixupr; build EndPacket; } +# (v5,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d - +:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { + src1:4 = rs5; + src2:4 = rt5; + Rd5 = reciprocal(src1, src2); + Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); + build EndPacket; +} # (v5,14) sfsub -- "Rd = sfsub ( Rs, Rt )" # _________________________________________________________________________________________________ @@ -624,46 +643,7 @@ define pcodeop sffixupr; } # -# V65 Floating Point Instructions -# - -# (v65,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P - - - - - - 0 e e d d d d d - -define pcodeop sfinvsqrta; # Rd = float inverse square root approximation of Rs -define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation - -:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) { - - # NOTE: Per PRM 80-N2040-60 p.594, Rd and Pe are only written when - # invsqrt_common(Rs) returns true (i.e. Rs is a normal-range value). - # For special inputs (NaN, infinity, zero, denormal) the writes are - # suppressed; that conditional is not modelled here. - - Rd5 = sfinvsqrta(rs5); - pu0506_ = sfinvsqrtaPred(rs5); - build EndPacket; - <> - pu0506 = pu0506_; -} - -# (v65,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d - -:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { - src1:4 = rs5; - src2:4 = rt5; - Rd5 = reciprocal(src1, src2); - Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); - build EndPacket; -} - -# -# V66 Floating Point Instructions +# V66 Floating Point Instructions # # (v66,14) dfadd -- "Rdd = dfadd ( Rss, Rtt )" @@ -720,7 +700,7 @@ define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation build EndPacket; } -# (v5,14) c -- "Rdd = dfmpyfix ( Rss, Rtt )" +# (v67,14) dfmpyfix -- "Rdd = dfmpyfix ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d @@ -755,7 +735,7 @@ define pcodeop dfmpylh; build EndPacket; } -# (v5,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" +# (v67,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d @@ -775,6 +755,14 @@ define pcodeop dfmpyll; # specific processor version that we have been able to identify. These instructions are for experimental # use only and may be intended for QEMU development testing only. # +# The "??" version marker below is intentional: no processor version could be established for these +# encodings. QEMU itself guards them with its own ADD_DP_OPS conditional in +# target/hexagon/imported/encode_pp.def (alongside the emulator-only F2_dfdivcheat / F2_dfsqrtcheat +# encodings) without attributing an architecture version, has no corresponding definitions in +# target/hexagon/imported/float.idef, and LLVM's HexagonDepInstrInfo.td has no definitions for them at +# all. They are likewise absent from every PRM checked (V60/V61 through V79), and the Qualcomm +# hexagon-llvm-mc assembler rejects them for every supported -mcpu (hexagonv65 through hexagonv71). +# ############################################################################################################# @ifdef ADD_DP_OPS diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc index 67c537d402..46bdf98133 100644 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc @@ -251,6 +251,18 @@ Qv_1112_S05: "!"^qv1112 is qv1112 & op5=1 { tmp:$(HVX_PREDICATE_SIZE) = ~qv1112; export tmp; } + +# Vector predicate source qv0809 (inverted) +Qv0809Not: "!"^qv0809 is qv0809 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv0809; + export tmp; +} + +# Vector predicate source qv2223 (inverted) +Qv2223Not: "!"^qv2223 is qv2223 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv2223; + export tmp; +} # Predicate Register Condition (least significant bit only) @@ -291,7 +303,6 @@ VPuCond1112_S05: ".if(!"pu1112name")" is op5=1 & pu1112 & pu1112name [cond=1;] ConditionReg = condition; } - # Signed immediate s3 Simm32_0810: "#"^s0810 is s0810 { export *[const]:4 s0810; } @@ -543,6 +554,16 @@ define pcodeop vhistq; build EndPacket; } +# (v60,1) and -- "Qd4=and(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d + +:and Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) { + Qd2 = qv0809 & Qv2223Not; + build EndPacket; +} + # (v60,1) or -- "Qd4=or(Qs4,Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -553,6 +574,16 @@ define pcodeop vhistq; build EndPacket; } +# (v60,1) or -- "Qd4=or(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d + +:or Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) { + Qd2 = qv0809 | Qv2223Not; + build EndPacket; +} + # (v60,1) xor -- "Qd4=xor(Qs4,Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -563,26 +594,6 @@ define pcodeop vhistq; build EndPacket; } -# (v60,1) or -- "Qd4=or(Qs4,!Qt4)" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d - -:or Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 | ~qv2223; - build EndPacket; -} - -# (v60,1) and -- "Qd4=and(Qs4,!Qt4)" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d - -:and Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 & ~qv2223; - build EndPacket; -} - # (v60,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -978,6 +989,7 @@ define pcodeop vsub_WuwWuw_sat; # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d +# define pcodeop vand_QV; @@ -991,8 +1003,8 @@ define pcodeop vand_QV; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d -:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { - Vd5 = vand_QV(~qv2223,Vu_0812); +:vand Vd5,Qv2223Not,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & Qv2223Not & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(Qv2223Not,Vu_0812); build EndPacket; } @@ -2365,11 +2377,23 @@ define pcodeop vcmp_gtxacc_QVhfVhf; define pcodeop condnac_QnVbVb; +# TODO: Verify that Ghidra renders properly (other cases like this exist) :accum^".if("^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { Vd5 = condnac_QnVbVb(qv2223,VsB_0004,VuB_0812); build EndPacket; } +# (v60,1) "if (!Qv4) Vx.b+=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x + +# TODO: Verify that Ghidra renders properly (other cases like this exist) +:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + # (v60,1) "if (Qv4) Vx.h+=Vu.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -2382,6 +2406,16 @@ define pcodeop condnac_QnVhVh; build EndPacket; } +# (v60,1) "if (!Qv4) Vx.h+=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x + +:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + # (v60,1) "if (Qv4) Vx.w+=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -2394,26 +2428,6 @@ define pcodeop condnac_QnVwVw; build EndPacket; } -# (v60,1) "if (!Qv4) Vx.b+=Vu.b" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x - -:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { - Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); - build EndPacket; -} - -# (v60,1) "if (!Qv4) Vx.h+=Vu.h" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x - -:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { - Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); - build EndPacket; -} - # (v60,1) "if (!Qv4) Vx.w+=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -4765,8 +4779,8 @@ define pcodeop V_vandor_VQR; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x -:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { - Vd5 = V_vandor_VQR(vs5,~qv0809,rx5); +:vand|= Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & Qv0809Not & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,Qv0809Not,rx5); build EndPacket; } @@ -4787,8 +4801,8 @@ define pcodeop V_vand_QR; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d -:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { - Vd5 = V_vand_QR(~qv0809,rx5); +:vand Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & Qv0809Not & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(Qv0809Not,rx5); build EndPacket; } diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx2.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx2.sinc index 8b71b013af..b88e006ae9 100644 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx2.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx2.sinc @@ -296,7 +296,7 @@ define pcodeop v_zextract_Rt; # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 1 1 0 d d d d d -:assign VdH_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x6 & VdH_0004 & VuHF_0812 & $(END_PACKET) { +:assign^":rnd" VdH_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x6 & VdH_0004 & VuHF_0812 & $(END_PACKET) { VdH_0004 = Vh_equals_Vhf(VuHF_0812); build EndPacket; }