From d35e81051a396ea92368367881e3414ad7374a48 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 28 Mar 2023 13:13:19 -0400 Subject: [PATCH] GP-2892: corrected NOP 0x90 to not collide with PAUSE. --- Ghidra/Processors/x86/data/languages/ia.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 34fd0d66ef..aa43ced869 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -288,6 +288,7 @@ define context contextreg rexRprefix=(16,16) # REX.R bit prefix extend r rexXprefix=(17,17) # REX.X bit prefix extend SIB index field to 4 bits rexBprefix=(18,18) # REX.B bit prefix extend r/m, SIB base, Reg operand + rexWRXBprefix=(15,18) # REX.WRXB bits rexprefix=(19,19) # True if the Rex prefix is present - note, if present, vex_mode is not supported # rexWRXB bits can be re-used since they are incompatible. vexMode=(20,20) # 1 for vex instruction, 0 for normal @@ -3201,8 +3202,7 @@ define pcodeop swap_bytes; :NEG rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=3 ... { negflags(rm64); rm64 = -rm64; resultflags(rm64); } @endif -:NOP is vexMode=0 & opsize=0 & byte=0x90 & rexprefix=0 { } -:NOP is vexMode=0 & opsize=1 & byte=0x90 & rexprefix=0 { } +:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4) & (rexprefix=0 | rexWRXBprefix=8) { } :NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { } :NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { } :NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { }