From c0bc9a882b7e6c6d3c0549c4410a8ae1abb68f00 Mon Sep 17 00:00:00 2001
From: Goatman13 <101417270+Goatman13@users.noreply.github.com>
Date: Thu, 8 Feb 2024 10:19:47 +0100
Subject: [PATCH] PowerPC VLE: Fix se_blrl flow

Opcode se_blrl is branch link register and link. Treating it as a return break flow and is wrong. Non VLE is already correct.
---
 Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
index 7b08e4b5a0..9e6f83ee10 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -114,7 +114,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 :se_blrl						is $(ISVLE) & OP15_VLE=2 & LK0_VLE=1 {	
 	tmp:$(REGISTER_SIZE) = LR & ~1;
 	LR = inst_next;
-	return [tmp];			
+	call [tmp];			
 }
 
 :se_sc							is $(ISVLE) & OP16_VLE=2 {