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Fix FDIVP freg,ST0

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AltimorTASDK
2024-03-01 03:35:53 -05:00
committed by GitHub
parent 63e64d5b28
commit c1debd3c94
1 changed files with 1 additions and 1 deletions
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Ghidra/Processors/x86/data/languages/ia.sinc
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@@ -4186,7 +4186,7 @@ define pcodeop fcos;
:FDIV spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=6 ... & spec_m64 { ST0 = ST0 f/ float2float(spec_m64); }
:FDIV ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=0 & freg & ST0 { ST0 = ST0 f/ freg; }
:FDIV freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=1 & freg & ST0 { freg = freg f/ ST0; }
:FDIVP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=1 & freg & ST0 { freg = ST0 f/ freg; fpop(); }
:FDIVP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=1 & freg & ST0 { freg = freg f/ ST0; fpop(); }
:FDIVP is vexMode=0 & byte=0xDE; byte=0xF9 { ST1 = ST1 f/ ST0; fpop(); }
:FIDIV spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=6 ... & spec_m32 { ST0 = ST0 f/ int2float(spec_m32); }
:FIDIV spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=6 ... & spec_m16 { ST0 = ST0 f/ int2float(spec_m16); }