diff --git a/Ghidra/Processors/RISCV/certification.manifest b/Ghidra/Processors/RISCV/certification.manifest
index 94d243a378..0df1bf8e2f 100644
--- a/Ghidra/Processors/RISCV/certification.manifest
+++ b/Ghidra/Processors/RISCV/certification.manifest
@@ -1,50 +1,52 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
-data/languages/RV32G.pspec||GHIDRA||||END|
-data/languages/RV32GC.pspec||GHIDRA||||END|
-data/languages/RV32I.pspec||GHIDRA||||END|
-data/languages/RV32IC.pspec||GHIDRA||||END|
-data/languages/RV32IMC.pspec||GHIDRA||||END|
-data/languages/RV64G.pspec||GHIDRA||||END|
-data/languages/RV64GC.pspec||GHIDRA||||END|
-data/languages/RV64I.pspec||GHIDRA||||END|
-data/languages/RV64IC.pspec||GHIDRA||||END|
+data/languages/riscv32.cspec||GHIDRA||||END|
+data/languages/riscv32.dwarf||GHIDRA||||END|
+data/languages/riscv32-fp.cspec||GHIDRA||||END|
+data/languages/riscv64.cspec||GHIDRA||||END|
+data/languages/riscv64.dwarf||GHIDRA||||END|
+data/languages/riscv64-fp.cspec||GHIDRA||||END|
data/languages/riscv.csr.sinc||GHIDRA||||END|
-data/languages/riscv.ilp32.slaspec||GHIDRA||||END|
+data/languages/riscv.custom.sinc||GHIDRA||||END|
data/languages/riscv.ilp32d.slaspec||GHIDRA||||END|
-data/languages/riscv.ilp32f.slaspec||GHIDRA||||END|
data/languages/riscv.instr.sinc||GHIDRA||||END|
data/languages/riscv.ldefs||GHIDRA||||END|
-data/languages/riscv.lp64.slaspec||GHIDRA||||END|
data/languages/riscv.lp64d.slaspec||GHIDRA||||END|
-data/languages/riscv.lp64f.slaspec||GHIDRA||||END|
data/languages/riscv.opinion||GHIDRA||||END|
data/languages/riscv.priv.sinc||GHIDRA||||END|
data/languages/riscv.reg.sinc||GHIDRA||||END|
data/languages/riscv.rv32a.sinc||GHIDRA||||END|
+data/languages/riscv.rv32b.sinc||GHIDRA||||END|
data/languages/riscv.rv32d.sinc||GHIDRA||||END|
data/languages/riscv.rv32f.sinc||GHIDRA||||END|
data/languages/riscv.rv32i.sinc||GHIDRA||||END|
+data/languages/riscv.rv32k.sinc||GHIDRA||||END|
data/languages/riscv.rv32m.sinc||GHIDRA||||END|
+data/languages/riscv.rv32p.sinc||GHIDRA||||END|
data/languages/riscv.rv32q.sinc||GHIDRA||||END|
data/languages/riscv.rv64a.sinc||GHIDRA||||END|
+data/languages/riscv.rv64b.sinc||GHIDRA||||END|
data/languages/riscv.rv64d.sinc||GHIDRA||||END|
data/languages/riscv.rv64f.sinc||GHIDRA||||END|
data/languages/riscv.rv64i.sinc||GHIDRA||||END|
+data/languages/riscv.rv64k.sinc||GHIDRA||||END|
data/languages/riscv.rv64m.sinc||GHIDRA||||END|
+data/languages/riscv.rv64p.sinc||GHIDRA||||END|
data/languages/riscv.rv64q.sinc||GHIDRA||||END|
data/languages/riscv.rvc.sinc||GHIDRA||||END|
+data/languages/riscv.rvv.sinc||GHIDRA||||END|
data/languages/riscv.table.sinc||GHIDRA||||END|
data/languages/riscv.zi.sinc||GHIDRA||||END|
-data/languages/riscv32-fp.cspec||GHIDRA||||END|
-data/languages/riscv32-fp.dwarf||GHIDRA||||END|
-data/languages/riscv32.cspec||GHIDRA||||END|
-data/languages/riscv32.dwarf||GHIDRA||||END|
-data/languages/riscv64-fp.cspec||GHIDRA||||END|
-data/languages/riscv64-fp.dwarf||GHIDRA||||END|
-data/languages/riscv64.cspec||GHIDRA||||END|
-data/languages/riscv64.dwarf||GHIDRA||||END|
+data/languages/RV32GC.pspec||GHIDRA||||END|
+data/languages/RV32G.pspec||GHIDRA||||END|
+data/languages/RV32IC.pspec||GHIDRA||||END|
+data/languages/RV32IMC.pspec||GHIDRA||||END|
+data/languages/RV32I.pspec||GHIDRA||||END|
+data/languages/RV64GC.pspec||GHIDRA||||END|
+data/languages/RV64G.pspec||GHIDRA||||END|
+data/languages/RV64IC.pspec||GHIDRA||||END|
+data/languages/RV64I.pspec||GHIDRA||||END|
data/patterns/patterncontraints.xml||GHIDRA||||END|
data/patterns/riscv_gc_patterns.xml||GHIDRA||||END|
scripts/binutil.py||GHIDRA||||END|
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32G.pspec b/Ghidra/Processors/RISCV/data/languages/RV32G.pspec
index 4ae572b3e3..b3b2a71451 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV32G.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV32G.pspec
@@ -4,8 +4,16 @@
-
-
+
+
+
+
+
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec
index 30a359fcfa..133923e1eb 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec
@@ -4,9 +4,17 @@
-
-
+
+
+
+
+
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32I.pspec b/Ghidra/Processors/RISCV/data/languages/RV32I.pspec
index c2f0d8f3f8..7ece09e0e1 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV32I.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV32I.pspec
@@ -4,8 +4,11 @@
-
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec
index 19e5af29d3..148daf445f 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec
@@ -4,9 +4,12 @@
-
-
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec
index 7a67fe559c..b9f539d28a 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec
@@ -4,10 +4,13 @@
-
+
+
+
-
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64G.pspec b/Ghidra/Processors/RISCV/data/languages/RV64G.pspec
index 789744421c..dcf939f3cf 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV64G.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV64G.pspec
@@ -4,8 +4,16 @@
-
-
+
+
+
+
+
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec
index b336b24854..2e75cb4f6a 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec
@@ -4,9 +4,17 @@
-
-
+
+
+
+
+
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64I.pspec b/Ghidra/Processors/RISCV/data/languages/RV64I.pspec
index 1af12e37bd..726e53df3f 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV64I.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV64I.pspec
@@ -4,8 +4,11 @@
-
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec
index 3aeb8c2115..0944cda18a 100644
--- a/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec
+++ b/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec
@@ -4,9 +4,12 @@
-
-
+
+
+
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
index cc2c099490..f00a83d20e 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc
@@ -4,76 +4,70 @@
# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0)
:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519
{
- #TODO Size restriction error
- # local tmprs1:$(XLEN) = rs1;
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # rd = oldcsr;
- # local tmp:$(XLEN) = op1519;
- # if (tmp == 0) goto inst_next;
- # local newcsr:$(XLEN) = oldcsr & ~tmprs1;
- # csr = zext(newcsr);
+ local tmprs1:$(XLEN) = rs1;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ rd = oldcsr;
+ local tmp:$(XLEN) = op1519;
+ if (tmp == 0) goto inst_next;
+ local newcsr:$(XLEN) = oldcsr & ~tmprs1;
+ csr = newcsr;
}
# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0)
:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7
{
- #TODO Size restriction error
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # rd = oldcsr;
- # local tmp:$(XLEN) = op1519;
- # if (tmp == 0) goto inst_next;
- # csr = csr & ~tmp;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ rd = oldcsr;
+ local tmp:$(XLEN) = op1519;
+ if (tmp == 0) goto inst_next;
+ csr = csr & ~tmp;
}
# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0)
:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519
{
- #TODO Size restriction error
- # local tmprs1 = rs1;
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # rd = oldcsr;
- # local tmp:$(XLEN) = op1519;
- # if (tmp == 0) goto inst_next;
- # csr = csr | tmprs1;
+ local tmprs1 = rs1;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ rd = oldcsr;
+ local tmp:$(XLEN) = op1519;
+ if (tmp == 0) goto inst_next;
+ csr = csr | tmprs1;
}
# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0)
:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6
{
- #TODO Size restriction error
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # rd = oldcsr;
- # local tmp:$(XLEN) = op1519;
- # if (tmp == 0) goto inst_next;
- # csr = csr | tmp;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ rd = oldcsr;
+ local tmp:$(XLEN) = op1519;
+ if (tmp == 0) goto inst_next;
+ csr = csr | tmp;
}
# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0)
:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519
{
- #TODO Size restriction error
- # local tmprs1:$(XLEN) = rs1;
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # local tmp:$(XLEN) = op1519;
- # csr = tmprs1;
- # if (tmp == 0) goto inst_next;
- # rd = oldcsr;
+ local tmprs1:$(XLEN) = rs1;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ local tmp:$(XLEN) = op1519;
+ csr = tmprs1;
+ if (tmp == 0) goto inst_next;
+ rd = oldcsr;
}
# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0)
:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5
{
- #TODO Size restriction error
- # local oldcsr:$(XLEN) = csr:$(XLEN);
- # local tmp:$(XLEN) = op1519;
- # csr = tmp;
- # if (tmp == 0) goto inst_next;
- # rd = oldcsr;
+ local oldcsr:$(XLEN) = csr:$(XLEN);
+ local tmp:$(XLEN) = op1519;
+ csr = tmp;
+ if (tmp == 0) goto inst_next;
+ rd = oldcsr;
}
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc
new file mode 100644
index 0000000000..3b859a1c2c
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc
@@ -0,0 +1,155 @@
+# custom
+
+define pcodeop custom0;
+define pcodeop custom0.rs1;
+define pcodeop custom0.rs1.rs2;
+define pcodeop custom0.rd;
+define pcodeop custom0.rd.rs1;
+define pcodeop custom0.rd.rs1.rs2;
+
+define pcodeop custom1;
+define pcodeop custom1.rs1;
+define pcodeop custom1.rs1.rs2;
+define pcodeop custom1.rd;
+define pcodeop custom1.rd.rs1;
+define pcodeop custom1.rd.rs1.rs2;
+
+define pcodeop custom2;
+define pcodeop custom2.rs1;
+define pcodeop custom2.rs1.rs2;
+define pcodeop custom2.rd;
+define pcodeop custom2.rd.rs1;
+define pcodeop custom2.rd.rs1.rs2;
+
+define pcodeop custom3;
+define pcodeop custom3.rs1;
+define pcodeop custom3.rs1.rs2;
+define pcodeop custom3.rd;
+define pcodeop custom3.rd.rs1;
+define pcodeop custom3.rd.rs1.rs2;
+
+:custom0 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x0
+{
+ custom0();
+}
+
+:custom0.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x2 & rs1
+{
+ custom0.rs1(rs1);
+}
+
+:custom0.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x3 & rs1 & rs2
+{
+ custom0.rs1.rs2(rs1, rs2);
+}
+
+:custom0.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x4 & rd
+{
+ rd = custom0.rd();
+}
+
+:custom0.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x6 & rd & rs1
+{
+ rd = custom0.rd.rs1(rs1);
+}
+
+:custom0.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x7 & rd & rs1 & rs2
+{
+ rd = custom0.rd.rs1.rs2(rs1, rs2);
+}
+
+
+:custom1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x0
+{
+ custom1();
+}
+
+:custom1.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x2 & rs1
+{
+ custom1.rs1(rs1);
+}
+
+:custom1.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x3 & rs1 & rs2
+{
+ custom1.rs1.rs2(rs1, rs2);
+}
+
+:custom1.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x4 & rd
+{
+ rd = custom1.rd();
+}
+
+:custom1.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x6 & rd & rs1
+{
+ rd = custom1.rd.rs1(rs1);
+}
+
+:custom1.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x7 & rd & rs1 & rs2
+{
+ rd = custom1.rd.rs1.rs2(rs1, rs2);
+}
+
+
+#TODO handle RV128 for custom-2/custom-3
+
+:custom2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x0
+{
+ custom2();
+}
+
+:custom2.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x2 & rs1
+{
+ custom2.rs1(rs1);
+}
+
+:custom2.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x3 & rs1 & rs2
+{
+ custom2.rs1.rs2(rs1, rs2);
+}
+
+:custom2.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x4 & rd
+{
+ rd = custom2.rd();
+}
+
+:custom2.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x6 & rd & rs1
+{
+ rd = custom2.rd.rs1(rs1);
+}
+
+:custom2.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x7 & rd & rs1 & rs2
+{
+ rd = custom2.rd.rs1.rs2(rs1, rs2);
+}
+
+
+:custom3 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x0
+{
+ custom3();
+}
+
+:custom3.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x2 & rs1
+{
+ custom3.rs1(rs1);
+}
+
+:custom3.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x3 & rs1 & rs2
+{
+ custom3.rs1.rs2(rs1, rs2);
+}
+
+:custom3.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x4 & rd
+{
+ rd = custom3.rd();
+}
+
+:custom3.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x6 & rd & rs1
+{
+ rd = custom3.rd.rs1(rs1);
+}
+
+:custom3.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x7 & rd & rs1 & rs2
+{
+ rd = custom3.rd.rs1.rs2(rs1, rs2);
+}
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec
deleted file mode 100644
index 58d9312de3..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec
+++ /dev/null
@@ -1,12 +0,0 @@
-define endian=little;
-
-@define XLEN 4
-@define XLEN2 8
-@define FLEN 0
-
-@define ADDRSIZE "32"
-@define FPSIZE ""
-
-@include "riscv.reg.sinc"
-@include "riscv.table.sinc"
-@include "riscv.instr.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
index c8157a3f5e..81dbf0589f 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec
@@ -4,6 +4,9 @@ define endian=little;
@define XLEN2 8
@define FLEN 8
+@define MXLEN_1 31
+@define MXLEN_2 30
+
@define ADDRSIZE "32"
@define FPSIZE "64"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec
deleted file mode 100644
index 6838e4d0d9..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec
+++ /dev/null
@@ -1,12 +0,0 @@
-define endian=little;
-
-@define XLEN 4
-@define XLEN2 8
-@define FLEN 4
-
-@define ADDRSIZE "32"
-@define FPSIZE "32"
-
-@include "riscv.reg.sinc"
-@include "riscv.table.sinc"
-@include "riscv.instr.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
index 77c6c9f1ab..743bdbaf39 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc
@@ -1,27 +1,54 @@
# This is just a top level to include the standards
+@if ADDRSIZE == "32" || ADDRSIZE == "64" || ADDRSIZE == "128"
@include "riscv.rv32i.sinc"
@include "riscv.rv32a.sinc"
-@include "riscv.rv32d.sinc"
-@include "riscv.rv32f.sinc"
@include "riscv.rv32m.sinc"
-@include "riscv.rv32q.sinc"
+@include "riscv.rv32b.sinc"
+@include "riscv.rv32p.sinc"
+@include "riscv.rv32k.sinc"
-@if ADDRSIZE == "64"
+@if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128"
+@include "riscv.rv32f.sinc"
+@endif
+
+@if FPSIZE == "64" || FPSIZE == "128"
+@include "riscv.rv32d.sinc"
+@endif
+
+@if FPSIZE == "128"
+@include "riscv.rv32q.sinc"
+@endif
+@endif
+
+@if ADDRSIZE == "64" || ADDRSIZE == "128"
@include "riscv.rv64i.sinc"
@include "riscv.rv64a.sinc"
-@include "riscv.rv64d.sinc"
-@include "riscv.rv64f.sinc"
@include "riscv.rv64m.sinc"
+@include "riscv.rv64b.sinc"
+@include "riscv.rv64p.sinc"
+@include "riscv.rv64k.sinc"
+
+@if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128"
+@include "riscv.rv64f.sinc"
+@endif
+
+@if FPSIZE == "64" || FPSIZE == "128"
+@include "riscv.rv64d.sinc"
+@endif
+
+@if FPSIZE == "128"
@include "riscv.rv64q.sinc"
@endif
+@endif
@include "riscv.csr.sinc"
@include "riscv.priv.sinc"
@include "riscv.rvc.sinc"
+@include "riscv.rvv.sinc"
@include "riscv.zi.sinc"
-
+@include "riscv.custom.sinc"
# todos that may be possible, mostly just artifacts from my
# script to generate the initial SELIGH
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
index 422cf7b888..fd84f1f2cf 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
@@ -7,7 +7,7 @@
size="64"
variant="RV64I"
version="1.1"
- slafile="riscv.lp64.sla"
+ slafile="riscv.lp64d.sla"
processorspec="RV64I.pspec"
id="RISCV:LE:64:RV64I">
RISC-V 64 little base
@@ -19,7 +19,7 @@
size="64"
variant="RV64IC"
version="1.1"
- slafile="riscv.lp64.sla"
+ slafile="riscv.lp64d.sla"
processorspec="RV64IC.pspec"
id="RISCV:LE:64:RV64IC">
RISC-V 64 little base compressed
@@ -36,7 +36,7 @@
id="RISCV:LE:64:RV64G">
RISC-V 64 little general purpose
-
+
RISC-V 64 little general purpose compressed
-
+
RISC-V 32 little default
-
+
RISC-V 32 little base
@@ -79,7 +79,7 @@
size="32"
variant="RV32IC"
version="1.1"
- slafile="riscv.ilp32.sla"
+ slafile="riscv.ilp32d.sla"
processorspec="RV32IC.pspec"
id="RISCV:LE:32:RV32IC">
RISC-V 32 little base compressed
@@ -91,7 +91,7 @@
size="32"
variant="RV32IMC"
version="1.1"
- slafile="riscv.ilp32.sla"
+ slafile="riscv.ilp32d.sla"
processorspec="RV32IMC.pspec"
id="RISCV:LE:32:RV32IMC">
RISC-V 32 little base compressed
@@ -108,7 +108,7 @@
id="RISCV:LE:32:RV32G">
RISC-V 32 little general purpose
-
+
RISC-V 32 little general purpose compressed
-
+
RISC-V 32 little default
-
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec
deleted file mode 100644
index 3b083a32a0..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec
+++ /dev/null
@@ -1,12 +0,0 @@
-define endian=little;
-
-@define XLEN 8
-@define XLEN2 16
-@define FLEN 0
-
-@define ADDRSIZE "64"
-@define FPSIZE ""
-
-@include "riscv.reg.sinc"
-@include "riscv.table.sinc"
-@include "riscv.instr.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
index a67d8e65bd..c07b5382ed 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec
@@ -4,6 +4,9 @@ define endian=little;
@define XLEN2 16
@define FLEN 8
+@define MXLEN_1 63
+@define MXLEN_2 62
+
@define ADDRSIZE "64"
@define FPSIZE "64"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec
deleted file mode 100644
index 731d749fa4..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec
+++ /dev/null
@@ -1,12 +0,0 @@
-define endian=little;
-
-@define XLEN 8
-@define XLEN2 16
-@define FLEN 4
-
-@define ADDRSIZE "64"
-@define FPSIZE "32"
-
-@include "riscv.reg.sinc"
-@include "riscv.table.sinc"
-@include "riscv.instr.sinc"
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc
index 8bd5bf6854..935adfbbab 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc
@@ -1,33 +1,47 @@
# RISC-V Privileged Instructions
+define pcodeop dret;
+define pcodeop hret;
+define pcodeop mret;
+define pcodeop sret;
+define pcodeop uret;
+define pcodeop wfi;
+define pcodeop sfence.vm;
+define pcodeop sfence.vma;
+
# Trap-Return
# dret 7b200073 ffffffff SIMPLE (0, 0)
:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640
{
+ dret();
}
# hret 20200073 ffffffff SIMPLE (0, 0)
:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040
{
+ hret();
}
# mret 30200073 ffffffff SIMPLE (0, 0)
:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040
{
+ mret();
}
# sret 10200073 ffffffff SIMPLE (0, 0)
:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040
{
+ sret();
}
# uret 00200073 ffffffff SIMPLE (0, 0)
:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40
{
+ uret();
}
@@ -36,6 +50,7 @@
# wfi 10500073 ffffffff SIMPLE (0, 0)
:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0
{
+ wfi();
}
@@ -44,20 +59,92 @@
# sfence.vm 10400073 ffffffff SIMPLE (0, 0)
:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080
{
+ sfence.vm();
}
# sfence.vm s 10400073 fff07fff SIMPLE (0, 0)
:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104
{
+ sfence.vm(rs1);
}
# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0)
:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9
{
+ sfence.vma(rs1, rs2);
}
# Hypervisor Memory-Management
-#TODO
+#TODO move to rv32h and rv64h?
+
+:hlv.b rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x0
+{
+ rd = sext(*[ram]:1 rs1);
+}
+
+:hlv.bu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x1
+{
+ rd = zext(*[ram]:1 rs1);
+}
+
+:hlv.h rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x0
+{
+ rd = sext(*[ram]:2 rs1);
+}
+
+:hlv.hu rd,rs1, is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x1
+{
+ rd = zext(*[ram]:2 rs1);
+}
+
+:hlvx.hu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x3
+{
+ rd = zext(*[ram]:2 rs1);
+}
+
+:hlv.w rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x0
+{
+ assignW(rd, *[ram]:4 rs1);
+}
+
+:hlvx.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x3
+{
+ zassignW(rd, *[ram]:4 rs1);
+}
+
+:hsv.b rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x31 & op0711=0x0 & rs1 & rs2
+{
+ *[ram]:1 rs1 = rs2:1;
+}
+
+:hsv.h rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x33 & op0711=0x0 & rs1 & rs2
+{
+ *[ram]:2 rs1 = rs2:2;
+}
+
+:hsv.w rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x35 & op0711=0x0 & rs1 & rs2
+{
+ *[ram]:4 rs1 = rs2:4;
+}
+
+@if ADDRSIZE == "64"
+
+:hlv.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x1
+{
+ rd = zext(*[ram]:4 rs1);
+}
+
+:hlv.d rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x36 & rs1 & rd & op2024=0x0
+{
+ rd = *[ram]:8 rs1;
+}
+
+:hsv.d rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x37 & op0711=0x0 & rs1 & rs2
+{
+ *[ram]:8 rs1 = rs2;
+}
+
+@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
index a8ee148fae..360bd7e9ea 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
@@ -4,46 +4,6 @@ define alignment=2;
define space ram type=ram_space size=$(XLEN) default;
define space register type=register_space size=4;
-
-# A - Atomic instructions
-# B - Bit manipulation instructions
-# C - Compressed instructions
-# D - Double-precision floating-point instructions
-# E - Embedded applications, resource-constrained subset
-# F - Single-precision floating-point instructions
-# G - General (I + M + A + F + D)
-# I - Integer base instructions
-# J - Dynamically translated languages
-# L - Decimal floating point instructions
-# M - Integer multiplication and division instructions
-# N - User-level interrupt instructions
-# P - Packed-SIMD instructions
-# Q - Quad-precision floating-point instructions
-# T - Transactional Memory instructions
-# V - Vector operations instructions
-# RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N
-define register offset=0x1020 size=8 extensions;
-define context extensions
- RVI=(0,0)
- RVM=(1,1)
- RVA=(2,2)
- RVF=(3,3)
- RVD=(4,4)
- RVG=(0,4)
- RVQ=(5,5)
- RVL=(6,6)
- RVC=(7,7)
- RVB=(8,8)
- RVJ=(9,9)
- RVT=(10,10)
- RVP=(11,11)
- RVV=(12,12)
- RVN=(13,13)
- RV128=(61,61)
- RV64=(62,62)
- RV32=(63,63)
-;
-
define register offset=0x1000 size=$(XLEN) [ pc ];
@@ -73,30 +33,618 @@ define register offset=0x1018 size=1 [ RESERVE ];
define register offset=0x101C size=1 [ RESERVE_LENGTH ];
#TODO FIXME
-
+#ATTN RV32E is the same instruction-set encoding, but only defines x0-x15
# x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15
# z ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5
# x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31
# a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6
+# register numbers 0x1000-0x101f
define register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2
s0 s1 a0 a1 a2 a3 a4 a5
a6 a7 s2 s3 s4 s5 s6 s7
s8 s9 s10 s11 t3 t4 t5 t6 ];
-@if FPSIZE != ""
+@if FPSIZE != "0"
+# register numbers 0x1020-0x103f
define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7
fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7
fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
@endif
+#TODO fix
+@define VLEN "256"
+define register offset=0x4000 size=$(VLEN) [ v0 v1 v2 v3 v4 v5 v6 v7
+ v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23
+ v24 v25 v26 v27 v28 v29 v30 v31 ];
+
+
+define register offset=0x90000000 size=$(XLEN) [
+ ustatus fflags frm fcsr uie utvec csr006 csr007
+ vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr
+ csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017
+ csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f
+ csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027
+ csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f
+ csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037
+ csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f
+ uscratch uepc ucause utval uip csr045 csr046 csr047
+ csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f
+ csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057
+ csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f
+ csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067
+ csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f
+ csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077
+ csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f
+ csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087
+ csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f
+ csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097
+ csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f
+ csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7
+ csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af
+ csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7
+ csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf
+ csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7
+ csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf
+ csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7
+ csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df
+ csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7
+ csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef
+ csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7
+ csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff
+ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107
+ csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f
+ csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117
+ csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f
+ csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
+ csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f
+ csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137
+ csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f
+ sscratch sepc scause stval sip csr145 csr146 csr147
+ csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f
+ csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157
+ csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f
+ csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
+ csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f
+ csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177
+ csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f
+ satp csr181 csr182 csr183 csr184 csr185 csr186 csr187
+ csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f
+ csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197
+ csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f
+ csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7
+ csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af
+ csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7
+ csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf
+ csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7
+ csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf
+ csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7
+ csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df
+ csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7
+ csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef
+ csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7
+ csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff
+ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207
+ csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f
+ csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217
+ csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f
+ csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227
+ csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f
+ csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237
+ csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f
+ vsscratch vsepc vscause vstval vsip csr245 csr246 csr247
+ csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f
+ csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257
+ csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f
+ csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267
+ csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f
+ csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277
+ csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f
+ vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287
+ csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f
+ csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297
+ csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f
+ csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7
+ csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af
+ csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7
+ csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf
+ csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7
+ csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf
+ csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7
+ csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df
+ csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7
+ csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef
+ csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7
+ csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff
+ mstatus misa medeleg mideleg mie mtvec mcounteren csr307
+ csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f
+ mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317
+ csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f
+ mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7
+ mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
+ mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23
+ mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
+ mscratch mepc mcause mtval mip csr345 csr346 csr347
+ csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f
+ csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357
+ csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f
+ csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367
+ csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f
+ csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377
+ csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f
+ mbase mbound mibase mibound mdbase mdbound csr386 csr387
+ csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f
+ csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397
+ csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f
+ pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7
+ pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15
+ pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7
+ pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
+ pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23
+ pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31
+ pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39
+ pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47
+ pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55
+ pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63
+ csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7
+ csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff
+ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407
+ csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f
+ csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417
+ csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f
+ csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427
+ csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f
+ csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437
+ csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f
+ csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447
+ csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f
+ csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457
+ csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f
+ csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467
+ csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f
+ csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477
+ csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f
+ csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487
+ csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f
+ csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497
+ csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f
+ csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7
+ csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af
+ csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7
+ csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf
+ csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7
+ csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf
+ csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7
+ csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df
+ csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7
+ csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef
+ csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7
+ csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff
+ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507
+ csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f
+ csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517
+ csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f
+ csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527
+ csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f
+ csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537
+ csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f
+ csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547
+ csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f
+ csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557
+ csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f
+ csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567
+ csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f
+ csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577
+ csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f
+ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587
+ csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f
+ csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597
+ csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f
+ csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7
+ scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af
+ csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7
+ csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf
+ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7
+ csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf
+ csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7
+ csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df
+ csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7
+ csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef
+ csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7
+ csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff
+ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie
+ csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f
+ csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617
+ csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f
+ csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627
+ csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f
+ csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637
+ csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f
+ csr640 csr641 csr642 htval hip hvip csr646 csr647
+ csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f
+ csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657
+ csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f
+ csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667
+ csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f
+ csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677
+ csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f
+ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687
+ csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f
+ csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697
+ csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f
+ csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7
+ hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af
+ csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7
+ csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf
+ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7
+ csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf
+ csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7
+ csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df
+ csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7
+ csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef
+ csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7
+ csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff
+ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707
+ csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f
+ csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717
+ csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f
+ csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727
+ csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f
+ csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737
+ csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f
+ csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747
+ csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f
+ csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757
+ csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f
+ csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767
+ csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f
+ csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777
+ csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f
+ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787
+ csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f
+ csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797
+ csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f
+ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7
+ mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af
+ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7
+ csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf
+ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7
+ csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf
+ csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7
+ csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df
+ csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7
+ csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef
+ csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7
+ csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff
+ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807
+ csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f
+ csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817
+ csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f
+ csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827
+ csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f
+ csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837
+ csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f
+ csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847
+ csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f
+ csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857
+ csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f
+ csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867
+ csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f
+ csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877
+ csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f
+ csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887
+ csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f
+ csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897
+ csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f
+ csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7
+ csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af
+ csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7
+ csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf
+ csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7
+ csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf
+ csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7
+ csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df
+ csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7
+ csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef
+ csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7
+ csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff
+ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907
+ csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f
+ csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917
+ csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f
+ csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927
+ csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f
+ csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937
+ csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f
+ csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947
+ csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f
+ csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957
+ csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f
+ csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967
+ csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f
+ csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977
+ csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f
+ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987
+ csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f
+ csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997
+ csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f
+ csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7
+ csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af
+ csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7
+ csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf
+ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7
+ csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf
+ csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7
+ csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df
+ csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7
+ csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef
+ csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7
+ csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff
+ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07
+ csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f
+ csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17
+ csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f
+ csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27
+ csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f
+ csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37
+ csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f
+ csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47
+ csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f
+ csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57
+ csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f
+ csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67
+ csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f
+ csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77
+ csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f
+ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87
+ csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f
+ csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97
+ csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f
+ csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7
+ csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf
+ csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7
+ csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf
+ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7
+ csrac8 csrac9 csraca csracb csracc csracd csrace csracf
+ csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7
+ csrad8 csrad9 csrada csradb csradc csradd csrade csradf
+ csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7
+ csrae8 csrae9 csraea csraeb csraec csraed csraee csraef
+ csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7
+ csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff
+ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7
+ mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
+ mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23
+ mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
+ csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27
+ csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f
+ csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37
+ csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f
+ csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47
+ csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f
+ csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57
+ csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f
+ csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67
+ csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f
+ csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77
+ csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f
+ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h
+ mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h
+ mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h
+ mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h
+ csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7
+ csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf
+ csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7
+ csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf
+ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7
+ csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf
+ csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7
+ csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf
+ csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7
+ csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef
+ csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7
+ csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff
+ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7
+ hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
+ hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23
+ hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
+ vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27
+ csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f
+ csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37
+ csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f
+ csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47
+ csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f
+ csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57
+ csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f
+ csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67
+ csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f
+ csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77
+ csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f
+ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h
+ hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
+ hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h
+ hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
+ csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7
+ csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf
+ csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7
+ csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf
+ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7
+ csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf
+ csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7
+ csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf
+ csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7
+ csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef
+ csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7
+ csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff
+ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07
+ csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f
+ csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17
+ csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f
+ csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27
+ csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f
+ csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37
+ csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f
+ csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47
+ csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f
+ csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57
+ csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f
+ csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67
+ csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f
+ csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77
+ csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f
+ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87
+ csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f
+ csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97
+ csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f
+ csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7
+ csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf
+ csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7
+ csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf
+ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7
+ csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf
+ csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7
+ csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf
+ csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7
+ csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef
+ csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7
+ csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff
+ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07
+ csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f
+ csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17
+ csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f
+ csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27
+ csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f
+ csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37
+ csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f
+ csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47
+ csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f
+ csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57
+ csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f
+ csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67
+ csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f
+ csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77
+ csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f
+ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87
+ csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f
+ csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97
+ csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f
+ csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7
+ csrea8 csrea9 csreaa csreab csreac csread csreae csreaf
+ csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7
+ csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf
+ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7
+ csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf
+ csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7
+ csred8 csred9 csreda csredb csredc csredd csrede csredf
+ csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7
+ csree8 csree9 csreea csreeb csreec csreed csreee csreef
+ csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7
+ csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff
+ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07
+ csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f
+ csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17
+ csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f
+ csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27
+ csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f
+ csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37
+ csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f
+ csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47
+ csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f
+ csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57
+ csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f
+ csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67
+ csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f
+ csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77
+ csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f
+ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87
+ csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f
+ csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97
+ csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f
+ csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7
+ csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf
+ csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7
+ csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf
+ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7
+ csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf
+ csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7
+ csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf
+ csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7
+ csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef
+ csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7
+ csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff
+];
+
+
+# SEE 3.1.1 Machine ISA Register misa
+# (MXLEN-1, MXLEN-2) MXL - Machine XLEN {1: 32, 2: 64, 3: 128}
+# Bit Character Description
+# 0 A Atomic extension
+# 1 B Tentatively reserved for Bit-Manipulation extension
+# 2 C Compressed extension
+# 3 D Double-precision floating-point extension
+# 4 E RV32E base ISA
+# 5 F Single-precision floating-point extension
+# 6 G Additional standard extensions present
+# 7 H Hypervisor extension
+# 8 I RV32I/64I/128I base ISA
+# 9 J Tentatively reserved for Dynamically Translated Languages extension
+# 10 K Reserved
+# 11 L Tentatively reserved for Decimal Floating-Point extension
+# 12 M Integer Multiply/Divide extension
+# 13 N User-level interrupts supported
+# 14 O Reserved
+# 15 P Tentatively reserved for Packed-SIMD extension
+# 16 Q Quad-precision floating-point extension
+# 17 R Reserved
+# 18 S Supervisor mode implemented
+# 19 T Tentatively reserved for Transactional Memory extension
+# 20 U User mode implemented
+# 21 V Tentatively reserved for Vector extension
+# 22 W Reserved
+# 23 X Non-standard extensions present
+# 24 Y Reserved
+# 25 Z Reserved
+define context misa
+ RVA=(0,0)
+ RVB=(1,1)
+ RVC=(2,2)
+ RVD=(3,3)
+ RVE=(4,4)
+ RVF=(5,5)
+ RVG=(6,6)
+ RVH=(7,7)
+ RVI=(8,8)
+ RVJ=(9,9)
+ RVK=(10,10)
+ RVL=(11,11)
+ RVM=(12,12)
+ RVN=(13,13)
+ RVO=(14,14)
+ RVP=(15,15)
+ RVQ=(16,16)
+ RVR=(17,17)
+ RVS=(18,18)
+ RVT=(19,19)
+ RVU=(20,20)
+ RVV=(21,21)
+ RVW=(22,22)
+ RVX=(23,23)
+ RVY=(24,24)
+ RVZ=(25,25)
+ MXL=($(MXLEN_2), $(MXLEN_1))
+;
+
+
define token instr (32)
op0001=(0,1)
+ op0006=(0,6)
op0204=(2,4)
op0506=(5,6)
op0707=(7,7)
op0711=(7,11)
r0711=(7,11)
fr0711=(7,11)
+ v0711=(7,11)
op0811=(8,11)
op1214=(12,14)
funct3=(12,14)
@@ -104,15 +652,23 @@ define token instr (32)
op1231=(12,31)
sop1231=(12,31) signed
op1519=(15,19)
+ sop1519=(15,19) signed
+ subf5=(15,19)
r1519=(15,19)
fr1519=(15,19)
+ v1519=(15,19)
op1527=(15,27)
op1531=(15,31)
op2020=(20,20)
+ op2022=(20,22)
succ=(20,23)
+ op2023=(20,23)
op2024=(20,24)
r2024=(20,24)
fr2024=(20,24)
+ v2024=(20,24)
+ op2025=(20,25)
+ op2026=(20,26)
csr_0=(20,27)
csr_1=(20,27)
csr_2=(20,27)
@@ -151,28 +707,38 @@ define token instr (32)
csr_F0=(20,26)
csr_F8=(20,25)
csr_FC=(20,25)
+ op2030=(20,30)
op2031=(20,31)
sop2031=(20,31) signed
op2130=(21,30)
+ op2324=(23,24)
+ op2424=(24,24)
op2427=(24,27)
pred=(24,27)
op2525=(25,25)
op2526=(25,26)
op2527=(25,27)
+ op2529=(25,29)
op2530=(25,30)
op2531=(25,31)
sop2531=(25,31) signed
funct7=(25,31)
+ wd=(26,26)
+ op2626=(26,26)
op2627=(26,27)
op2631=(26,31)
op2731=(27,31)
+ amoop=(27,31)
funct5=(27,31)
op2727=(27,27)
r2731=(27,31)
fr2731=(27,31)
+ op2828=(28,28)
op2829=(28,29)
fm=(28,31)
+ op2931=(29,31)
op3031=(30,31)
+ op3131=(31,31)
sop3131=(31,31) signed
;
@@ -233,7 +799,7 @@ attach variables [ cr0204s cr0709s cd0709s ]
[ s0 s1 a0 a1 a2 a3 a4 a5 ];
-@if FPSIZE != ""
+@if FPSIZE != "0"
attach variables [ fr0711 fr1519 fr2024 fr2731 ]
[ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5
fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ];
@@ -247,547 +813,558 @@ attach variables [ cfr0204s cfr0709s ]
@endif
-#TODO this approach is probably incorrect
-define register offset=0x90000000 size=$(XLEN) [ ustatus ];
-define register offset=0x90000010 size=$(XLEN) [ fflags ];
-define register offset=0x90000020 size=$(XLEN) [ frm ];
-define register offset=0x90000030 size=$(XLEN) [ fcsr ];
-define register offset=0x90000040 size=$(XLEN) [ uie ];
-define register offset=0x90000050 size=$(XLEN) [ utvec ];
-define register offset=0x90000400 size=$(XLEN) [ uscratch ];
-define register offset=0x90000410 size=$(XLEN) [ uepc ];
-define register offset=0x90000420 size=$(XLEN) [ ucause ];
-define register offset=0x90000430 size=$(XLEN) [ utval ];
-define register offset=0x90000440 size=$(XLEN) [ uip ];
-define register offset=0x90001000 size=$(XLEN) [ sstatus ];
-define register offset=0x90001020 size=$(XLEN) [ sedeleg ];
-define register offset=0x90001030 size=$(XLEN) [ sideleg ];
-define register offset=0x90001040 size=$(XLEN) [ sie ];
-define register offset=0x90001050 size=$(XLEN) [ stvec ];
-define register offset=0x90001060 size=$(XLEN) [ scounteren ];
-define register offset=0x90001400 size=$(XLEN) [ sscratch ];
-define register offset=0x90001410 size=$(XLEN) [ sepc ];
-define register offset=0x90001420 size=$(XLEN) [ scause ];
-define register offset=0x90001430 size=$(XLEN) [ stval ];
-define register offset=0x90001440 size=$(XLEN) [ sip ];
-define register offset=0x90001800 size=$(XLEN) [ satp ];
-define register offset=0x90002000 size=$(XLEN) [ vsstatus ];
-define register offset=0x90002040 size=$(XLEN) [ vsie ];
-define register offset=0x90002050 size=$(XLEN) [ vstvec ];
-define register offset=0x90002400 size=$(XLEN) [ vsscratch ];
-define register offset=0x90002410 size=$(XLEN) [ vsepc ];
-define register offset=0x90002420 size=$(XLEN) [ vscause ];
-define register offset=0x90002430 size=$(XLEN) [ vstval ];
-define register offset=0x90002440 size=$(XLEN) [ vsip ];
-define register offset=0x90002800 size=$(XLEN) [ vsatp ];
-define register offset=0x90003000 size=$(XLEN) [ mstatus ];
-define register offset=0x90003010 size=$(XLEN) [ misa ];
-define register offset=0x90003020 size=$(XLEN) [ medeleg ];
-define register offset=0x90003030 size=$(XLEN) [ mideleg ];
-define register offset=0x90003040 size=$(XLEN) [ mie ];
-define register offset=0x90003050 size=$(XLEN) [ mtvec ];
-define register offset=0x90003060 size=$(XLEN) [ mcounteren ];
-define register offset=0x90003100 size=$(XLEN) [ mstatush ];
-define register offset=0x90003200 size=$(XLEN) [ mucounteren ];
-define register offset=0x90003210 size=$(XLEN) [ mscounteren ];
-define register offset=0x90003220 size=$(XLEN) [ mhcounteren ];
-define register offset=0x90003400 size=$(XLEN) [ mscratch ];
-define register offset=0x90003410 size=$(XLEN) [ mepc ];
-define register offset=0x90003420 size=$(XLEN) [ mcause ];
-define register offset=0x90003430 size=$(XLEN) [ mtval ];
-define register offset=0x90003440 size=$(XLEN) [ mip ];
-define register offset=0x90003800 size=$(XLEN) [ mbase ];
-define register offset=0x90003810 size=$(XLEN) [ mbound ];
-define register offset=0x90003820 size=$(XLEN) [ mibase ];
-define register offset=0x90003830 size=$(XLEN) [ mibound ];
-define register offset=0x90003840 size=$(XLEN) [ mdbase ];
-define register offset=0x90003850 size=$(XLEN) [ mdbound ];
-define register offset=0x90003a00 size=$(XLEN) [ pmpcfg0 ];
-define register offset=0x90003a10 size=$(XLEN) [ pmpcfg1 ];
-define register offset=0x90003a20 size=$(XLEN) [ pmpcfg2 ];
-define register offset=0x90003a30 size=$(XLEN) [ pmpcfg3 ];
-define register offset=0x90003b00 size=$(XLEN) [ pmpaddr0 ];
-define register offset=0x90003b10 size=$(XLEN) [ pmpaddr1 ];
-define register offset=0x90003b20 size=$(XLEN) [ pmpaddr2 ];
-define register offset=0x90003b30 size=$(XLEN) [ pmpaddr3 ];
-define register offset=0x90003b40 size=$(XLEN) [ pmpaddr4 ];
-define register offset=0x90003b50 size=$(XLEN) [ pmpaddr5 ];
-define register offset=0x90003b60 size=$(XLEN) [ pmpaddr6 ];
-define register offset=0x90003b70 size=$(XLEN) [ pmpaddr7 ];
-define register offset=0x90003b80 size=$(XLEN) [ pmpaddr8 ];
-define register offset=0x90003b90 size=$(XLEN) [ pmpaddr9 ];
-define register offset=0x90003ba0 size=$(XLEN) [ pmpaddr10 ];
-define register offset=0x90003bb0 size=$(XLEN) [ pmpaddr11 ];
-define register offset=0x90003bc0 size=$(XLEN) [ pmpaddr12 ];
-define register offset=0x90003bd0 size=$(XLEN) [ pmpaddr13 ];
-define register offset=0x90003be0 size=$(XLEN) [ pmpaddr14 ];
-define register offset=0x90003bf0 size=$(XLEN) [ pmpaddr15 ];
-define register offset=0x90006000 size=$(XLEN) [ hstatus ];
-define register offset=0x90006020 size=$(XLEN) [ hedeleg ];
-define register offset=0x90006030 size=$(XLEN) [ hideleg ];
-define register offset=0x90006060 size=$(XLEN) [ hcounteren ];
-define register offset=0x90006800 size=$(XLEN) [ hgatp ];
-define register offset=0x90007a00 size=$(XLEN) [ tselect ];
-define register offset=0x90007a10 size=$(XLEN) [ tdata1 ];
-define register offset=0x90007a20 size=$(XLEN) [ tdata2 ];
-define register offset=0x90007a30 size=$(XLEN) [ tdata3 ];
-define register offset=0x90007b00 size=$(XLEN) [ dcsr ];
-define register offset=0x90007b10 size=$(XLEN) [ dpc ];
-define register offset=0x90007b20 size=$(XLEN) [ dscratch0 ];
-define register offset=0x90007b30 size=$(XLEN) [ dscratch1 ];
-define register offset=0x9000b000 size=$(XLEN) [ mcycle ];
-define register offset=0x9000b020 size=$(XLEN) [ minstret ];
-define register offset=0x9000b030 size=$(XLEN) [ mhpmcounter3 ];
-define register offset=0x9000b040 size=$(XLEN) [ mhpmcounter4 ];
-define register offset=0x9000b050 size=$(XLEN) [ mhpmcounter5 ];
-define register offset=0x9000b060 size=$(XLEN) [ mhpmcounter6 ];
-define register offset=0x9000b070 size=$(XLEN) [ mhpmcounter7 ];
-define register offset=0x9000b080 size=$(XLEN) [ mhpmcounter8 ];
-define register offset=0x9000b090 size=$(XLEN) [ mhpmcounter9 ];
-define register offset=0x9000b0a0 size=$(XLEN) [ mhpmcounter10 ];
-define register offset=0x9000b0b0 size=$(XLEN) [ mhpmcounter11 ];
-define register offset=0x9000b0c0 size=$(XLEN) [ mhpmcounter12 ];
-define register offset=0x9000b0d0 size=$(XLEN) [ mhpmcounter13 ];
-define register offset=0x9000b0e0 size=$(XLEN) [ mhpmcounter14 ];
-define register offset=0x9000b0f0 size=$(XLEN) [ mhpmcounter15 ];
-define register offset=0x9000b100 size=$(XLEN) [ mhpmcounter16 ];
-define register offset=0x9000b110 size=$(XLEN) [ mhpmcounter17 ];
-define register offset=0x9000b120 size=$(XLEN) [ mhpmcounter18 ];
-define register offset=0x9000b130 size=$(XLEN) [ mhpmcounter19 ];
-define register offset=0x9000b140 size=$(XLEN) [ mhpmcounter20 ];
-define register offset=0x9000b150 size=$(XLEN) [ mhpmcounter21 ];
-define register offset=0x9000b160 size=$(XLEN) [ mhpmcounter22 ];
-define register offset=0x9000b170 size=$(XLEN) [ mhpmcounter23 ];
-define register offset=0x9000b180 size=$(XLEN) [ mhpmcounter24 ];
-define register offset=0x9000b190 size=$(XLEN) [ mhpmcounter25 ];
-define register offset=0x9000b1a0 size=$(XLEN) [ mhpmcounter26 ];
-define register offset=0x9000b1b0 size=$(XLEN) [ mhpmcounter27 ];
-define register offset=0x9000b1c0 size=$(XLEN) [ mhpmcounter28 ];
-define register offset=0x9000b1d0 size=$(XLEN) [ mhpmcounter29 ];
-define register offset=0x9000b1e0 size=$(XLEN) [ mhpmcounter30 ];
-define register offset=0x9000b1f0 size=$(XLEN) [ mhpmcounter31 ];
-define register offset=0x9000b200 size=$(XLEN) [ mcountinhibit ];
-define register offset=0x9000b230 size=$(XLEN) [ mhpmevent3 ];
-define register offset=0x9000b240 size=$(XLEN) [ mhpmevent4 ];
-define register offset=0x9000b250 size=$(XLEN) [ mhpmevent5 ];
-define register offset=0x9000b260 size=$(XLEN) [ mhpmevent6 ];
-define register offset=0x9000b270 size=$(XLEN) [ mhpmevent7 ];
-define register offset=0x9000b280 size=$(XLEN) [ mhpmevent8 ];
-define register offset=0x9000b290 size=$(XLEN) [ mhpmevent9 ];
-define register offset=0x9000b2a0 size=$(XLEN) [ mhpmevent10 ];
-define register offset=0x9000b2b0 size=$(XLEN) [ mhpmevent11 ];
-define register offset=0x9000b2c0 size=$(XLEN) [ mhpmevent12 ];
-define register offset=0x9000b2d0 size=$(XLEN) [ mhpmevent13 ];
-define register offset=0x9000b2e0 size=$(XLEN) [ mhpmevent14 ];
-define register offset=0x9000b2f0 size=$(XLEN) [ mhpmevent15 ];
-define register offset=0x9000b300 size=$(XLEN) [ mhpmevent16 ];
-define register offset=0x9000b310 size=$(XLEN) [ mhpmevent17 ];
-define register offset=0x9000b320 size=$(XLEN) [ mhpmevent18 ];
-define register offset=0x9000b330 size=$(XLEN) [ mhpmevent19 ];
-define register offset=0x9000b340 size=$(XLEN) [ mhpmevent20 ];
-define register offset=0x9000b350 size=$(XLEN) [ mhpmevent21 ];
-define register offset=0x9000b360 size=$(XLEN) [ mhpmevent22 ];
-define register offset=0x9000b370 size=$(XLEN) [ mhpmevent23 ];
-define register offset=0x9000b380 size=$(XLEN) [ mhpmevent24 ];
-define register offset=0x9000b390 size=$(XLEN) [ mhpmevent25 ];
-define register offset=0x9000b3a0 size=$(XLEN) [ mhpmevent26 ];
-define register offset=0x9000b3b0 size=$(XLEN) [ mhpmevent27 ];
-define register offset=0x9000b3c0 size=$(XLEN) [ mhpmevent28 ];
-define register offset=0x9000b3d0 size=$(XLEN) [ mhpmevent29 ];
-define register offset=0x9000b3e0 size=$(XLEN) [ mhpmevent30 ];
-define register offset=0x9000b3f0 size=$(XLEN) [ mhpmevent31 ];
-define register offset=0x9000b800 size=$(XLEN) [ mcycleh ];
-define register offset=0x9000b820 size=$(XLEN) [ minstreth ];
-define register offset=0x9000b830 size=$(XLEN) [ mhpmcounter3h ];
-define register offset=0x9000b840 size=$(XLEN) [ mhpmcounter4h ];
-define register offset=0x9000b850 size=$(XLEN) [ mhpmcounter5h ];
-define register offset=0x9000b860 size=$(XLEN) [ mhpmcounter6h ];
-define register offset=0x9000b870 size=$(XLEN) [ mhpmcounter7h ];
-define register offset=0x9000b880 size=$(XLEN) [ mhpmcounter8h ];
-define register offset=0x9000b890 size=$(XLEN) [ mhpmcounter9h ];
-define register offset=0x9000b8a0 size=$(XLEN) [ mhpmcounter10h ];
-define register offset=0x9000b8b0 size=$(XLEN) [ mhpmcounter11h ];
-define register offset=0x9000b8c0 size=$(XLEN) [ mhpmcounter12h ];
-define register offset=0x9000b8d0 size=$(XLEN) [ mhpmcounter13h ];
-define register offset=0x9000b8e0 size=$(XLEN) [ mhpmcounter14h ];
-define register offset=0x9000b8f0 size=$(XLEN) [ mhpmcounter15h ];
-define register offset=0x9000b900 size=$(XLEN) [ mhpmcounter16h ];
-define register offset=0x9000b910 size=$(XLEN) [ mhpmcounter17h ];
-define register offset=0x9000b920 size=$(XLEN) [ mhpmcounter18h ];
-define register offset=0x9000b930 size=$(XLEN) [ mhpmcounter19h ];
-define register offset=0x9000b940 size=$(XLEN) [ mhpmcounter20h ];
-define register offset=0x9000b950 size=$(XLEN) [ mhpmcounter21h ];
-define register offset=0x9000b960 size=$(XLEN) [ mhpmcounter22h ];
-define register offset=0x9000b970 size=$(XLEN) [ mhpmcounter23h ];
-define register offset=0x9000b980 size=$(XLEN) [ mhpmcounter24h ];
-define register offset=0x9000b990 size=$(XLEN) [ mhpmcounter25h ];
-define register offset=0x9000b9a0 size=$(XLEN) [ mhpmcounter26h ];
-define register offset=0x9000b9b0 size=$(XLEN) [ mhpmcounter27h ];
-define register offset=0x9000b9c0 size=$(XLEN) [ mhpmcounter28h ];
-define register offset=0x9000b9d0 size=$(XLEN) [ mhpmcounter29h ];
-define register offset=0x9000b9e0 size=$(XLEN) [ mhpmcounter30h ];
-define register offset=0x9000b9f0 size=$(XLEN) [ mhpmcounter31h ];
-define register offset=0x9000c000 size=$(XLEN) [ cycle ];
-define register offset=0x9000c010 size=$(XLEN) [ time ];
-define register offset=0x9000c020 size=$(XLEN) [ instret ];
-define register offset=0x9000c030 size=$(XLEN) [ hpmcounter3 ];
-define register offset=0x9000c040 size=$(XLEN) [ hpmcounter4 ];
-define register offset=0x9000c050 size=$(XLEN) [ hpmcounter5 ];
-define register offset=0x9000c060 size=$(XLEN) [ hpmcounter6 ];
-define register offset=0x9000c070 size=$(XLEN) [ hpmcounter7 ];
-define register offset=0x9000c080 size=$(XLEN) [ hpmcounter8 ];
-define register offset=0x9000c090 size=$(XLEN) [ hpmcounter9 ];
-define register offset=0x9000c0a0 size=$(XLEN) [ hpmcounter10 ];
-define register offset=0x9000c0b0 size=$(XLEN) [ hpmcounter11 ];
-define register offset=0x9000c0c0 size=$(XLEN) [ hpmcounter12 ];
-define register offset=0x9000c0d0 size=$(XLEN) [ hpmcounter13 ];
-define register offset=0x9000c0e0 size=$(XLEN) [ hpmcounter14 ];
-define register offset=0x9000c0f0 size=$(XLEN) [ hpmcounter15 ];
-define register offset=0x9000c100 size=$(XLEN) [ hpmcounter16 ];
-define register offset=0x9000c110 size=$(XLEN) [ hpmcounter17 ];
-define register offset=0x9000c120 size=$(XLEN) [ hpmcounter18 ];
-define register offset=0x9000c130 size=$(XLEN) [ hpmcounter19 ];
-define register offset=0x9000c140 size=$(XLEN) [ hpmcounter20 ];
-define register offset=0x9000c150 size=$(XLEN) [ hpmcounter21 ];
-define register offset=0x9000c160 size=$(XLEN) [ hpmcounter22 ];
-define register offset=0x9000c170 size=$(XLEN) [ hpmcounter23 ];
-define register offset=0x9000c180 size=$(XLEN) [ hpmcounter24 ];
-define register offset=0x9000c190 size=$(XLEN) [ hpmcounter25 ];
-define register offset=0x9000c1a0 size=$(XLEN) [ hpmcounter26 ];
-define register offset=0x9000c1b0 size=$(XLEN) [ hpmcounter27 ];
-define register offset=0x9000c1c0 size=$(XLEN) [ hpmcounter28 ];
-define register offset=0x9000c1d0 size=$(XLEN) [ hpmcounter29 ];
-define register offset=0x9000c1e0 size=$(XLEN) [ hpmcounter30 ];
-define register offset=0x9000c1f0 size=$(XLEN) [ hpmcounter31 ];
-define register offset=0x9000c800 size=$(XLEN) [ cycleh ];
-define register offset=0x9000c810 size=$(XLEN) [ timeh ];
-define register offset=0x9000c820 size=$(XLEN) [ instreth ];
-define register offset=0x9000c830 size=$(XLEN) [ hpmcounter3h ];
-define register offset=0x9000c840 size=$(XLEN) [ hpmcounter4h ];
-define register offset=0x9000c850 size=$(XLEN) [ hpmcounter5h ];
-define register offset=0x9000c860 size=$(XLEN) [ hpmcounter6h ];
-define register offset=0x9000c870 size=$(XLEN) [ hpmcounter7h ];
-define register offset=0x9000c880 size=$(XLEN) [ hpmcounter8h ];
-define register offset=0x9000c890 size=$(XLEN) [ hpmcounter9h ];
-define register offset=0x9000c8a0 size=$(XLEN) [ hpmcounter10h ];
-define register offset=0x9000c8b0 size=$(XLEN) [ hpmcounter11h ];
-define register offset=0x9000c8c0 size=$(XLEN) [ hpmcounter12h ];
-define register offset=0x9000c8d0 size=$(XLEN) [ hpmcounter13h ];
-define register offset=0x9000c8e0 size=$(XLEN) [ hpmcounter14h ];
-define register offset=0x9000c8f0 size=$(XLEN) [ hpmcounter15h ];
-define register offset=0x9000c900 size=$(XLEN) [ hpmcounter16h ];
-define register offset=0x9000c910 size=$(XLEN) [ hpmcounter17h ];
-define register offset=0x9000c920 size=$(XLEN) [ hpmcounter18h ];
-define register offset=0x9000c930 size=$(XLEN) [ hpmcounter19h ];
-define register offset=0x9000c940 size=$(XLEN) [ hpmcounter20h ];
-define register offset=0x9000c950 size=$(XLEN) [ hpmcounter21h ];
-define register offset=0x9000c960 size=$(XLEN) [ hpmcounter22h ];
-define register offset=0x9000c970 size=$(XLEN) [ hpmcounter23h ];
-define register offset=0x9000c980 size=$(XLEN) [ hpmcounter24h ];
-define register offset=0x9000c990 size=$(XLEN) [ hpmcounter25h ];
-define register offset=0x9000c9a0 size=$(XLEN) [ hpmcounter26h ];
-define register offset=0x9000c9b0 size=$(XLEN) [ hpmcounter27h ];
-define register offset=0x9000c9c0 size=$(XLEN) [ hpmcounter28h ];
-define register offset=0x9000c9d0 size=$(XLEN) [ hpmcounter29h ];
-define register offset=0x9000c9e0 size=$(XLEN) [ hpmcounter30h ];
-define register offset=0x9000c9f0 size=$(XLEN) [ hpmcounter31h ];
-define register offset=0x9000f110 size=$(XLEN) [ mvendorid ];
-define register offset=0x9000f120 size=$(XLEN) [ marchid ];
-define register offset=0x9000f130 size=$(XLEN) [ mimpid ];
-define register offset=0x9000f140 size=$(XLEN) [ mhartid ];
+attach variables [ v0711 v1519 v2024 ]
+ [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];
attach variables [ csr_0 ]
- [ ustatus fflags frm fcsr uie utvec _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- uscratch uepc ucause utval uip _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ ustatus fflags frm fcsr uie utvec csr006 csr007
+ vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr
+ csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017
+ csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f
+ csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027
+ csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f
+ csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037
+ csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f
+ uscratch uepc ucause utval uip csr045 csr046 csr047
+ csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f
+ csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057
+ csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f
+ csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067
+ csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f
+ csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077
+ csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f
+ csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087
+ csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f
+ csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097
+ csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f
+ csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7
+ csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af
+ csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7
+ csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf
+ csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7
+ csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf
+ csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7
+ csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df
+ csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7
+ csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef
+ csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7
+ csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ];
attach variables [ csr_1 ]
- [ sstatus _ sedeleg sideleg sie stvec scounteren _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- sscratch sepc scause stval sip _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- satp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107
+ csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f
+ csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117
+ csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f
+ csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127
+ csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f
+ csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137
+ csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f
+ sscratch sepc scause stval sip csr145 csr146 csr147
+ csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f
+ csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157
+ csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f
+ csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167
+ csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f
+ csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177
+ csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f
+ satp csr181 csr182 csr183 csr184 csr185 csr186 csr187
+ csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f
+ csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197
+ csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f
+ csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7
+ csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af
+ csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7
+ csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf
+ csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7
+ csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf
+ csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7
+ csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df
+ csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7
+ csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef
+ csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7
+ csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ];
attach variables [ csr_2 ]
- [ vsstatus _ _ _ vsie vstvec _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- vsscratch vsepc vscause vstval vsip _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- vsatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207
+ csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f
+ csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217
+ csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f
+ csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227
+ csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f
+ csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237
+ csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f
+ vsscratch vsepc vscause vstval vsip csr245 csr246 csr247
+ csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f
+ csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257
+ csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f
+ csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267
+ csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f
+ csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277
+ csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f
+ vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287
+ csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f
+ csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297
+ csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f
+ csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7
+ csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af
+ csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7
+ csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf
+ csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7
+ csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf
+ csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7
+ csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df
+ csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7
+ csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef
+ csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7
+ csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ];
attach variables [ csr_3 ]
- [ mstatus misa medeleg mideleg mie mtvec mcounteren _ _ _ _ _ _ _ _ _
- mstatush _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- mscratch mepc mcause mtval mip _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 _ _ _ _ _ _ _ _ _ _ _ _
- pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307
+ csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f
+ mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317
+ csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f
+ mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7
+ mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
+ mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23
+ mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
+ mscratch mepc mcause mtval mip csr345 csr346 csr347
+ csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f
+ csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357
+ csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f
+ csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367
+ csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f
+ csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377
+ csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f
+ mbase mbound mibase mibound mdbase mdbound csr386 csr387
+ csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f
+ csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397
+ csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f
+ pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7
+ pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15
+ pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7
+ pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15
+ pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23
+ pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31
+ pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39
+ pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47
+ pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55
+ pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63
+ csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7
+ csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ];
attach variables [ csr_4 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407
+ csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f
+ csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417
+ csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f
+ csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427
+ csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f
+ csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437
+ csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f
+ csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447
+ csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f
+ csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457
+ csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f
+ csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467
+ csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f
+ csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477
+ csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f
+ csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487
+ csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f
+ csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497
+ csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f
+ csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7
+ csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af
+ csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7
+ csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf
+ csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7
+ csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf
+ csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7
+ csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df
+ csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7
+ csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef
+ csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7
+ csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ];
attach variables [ csr_50 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507
+ csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f
+ csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517
+ csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f
+ csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527
+ csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f
+ csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537
+ csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f
+ csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547
+ csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f
+ csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557
+ csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f
+ csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567
+ csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f
+ csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577
+ csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ];
attach variables [ csr_58 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587
+ csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f
+ csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597
+ csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f
+ csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7
+ scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af
+ csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7
+ csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ];
attach variables [ csr_5C ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7
+ csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf
+ csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7
+ csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df
+ csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7
+ csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef
+ csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7
+ csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ];
attach variables [ csr_60 ]
- [ hstatus _ hedeleg hideleg _ _ hcounteren _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie
+ csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f
+ csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617
+ csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f
+ csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627
+ csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f
+ csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637
+ csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f
+ csr640 csr641 csr642 htval hip hvip csr646 csr647
+ csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f
+ csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657
+ csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f
+ csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667
+ csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f
+ csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677
+ csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ];
attach variables [ csr_68 ]
- [ hgatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687
+ csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f
+ csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697
+ csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f
+ csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7
+ hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af
+ csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7
+ csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ];
attach variables [ csr_6C ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7
+ csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf
+ csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7
+ csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df
+ csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7
+ csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef
+ csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7
+ csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ];
attach variables [ csr_70 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707
+ csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f
+ csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717
+ csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f
+ csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727
+ csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f
+ csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737
+ csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f
+ csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747
+ csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f
+ csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757
+ csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f
+ csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767
+ csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f
+ csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777
+ csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ];
attach variables [ csr_78 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787
+ csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f
+ csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797
+ csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ];
attach variables [ csr_7A ]
- [ tselect tdata1 tdata2 tdata3 _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7
+ mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ];
attach variables [ csr_7B ]
- [ dcsr dpc dscratch0 dscratch1 _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7
+ csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ];
attach variables [ csr_7C ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7
+ csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf
+ csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7
+ csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df
+ csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7
+ csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef
+ csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7
+ csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ];
attach variables [ csr_8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807
+ csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f
+ csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817
+ csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f
+ csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827
+ csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f
+ csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837
+ csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f
+ csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847
+ csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f
+ csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857
+ csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f
+ csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867
+ csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f
+ csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877
+ csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f
+ csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887
+ csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f
+ csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897
+ csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f
+ csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7
+ csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af
+ csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7
+ csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf
+ csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7
+ csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf
+ csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7
+ csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df
+ csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7
+ csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef
+ csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7
+ csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ];
attach variables [ csr_90 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907
+ csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f
+ csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917
+ csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f
+ csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927
+ csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f
+ csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937
+ csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f
+ csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947
+ csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f
+ csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957
+ csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f
+ csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967
+ csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f
+ csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977
+ csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ];
attach variables [ csr_98 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987
+ csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f
+ csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997
+ csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f
+ csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7
+ csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af
+ csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7
+ csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ];
attach variables [ csr_9C ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7
+ csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf
+ csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7
+ csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df
+ csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7
+ csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef
+ csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7
+ csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ];
attach variables [ csr_A0 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07
+ csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f
+ csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17
+ csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f
+ csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27
+ csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f
+ csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37
+ csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f
+ csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47
+ csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f
+ csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57
+ csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f
+ csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67
+ csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f
+ csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77
+ csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ];
attach variables [ csr_A8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87
+ csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f
+ csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97
+ csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f
+ csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7
+ csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf
+ csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7
+ csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ];
attach variables [ csr_AC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7
+ csrac8 csrac9 csraca csracb csracc csracd csrace csracf
+ csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7
+ csrad8 csrad9 csrada csradb csradc csradd csrade csradf
+ csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7
+ csrae8 csrae9 csraea csraeb csraec csraed csraee csraef
+ csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7
+ csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ];
attach variables [ csr_B0 ]
- [ mcycle _ minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
- mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
- mcountinhibit _ _ mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15
- mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7
+ mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15
+ mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23
+ mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31
+ csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27
+ csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f
+ csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37
+ csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f
+ csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47
+ csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f
+ csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57
+ csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f
+ csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67
+ csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f
+ csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77
+ csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ];
attach variables [ csr_B8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h
+ mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h
+ mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h
+ mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h
+ csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7
+ csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf
+ csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7
+ csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ];
attach variables [ csr_BC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7
+ csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf
+ csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7
+ csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf
+ csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7
+ csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef
+ csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7
+ csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ];
attach variables [ csr_C0 ]
- [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
- hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7
+ hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15
+ hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23
+ hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31
+ vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27
+ csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f
+ csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37
+ csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f
+ csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47
+ csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f
+ csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57
+ csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f
+ csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67
+ csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f
+ csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77
+ csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ];
attach variables [ csr_C8 ]
- [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
- hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h
+ hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h
+ hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h
+ hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h
+ csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7
+ csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf
+ csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7
+ csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ];
attach variables [ csr_CC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7
+ csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf
+ csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7
+ csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf
+ csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7
+ csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef
+ csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7
+ csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ];
attach variables [ csr_D0 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07
+ csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f
+ csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17
+ csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f
+ csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27
+ csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f
+ csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37
+ csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f
+ csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47
+ csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f
+ csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57
+ csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f
+ csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67
+ csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f
+ csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77
+ csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ];
attach variables [ csr_D8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87
+ csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f
+ csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97
+ csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f
+ csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7
+ csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf
+ csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7
+ csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ];
attach variables [ csr_DC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7
+ csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf
+ csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7
+ csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf
+ csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7
+ csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef
+ csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7
+ csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ];
attach variables [ csr_E0 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07
+ csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f
+ csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17
+ csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f
+ csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27
+ csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f
+ csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37
+ csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f
+ csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47
+ csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f
+ csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57
+ csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f
+ csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67
+ csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f
+ csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77
+ csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ];
attach variables [ csr_E8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87
+ csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f
+ csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97
+ csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f
+ csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7
+ csrea8 csrea9 csreaa csreab csreac csread csreae csreaf
+ csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7
+ csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ];
attach variables [ csr_EC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7
+ csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf
+ csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7
+ csred8 csred9 csreda csredb csredc csredd csrede csredf
+ csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7
+ csree8 csree9 csreea csreeb csreec csreed csreee csreef
+ csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7
+ csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ];
attach variables [ csr_F0 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ mvendorid marchid mimpid mhartid _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07
+ csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f
+ csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17
+ csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f
+ csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27
+ csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f
+ csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37
+ csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f
+ csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47
+ csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f
+ csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57
+ csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f
+ csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67
+ csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f
+ csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77
+ csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ];
attach variables [ csr_F8 ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87
+ csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f
+ csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97
+ csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f
+ csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7
+ csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf
+ csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7
+ csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ];
attach variables [ csr_FC ]
- [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+ [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7
+ csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf
+ csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7
+ csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf
+ csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7
+ csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef
+ csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7
+ csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ];
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc
index a75be012b9..51960421b4 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc
@@ -1,7 +1,7 @@
# RV32A Standard Extension
# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4)
-:amoadd.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl
+:amoadd.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -13,7 +13,7 @@
# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4)
-:amoand.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl
+:amoand.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -25,7 +25,7 @@
# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4)
-:amomax.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl
+:amomax.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -37,7 +37,7 @@
# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4)
-:amomaxu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl
+:amomaxu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -49,7 +49,7 @@
# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4)
-:amomin.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl
+:amomin.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -61,7 +61,7 @@
# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4)
-:amominu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl
+:amominu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -73,7 +73,7 @@
# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4)
-:amoor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl
+:amoor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -85,7 +85,7 @@
# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4)
-:amoswap.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl
+:amoswap.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -96,7 +96,7 @@
# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4)
-:amoxor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl
+:amoxor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2W;
@@ -108,7 +108,7 @@
# lr.w d,0(s) 1000202f fff0707f DWORD|DREF (0, 4)
-:lr.w^aqrl rd,(rs1) is RV32 & RVA & rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl
+:lr.w^aqrl rd,(rs1) is rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl
{
RESERVE_ADDRESS = rs1;
RESERVE = 1;
@@ -118,14 +118,12 @@
# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4)
-:sc.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl
+:sc.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl
{
local tmprs2 = rs2W;
local tmprs1 = rs1;
rd = 1;
- if (RESERVE == 0) goto inst_next;
- if (RESERVE_ADDRESS != rs1) goto inst_next;
- if (RESERVE_LENGTH != 8) goto inst_next;
+ if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next;
*[ram]:4 tmprs1 = tmprs2;
rd = 0;
RESERVE_ADDRESS = 0;
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc
new file mode 100644
index 0000000000..41512c11c2
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc
@@ -0,0 +1,131 @@
+# RV32 Bitmanip Extension
+
+:andn rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x20 & rd & rs1 & rs2 unimpl
+
+:bdep rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:bext rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:bfp rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:clmul rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clmulh rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clmulr rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl
+
+:cmix rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x1 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl
+
+:cmov rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x5 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl
+
+:crc32.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x10 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x11 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x12 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32c.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x18 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32c.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x19 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32c.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1a & op2531=0x30 & rd & rs1 unimpl
+
+:ctz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl
+
+:fsl rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl
+
+:fsr rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl
+
+#TODO fix op2025
+#TODO this looks like a typo in 0.92
+:fsri rd, rs1, rs3, op2025 is op0006=0x33 & op1214=0x5 & op2626=0x1 & op2025 & rd & rs1 & rs3 unimpl
+
+:gorc rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:gorci rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x5 & op2026 & rd & rs1 unimpl
+
+:grev rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:grevi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xd & op2026 & rd & rs1 unimpl
+
+:max rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:maxu rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:min rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:minu rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:orn rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x20 & rd & rs1 & rs2 unimpl
+
+:pack rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:packh rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:packu rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:pcnt rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl
+
+:rol rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl
+
+:ror rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:rori rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xc & op2026 & rd & rs1 unimpl
+
+:sbclr rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sbclri rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x9 & op2026 & rd & rs1 unimpl
+
+:sbext rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sbexti rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x9 & op2026 & rd & rs1 unimpl
+
+:sbinv rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sbinvi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0xd & op2026 & rd & rs1 unimpl
+
+:sbset rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sbseti rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x5 & op2026 & rd & rs1 unimpl
+
+:sext.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x4 & op2531=0x30 & rd & rs1 unimpl
+
+:sext.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x5 & op2531=0x30 & rd & rs1 unimpl
+
+:sh1add rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:sh2add rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:sh3add rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:shfl rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2025
+:shfli rd, rs1, op2025 is op0006=0x13 & op1214=0x1 & op2631=0x2 & op2025 & rd & rs1 unimpl
+
+:slo rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sloi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x4 & op2026 & rd & rs1 unimpl
+
+:sro rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:sroi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x4 & op2026 & rd & rs1 unimpl
+
+:unshfl rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2025
+:unshfli rd, rs1, op2025 is op0006=0x13 & op1214=0x5 & op2631=0x2 & op2025 & rd & rs1 unimpl
+
+:xnor rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x20 & rd & rs1 & rs2 unimpl
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc
index 547b541bbb..e8d298bfbe 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc
@@ -1,23 +1,15 @@
# RV32D Standard Extension
-@if FPSIZE == "64"
-
-# fadd.d D,S,T 02007053 fe00707f SIMPLE (0, 0)
-:fadd.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x1
-{
- frd = frs1D f+ frs2D;
-}
-
# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0)
-:fadd.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1
+:fadd.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1
{
frd = frs1D f+ frs2D;
}
# fclass.d d,S e2001053 fff0707f SIMPLE (0, 0)
-:fclass.d rd,frs1D is RV32 & RVD & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0
+:fclass.d rd,frs1D is frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0
{
#TODO
# rd = 0;
@@ -35,7 +27,7 @@
# fcvt.d.s D,S 42000053 fff0707f SIMPLE (0, 0)
-:fcvt.d.s frd,frs1S is RV32 & RVD & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0
+:fcvt.d.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0
{
local tmp:8 = float2float(frs1S);
frd = tmp;
@@ -43,7 +35,7 @@
# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0)
-:fcvt.d.w frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0
+:fcvt.d.w frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0
{
local tmp:8 = int2float(rs1W);
frd = tmp;
@@ -51,7 +43,7 @@
# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0)
-:fcvt.d.wu frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1
+:fcvt.d.wu frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1
{
#ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W);
@@ -60,75 +52,45 @@
}
-# fcvt.s.d D,S 40107053 fff0707f SIMPLE (0, 0)
-:fcvt.s.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x1
-{
- local tmp:4 = float2float(frs1D);
- frd = zext(tmp);
-}
-
-
# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0)
-:fcvt.s.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1
+:fcvt.s.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1
{
local tmp:4 = float2float(frs1D);
frd = zext(tmp);
}
-# fcvt.w.d d,S c2007053 fff0707f SIMPLE (0, 0)
-:fcvt.w.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x0
-{
- rdW = trunc(frs1D);
-}
-
-
# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0)
-:fcvt.w.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
+:fcvt.w.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
{
rdW = trunc(frs1D);
}
-# fcvt.wu.d d,S c2107053 fff0707f SIMPLE (0, 0)
-:fcvt.wu.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x1
-{
- #TODO unsigned
- rdW = trunc(frs1D);
-}
-
-
# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0)
-:fcvt.wu.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
+:fcvt.wu.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1D);
}
-# fdiv.d D,S,T 1a007053 fe00707f SIMPLE (0, 0)
-:fdiv.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xd
-{
- frd = frs1D f/ frs2D;
-}
-
-
# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0)
-:fdiv.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd
+:fdiv.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd
{
frd = frs1D f/ frs2D;
}
# feq.d d,S,T a2002053 fe00707f SIMPLE (0, 0)
-:feq.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51
+:feq.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51
{
rd = zext(frs1D f== frs2D);
}
# fld D,o(s) 00003007 0000707f QWORD|DREF (0, 8)
-:fld frd,immI(rs1) is RV32 & RVD & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3
+:fld frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3
{
local ea:$(XLEN) = immI + rs1;
frd = *[ram]:$(DFLEN) ea;
@@ -136,36 +98,29 @@
# fle.d d,S,T a2000053 fe00707f SIMPLE (0, 0)
-:fle.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51
+:fle.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51
{
rd = zext(frs1D f<= frs2D);
}
# flt.d d,S,T a2001053 fe00707f SIMPLE (0, 0)
-:flt.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51
+:flt.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51
{
rd = zext(frs1D f< frs2D);
}
#endif
-# fmadd.d D,S,T,R 02007043 0600707f SIMPLE (0, 0)
-:fmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x1
-{
- frd = (frs1D f* frs2D) f+ frs3D;
-}
-
-
# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0)
-:fmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1
+:fmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1
{
frd = (frs1D f* frs2D) f+ frs3D;
}
# fmax.d D,S,T 2a001053 fe00707f SIMPLE (0, 0)
-:fmax.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15
+:fmax.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15
{
#TODO redo this
local tmpfrs1 = frs1D;
@@ -181,7 +136,7 @@
# fmin.d D,S,T 2a000053 fe00707f SIMPLE (0, 0)
-:fmin.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15
+:fmin.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15
{
#TODO redo this
local tmpfrs1 = frs1D;
@@ -196,64 +151,36 @@
}
-# fmsub.d D,S,T,R 02007047 0600707f SIMPLE (0, 0)
-:fmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x1
-{
- frd = (frs1D f* frs2D) f- frs3D;
-}
-
-
# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0)
-:fmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1
+:fmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1
{
frd = (frs1D f* frs2D) f- frs3D;
}
-# fmul.d D,S,T 12007053 fe00707f SIMPLE (0, 0)
-:fmul.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x9
-{
- frd = frs1D f* frs2D;
-}
-
-
# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0)
-:fmul.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9
+:fmul.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9
{
frd = frs1D f* frs2D;
}
-# fnmadd.d D,S,T,R 0200704f 0600707f SIMPLE (0, 0)
-:fnmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x1
-{
- frd = (f- (frs1D f* frs2D)) f- frs3D;
-}
-
-
# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0)
-:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1
+:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f- frs3D;
}
-# fnmsub.d D,S,T,R 0200704b 0600707f SIMPLE (0, 0)
-:fnmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x1
-{
- frd = (f- (frs1D f* frs2D)) f+ frs3D;
-}
-
-
# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0)
-:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1
+:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1
{
frd = (f- (frs1D f* frs2D)) f+ frs3D;
}
# fsd T,q(s) 00003027 0000707f QWORD|DREF (0, 8)
-:fsd frs2D,immS(rs1) is RV32 & RVD & frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3
+:fsd frs2D,immS(rs1) is frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(DFLEN) ea = frs2D;
@@ -261,7 +188,7 @@
# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0)
-:fsgnj.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11
+:fsgnj.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = frs2D[63,1];
@@ -269,14 +196,14 @@
}
# fmv.d D,U 22000053 fe00707f ALIAS (0, 0)
-:fmv.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024
+:fmv.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024
{
frd = frs1D;
}
# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0)
-:fsgnjn.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11
+:fsgnjn.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = !frs2D[63,1];
@@ -284,14 +211,14 @@
}
# fneg.d D,U 22001053 fe00707f ALIAS (0, 0)
-:fneg.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024
+:fneg.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024
{
frd = f- frs1D;
}
# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0)
-:fsgnjx.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11
+:fsgnjx.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11
{
local tmp:$(DFLEN) = frs1D;
tmp[63,1] = tmp[63,1] ^ frs2D[63,1];
@@ -299,37 +226,21 @@
}
# fabs.d D,U 22002053 fe00707f ALIAS (0, 0)
-:fabs.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024
+:fabs.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024
{
frd = abs(frs1D);
}
-# fsqrt.d D,S 5a007053 fff0707f SIMPLE (0, 0)
-:fsqrt.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2d & op2024=0x0
-{
- frd = sqrt(frs1D);
-}
-
-
# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0)
-:fsqrt.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0
+:fsqrt.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0
{
frd = sqrt(frs1D);
}
-# fsub.d D,S,T 0a007053 fe00707f SIMPLE (0, 0)
-:fsub.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x5
-{
- frd = frs1D f- frs2D;
-}
-
-
# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0)
-:fsub.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5
+:fsub.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5
{
frd = frs1D f- frs2D;
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc
index 51d606d9a5..e830008391 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc
@@ -1,17 +1,7 @@
# RV32F Standard Extension
-@if FPSIZE != ""
-
-# fadd.s D,S,T 00007053 fe00707f SIMPLE (0, 0)
-:fadd.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x0
-{
- local tmp:4 = frs1S f+ frs2S;
- fassignS(frd, tmp);
-}
-
-
# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0)
-:fadd.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0
+:fadd.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0
{
local tmp:4 = frs1S f+ frs2S;
fassignS(frd, tmp);
@@ -19,7 +9,7 @@
# fclass.s d,S e0001053 fff0707f SIMPLE (0, 0)
-:fclass.s rd,frs1S is RV32 & RVF & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0
+:fclass.s rd,frs1S is frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0
{
#TODO
# rd = 0;
@@ -36,34 +26,16 @@
}
-# fcvt.s.w D,s d0007053 fff0707f SIMPLE (0, 0)
-:fcvt.s.w frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x0
-{
- local tmp:4 = int2float(rs1W);
- fassignS(frd, tmp);
-}
-
-
# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0)
-:fcvt.s.w frd,rs1W,FRM is RV32 & RVF & frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
+:fcvt.s.w frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
{
local tmp:4 = int2float(rs1W);
fassignS(frd, tmp);
}
-# fcvt.s.wu D,s d0107053 fff0707f SIMPLE (0, 0)
-:fcvt.s.wu frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x1
-{
- #ATTN unsigned can be an issue here
- local u32:$(XLEN2) = zext(rs1W);
- local tmp:4 = int2float(u32);
- fassignS(frd, tmp);
-}
-
-
# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0)
-:fcvt.s.wu frd,rs1W,FRM is RV32 & RVF & frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
+:fcvt.s.wu frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
{
#ATTN unsigned can be an issue here
local u32:$(XLEN2) = zext(rs1W);
@@ -72,44 +44,23 @@
}
-# fcvt.w.s d,S c0007053 fff0707f SIMPLE (0, 0)
-:fcvt.w.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x0
-{
- rdW = trunc(frs1S);
-}
-
# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0)
-:fcvt.w.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
+:fcvt.w.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
{
rdW = trunc(frs1S);
}
-# fcvt.wu.s d,S c0107053 fff0707f SIMPLE (0, 0)
-:fcvt.wu.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x1
-{
- #TODO unsigned
- rdW = trunc(frs1S);
-}
-
# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0)
-:fcvt.wu.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
+:fcvt.wu.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
{
#TODO unsigned
rdW = trunc(frs1S);
}
-# fdiv.s D,S,T 18007053 fe00707f SIMPLE (0, 0)
-:fdiv.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xc
-{
- local tmp:4 = frs1S f/ frs2S;
- fassignS(frd, tmp);
-}
-
-
# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0)
-:fdiv.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc
+:fdiv.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc
{
local tmp:4 = frs1S f/ frs2S;
fassignS(frd, tmp);
@@ -117,44 +68,36 @@
# feq.s d,S,T a0002053 fe00707f SIMPLE (0, 0)
-:feq.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50
+:feq.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50
{
rd = zext(frs1S f== frs2S);
}
# fle.s d,S,T a0000053 fe00707f SIMPLE (0, 0)
-:fle.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50
+:fle.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50
{
rd = zext(frs1S f<= frs2S);
}
# flt.s d,S,T a0001053 fe00707f SIMPLE (0, 0)
-:flt.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50
+:flt.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50
{
rd = zext(frs1S f< frs2S);
}
# flw D,o(s) 00002007 0000707f DWORD|DREF (0, 4)
-:flw frd,immI(rs1) is RV32 & RVF & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2
+:flw frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2
{
local ea:$(XLEN) = immI + rs1;
fassignS(frd, *[ram]:4 ea);
}
-# fmadd.s D,S,T,R 00007043 0600707f SIMPLE (0, 0)
-:fmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x0
-{
- local tmp:4 = (frs1S f* frs2S) f+ frs3S;
- fassignS(frd, tmp);
-}
-
-
# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0)
-:fmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0
+:fmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f+ frs3S;
fassignS(frd, tmp);
@@ -162,7 +105,7 @@
# fmax.s D,S,T 28001053 fe00707f SIMPLE (0, 0)
-:fmax.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14
+:fmax.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14
{
#TODO redo this
local tmpfrs1 = frs1S;
@@ -178,7 +121,7 @@
# fmin.s D,S,T 28000053 fe00707f SIMPLE (0, 0)
-:fmin.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14
+:fmin.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14
{
#TODO redo this
local tmpfrs1 = frs1S;
@@ -193,31 +136,16 @@
}
-# fmsub.s D,S,T,R 00007047 0600707f SIMPLE (0, 0)
-:fmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x0
-{
- local tmp:4 = (frs1S f* frs2S) f- frs3S;
- fassignS(frd, tmp);
-}
-
-
# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0)
-:fmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0
+:fmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (frs1S f* frs2S) f- frs3S;
fassignS(frd, tmp);
}
-# fmul.s D,S,T 10007053 fe00707f SIMPLE (0, 0)
-:fmul.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x8
-{
- local tmp:4 = frs1S f* frs2S;
- fassignS(frd, tmp);
-}
-
# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0)
-:fmul.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8
+:fmul.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8
{
local tmp:4 = frs1S f* frs2S;
fassignS(frd, tmp);
@@ -225,44 +153,30 @@
# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0)
-:fmv.w.x frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0
+:fmv.w.x frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0
{
fassignS(frd, rs1W);
}
# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0)
-:fmv.x.w rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0
+:fmv.x.w rdW,frs1S is frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0
{
- zassignW(rdW, frs1S);
-}
-
-
-# fnmadd.s D,S,T,R 0000704f 0600707f SIMPLE (0, 0)
-:fnmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x0
-{
- local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;
- fassignS(frd, tmp);
+ local tmpreg:4 = &frs1S;
+ local tmp:4 = *[register]:4 tmpreg;
+ rdW = tmp;
}
# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0)
-:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0
+:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;
fassignS(frd, tmp);
}
-# fnmsub.s D,S,T,R 0000704b 0600707f SIMPLE (0, 0)
-:fnmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x0
-{
- local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;
- fassignS(frd, tmp);
-}
-
-
# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0)
-:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0
+:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0
{
local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;
fassignS(frd, tmp);
@@ -270,7 +184,7 @@
# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0)
-:fsgnj.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10
+:fsgnj.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = frs2S[31,1];
@@ -278,14 +192,14 @@
}
# fmv.s D,U 20000053 fe00707f ALIAS (0, 0)
-:fmv.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024
+:fmv.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024
{
fassignS(frd, frs1S);
}
# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0)
-:fsgnjn.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10
+:fsgnjn.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = !frs2S[31,1];
@@ -293,7 +207,7 @@
}
# fneg.s D,U 20001053 fe00707f ALIAS (0, 0)
-:fneg.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024
+:fneg.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024
{
local tmp:4 = f- frs1S;
fassignS(frd, tmp);
@@ -301,7 +215,7 @@
# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0)
-:fsgnjx.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10
+:fsgnjx.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10
{
local tmp:$(SFLEN) = frs1S;
tmp[31,1] = tmp[31,1] ^ frs2S[31,1];
@@ -309,39 +223,23 @@
}
# fabs.s D,U 20002053 fe00707f ALIAS (0, 0)
-:fabs.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024
+:fabs.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024
{
local tmp:4 = abs(frs1S);
fassignS(frd, tmp);
}
-# fsqrt.s D,S 58007053 fff0707f SIMPLE (0, 0)
-:fsqrt.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2c & op2024=0x0
-{
- local tmp:4 = sqrt(frs1S);
- fassignS(frd, tmp);
-}
-
-
# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0)
-:fsqrt.s frd,frs1S,FRM is RV32 & RVF & frs1S & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0
+:fsqrt.s frd,frs1S,FRM is frs1S & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0
{
local tmp:4 = sqrt(frs1S);
fassignS(frd, tmp);
}
-# fsub.s D,S,T 08007053 fe00707f SIMPLE (0, 0)
-:fsub.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x4
-{
- local tmp:4 = frs1S f- frs2S;
- fassignS(frd, tmp);
-}
-
-
# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0)
-:fsub.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4
+:fsub.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4
{
local tmp:4 = frs1S f- frs2S;
fassignS(frd, tmp);
@@ -349,10 +247,8 @@
# fsw T,q(s) 00002027 0000707f DWORD|DREF (0, 4)
-:fsw frs2S,immS(rs1) is RV32 & RVF & frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2
+:fsw frs2S,immS(rs1) is frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(SFLEN) ea = frs2S;
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
index 39861f592b..98326a6826 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
@@ -1,34 +1,33 @@
# RV32I Base Instruction Set
-
# add d,s,t 00000033 fe00707f SIMPLE (0, 0)
-:add rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0
+:add rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0
{
rd = rs1 + rs2;
}
# addi d,s,j 00000013 0000707f SIMPLE (0, 0)
-:addi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0
+:addi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0
{
rd = rs1 + immI;
}
# nop 00000013 ffffffff ALIAS (0, 0)
-:nop is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0
+:nop is op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0
{
local NOP:1 = 0;
NOP = NOP;
}
# mv d,s 00000013 fff0707f ALIAS (0, 0)
-:mv rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0
+:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0
{
rd = rs1;
}
# li d,j 00000013 000ff07f ALIAS (0, 0)
-:li rd,immI is RV32 & RVI & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0
+:li rd,immI is immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0
{
#TODO alias of addi rd,zero,0x0 is an issue
rd = immI;
@@ -36,129 +35,133 @@
# Resolve conflict between: mv rd,zero and li rd,0x0
# ATTN this implementation uses mv rd,zero
-:mv rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1531=0x0
+:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1531=0x0
{
rd = rs1;
}
+
# and d,s,t 00007033 fe00707f SIMPLE (0, 0)
-:and rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0
+:and rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0
{
rd = rs1 & rs2;
}
# andi d,s,j 00007013 0000707f SIMPLE (0, 0)
-:andi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7
+:andi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7
{
rd = rs1 & immI;
}
# auipc d,u 00000017 0000007f SIMPLE (0, 0)
-:auipc rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0
+:auipc rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0
{
- rd = (immU << 12) + inst_start;
+ rd = immU + inst_start;
}
# beq s,t,p 00000063 0000707f CONDBRANCH (0, 0)
-:beq rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0
+:beq rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0
{
if (rs1 == rs2) goto immSB;
}
# bge s,t,p 00005063 0000707f CONDBRANCH (0, 0)
-:bge rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5
+:bge rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5
{
if (rs1 s>= rs2) goto immSB;
}
# bgeu s,t,p 00007063 0000707f CONDBRANCH (0, 0)
-:bgeu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7
+:bgeu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7
{
if (rs1 >= rs2) goto immSB;
}
# blt s,t,p 00004063 0000707f CONDBRANCH (0, 0)
-:blt rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4
+:blt rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4
{
if (rs1 s< rs2) goto immSB;
}
# bltu s,t,p 00006063 0000707f CONDBRANCH (0, 0)
-:bltu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6
+:bltu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6
{
if (rs1 < rs2) goto immSB;
}
# bne s,t,p 00001063 0000707f CONDBRANCH (0, 0)
-:bne rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1
+:bne rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1
{
if (rs1 != rs2) goto immSB;
}
-
# ebreak 00100073 ffffffff SIMPLE (0, 0)
-:ebreak is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20
+:ebreak is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20
{
+ ebreak();
}
-
# ecall 00000073 ffffffff SIMPLE (0, 0)
-:ecall is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0
+:ecall is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0
{
+ ecall();
}
# fence P,Q 0000000f f00fffff SIMPLE (0, 0)
-:fence pred,succ is RV32 & RVI & pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0
+:fence pred,succ is pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0
{
+ fence();
}
# jal d,a 0000006f 0000007f JSR (0, 0)
-:jal rd,immUJ is RV32 & RVI & immUJ & rd & op0001=0x3 & op0204=0x3 & op0506=0x3
+:jal rd,immUJ is immUJ & rd & op0001=0x3 & op0204=0x3 & op0506=0x3
{
+ #TODO RAS: push inst_next if rd=x1/x5
rd = inst_next;
call immUJ;
}
# j a 0000006f 00000fff BRANCH|ALIAS (0, 0)
-:j immUJ is RV32 & RVI & immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0
+:j immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0
{
goto immUJ;
}
# jalr d,s,j 00000067 0000707f JSR (0, 0)
-:jalr rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
+:jalr rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
{
+ #TODO RAS: push inst_next/pop based on rd=x1/x5 or rs1=x1/x5
local ea:$(XLEN) = (rs1 + immI) & ~1;
rd = inst_next;
call [ea];
}
# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0)
-:jr immI(rs1) is RV32 & RVI & immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0
+:jr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0
{
local ea:$(XLEN) = (rs1 + immI) & ~1;
goto [ea];
}
# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0)
-:jr rs1 is RV32 & RVI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0
+:jr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0
{
local ea:$(XLEN) = rs1 & ~1;
goto [ea];
}
# ret 00008067 ffffffff BRANCH|ALIAS (0, 0)
-:ret is RV32 & RVI & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1
+:ret is op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1
{
local ea:$(XLEN) = ra & ~1;
return [ea];
@@ -166,7 +169,7 @@
# lb d,o(s) 00000003 0000707f BYTE|DREF (0, 1)
-:lb rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0
+:lb rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0
{
local ea:$(XLEN) = rs1 + immI;
rd = sext(*[ram]:1 ea);
@@ -174,7 +177,7 @@
# lbu d,o(s) 00004003 0000707f BYTE|DREF (0, 1)
-:lbu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4
+:lbu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:1 ea);
@@ -182,7 +185,7 @@
# lh d,o(s) 00001003 0000707f WORD|DREF (0, 2)
-:lh rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1
+:lh rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1
{
local ea:$(XLEN) = rs1 + immI;
rd = sext(*[ram]:2 ea);
@@ -190,7 +193,7 @@
# lhu d,o(s) 00005003 0000707f WORD|DREF (0, 2)
-:lhu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5
+:lhu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:2 ea);
@@ -198,14 +201,14 @@
# lui d,u 00000037 0000007f SIMPLE (0, 0)
-:lui rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1
+:lui rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1
{
- rd = immU << 12;
+ rd = immU;
}
# lw d,o(s) 00002003 0000707f DWORD|DREF (0, 4)
-:lw rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2
+:lw rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2
{
local ea:$(XLEN) = rs1 + immI;
assignW(rd, *[ram]:4 ea);
@@ -213,21 +216,21 @@
# or d,s,t 00006033 fe00707f SIMPLE (0, 0)
-:or rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0
+:or rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0
{
rd = rs1 | rs2;
}
# ori d,s,j 00006013 0000707f SIMPLE (0, 0)
-:ori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6
+:ori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6
{
rd = rs1 | immI;
}
# sb t,q(s) 00000023 0000707f BYTE|DREF (0, 1)
-:sb rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0
+:sb rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:1 ea = rs2:1;
@@ -235,7 +238,7 @@
# sh t,q(s) 00001023 0000707f WORD|DREF (0, 2)
-:sh rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1
+:sh rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:2 ea = rs2:2;
@@ -243,93 +246,93 @@
# sll d,s,t 00001033 fe00707f SIMPLE (0, 0)
-:sll rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0
+:sll rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0
{
- local shift:$(XLEN) = rs2 & 0x3f;
+ local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);
rd = rs1 << shift;
}
# slli d,s,> 00001013 fc00707f SIMPLE (0, 0)
-:slli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0
+:slli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0
{
rd = rs1 << shamt6;
}
# slt d,s,t 00002033 fe00707f SIMPLE (0, 0)
-:slt rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0
+:slt rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0
{
rd = zext(rs1 s< rs2);
}
# slti d,s,j 00002013 0000707f SIMPLE (0, 0)
-:slti rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2
+:slti rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2
{
rd = zext(rs1 s< immI);
}
# sltiu d,s,j 00003013 0000707f SIMPLE (0, 0)
-:sltiu rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3
+:sltiu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3
{
rd = zext(rs1 < immI);
}
# sltu d,s,t 00003033 fe00707f SIMPLE (0, 0)
-:sltu rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0
+:sltu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0
{
rd = zext(rs1 < rs2);
}
# sra d,s,t 40005033 fe00707f SIMPLE (0, 0)
-:sra rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20
+:sra rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20
{
- local shift:$(XLEN) = rs2 & 0x3f;
+ local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);
rd = rs1 s>> shift;
}
# srai d,s,> 40005013 fc00707f SIMPLE (0, 0)
-:srai rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10
+:srai rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10
{
rd = rs1 s>> shamt6;
}
# srl d,s,t 00005033 fe00707f SIMPLE (0, 0)
-:srl rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0
+:srl rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0
{
- local shift:$(XLEN) = rs2 & 0x3f;
+ local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1);
rd = rs1 >> shift;
}
# srli d,s,> 00005013 fc00707f SIMPLE (0, 0)
-:srli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0
+:srli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0
{
rd = rs1 >> shamt6;
}
# sub d,s,t 40000033 fe00707f SIMPLE (0, 0)
-:sub rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20
+:sub rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20
{
rd = rs1 - rs2;
}
# neg d,t 40000033 fe0ff07f ALIAS (0, 0)
-:neg rd,rs2 is RV32 & RVI & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
+:neg rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
{
rd = -rs2;
}
# sw t,q(s) 00002023 0000707f DWORD|DREF (0, 4)
-:sw rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2
+:sw rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:4 ea = rs2:4;
@@ -337,26 +340,27 @@
# unimp c0001073 ffffffff SIMPLE (0, 0)
-:unimp is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000
+:unimp is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000
{
+ unimp();
}
# xor d,s,t 00004033 fe00707f SIMPLE (0, 0)
-:xor rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0
+:xor rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0
{
rd = rs1 ^ rs2;
}
# xori d,s,j 00004013 0000707f SIMPLE (0, 0)
-:xori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4
+:xori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4
{
rd = rs1 ^ immI;
}
# not d,s fff04013 fff0707f ALIAS (0, 0)
-:not rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff
+:not rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff
{
rd = ~rs1;
}
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc
new file mode 100644
index 0000000000..243b744b4f
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc
@@ -0,0 +1,59 @@
+# RV32 Crypto Extension
+# NOTE 0.6.2
+
+# bs 00001 rs2 rs1 010 rd 0101011 saes32.encs
+:saes32.encs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x1 unimpl
+
+# bs 00000 rs2 rs1 010 rd 0101011 saes32.encsm
+:saes32.encsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x0 unimpl
+
+# bs 00011 rs2 rs1 010 rd 0101011 saes32.decs
+:saes32.decs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x3 unimpl
+
+# bs 00010 rs2 rs1 010 rd 0101011 saes32.decsm
+:saes32.decsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x2 unimpl
+
+# 0000111 00000 rs1 111 rd 0101011 ssha256.sig0
+:ssha256.sig0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x00 & op2531=0x07 unimpl
+
+# 0000111 00001 rs1 111 rd 0101011 ssha256.sig1
+:ssha256.sig1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x01 & op2531=0x07 unimpl
+
+# 0000111 00010 rs1 111 rd 0101011 ssha256.sum0
+:ssha256.sum0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x02 & op2531=0x07 unimpl
+
+# 0000111 00011 rs1 111 rd 0101011 ssha256.sum1
+:ssha256.sum1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x03 & op2531=0x07 unimpl
+
+# 0001100 rs2 rs1 111 rd 0101011 ssha512.sum0r
+:ssha512.sum0r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0c unimpl
+
+# 0001101 rs2 rs1 111 rd 0101011 ssha512.sum1r
+:ssha512.sum1r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0d unimpl
+
+# 0001000 rs2 rs1 111 rd 0101011 ssha512.sig0l
+:ssha512.sig0l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x08 unimpl
+
+# 0001001 rs2 rs1 111 rd 0101011 ssha512.sig0h
+:ssha512.sig0h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x09 unimpl
+
+# 0001010 rs2 rs1 111 rd 0101011 ssha512.sig1l
+:ssha512.sig1l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0a unimpl
+
+# 0001011 rs2 rs1 111 rd 0101011 ssha512.sig1h
+:ssha512.sig1h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0b unimpl
+
+# 0000111 01000 rs1 111 rd 0101011 ssm3.p0
+:ssm3.p0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x08 & op2531=0x07 unimpl
+
+# 0000111 01001 rs1 111 rd 0101011 ssm3.p1
+:ssm3.p1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x09 & op2531=0x07 unimpl
+
+# bs 00100 rs2 rs1 011 rd 0101011 ssm4.ed
+:ssm4.ed rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x4 unimpl
+
+# bs 00101 rs2 rs1 011 rd 0101011 ssm4.ks
+:ssm4.ks rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x5 unimpl
+
+# 0000111 shamtw 01010 111 rd 0101011 pollentropy
+:pollentropy rd, shamtw is rd & shamtw & op0006=0x2b & op1214=0x7 & op1519=0x0a & op2531=0x07 unimpl
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc
index b1e05c75d7..f7202a39f4 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc
@@ -1,29 +1,28 @@
# RV32M Standard Extension
-
# div d,s,t 02004033 fe00707f SIMPLE (0, 0)
-:div rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1
+:div rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1
{
rd = rs1 s/ rs2;
}
# divu d,s,t 02005033 fe00707f SIMPLE (0, 0)
-:divu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1
+:divu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1
{
rd = rs1 / rs2;
}
# mul d,s,t 02000033 fe00707f SIMPLE (0, 0)
-:mul rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1
+:mul rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1
{
rd = rs1 * rs2;
}
# mulh d,s,t 02001033 fe00707f SIMPLE (0, 0)
-:mulh rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1
+:mulh rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1
{
local trs1:$(XLEN2) = sext(rs1);
local trs2:$(XLEN2) = sext(rs2);
@@ -33,7 +32,7 @@
# mulhsu d,s,t 02002033 fe00707f SIMPLE (0, 0)
-:mulhsu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1
+:mulhsu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1
{
local trs1:$(XLEN2) = sext(rs1);
local trs2:$(XLEN2) = zext(rs2);
@@ -43,7 +42,7 @@
# mulhu d,s,t 02003033 fe00707f SIMPLE (0, 0)
-:mulhu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1
+:mulhu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1
{
local trs1:$(XLEN2) = zext(rs1);
local trs2:$(XLEN2) = zext(rs2);
@@ -53,14 +52,14 @@
# rem d,s,t 02006033 fe00707f SIMPLE (0, 0)
-:rem rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1
+:rem rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1
{
rd = rs1 s% rs2;
}
# remu d,s,t 02007033 fe00707f SIMPLE (0, 0)
-:remu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1
+:remu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1
{
rd = rs1 % rs2;
}
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc
new file mode 100644
index 0000000000..749f6b3157
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc
@@ -0,0 +1,996 @@
+# RV32 P Extension
+
+
+# add16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:add16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x20
+{
+ local tmp1:$(XLEN) = rs1;
+ local tmp2:$(XLEN) = rs2;
+ rd[ 0,16] = tmp1[ 0,16] + tmp2[ 0,16];
+ rd[16,16] = tmp1[16,16] + tmp2[16,16];
+@if ADDRSIZE == "64"
+ rd[32,16] = tmp1[32,16] + tmp2[32,16];
+ rd[48,16] = tmp1[48,16] + tmp2[48,16];
+@endif
+}
+
+
+# add64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 + b64; + ; + ; r[tU].r[tL] = t64;
+:add64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x60
+{
+@if ADDRSIZE == "32"
+ local dst:$(XLEN) = &rd;
+ local src1:$(XLEN) = &rs1;
+ local src2:$(XLEN) = &rs2;
+ *[register]:8 dst = *[register]:8 src1 + *[register]:8 src2;
+@else
+ rd = rs1 + rs2;
+@endif
+}
+
+
+# add8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] + rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:add8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x24
+{
+ local tmp1:$(XLEN) = rs1;
+ local tmp2:$(XLEN) = rs2;
+ rd[ 0,8] = tmp1[ 0,8] + tmp2[ 0,8];
+ rd[ 8,8] = tmp1[ 8,8] + tmp2[ 8,8];
+ rd[16,8] = tmp1[16,8] + tmp2[16,8];
+ rd[24,8] = tmp1[24,8] + tmp2[24,8];
+@if ADDRSIZE == "64"
+ rd[32,8] = tmp1[32,8] + tmp2[32,8];
+ rd[40,8] = tmp1[40,8] + tmp2[40,8];
+ rd[48,8] = tmp1[48,8] + tmp2[48,8];
+ rd[56,8] = tmp1[56,8] + tmp2[56,8];
+@endif
+}
+
+
+# ave rt, ra, rb
+:ave rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x70
+{
+ local tmp:$(XLEN) = rs1 + rs2;
+ rd = (tmp / 2) + (tmp & 1);
+}
+
+
+# bitrev rt, ra, rb ; msb = rb[4:0]; // RV32 ; msb = rb[5:0]; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]);
+:bitrev rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x73 unimpl
+
+
+# bitrevi rt, ra, imm5u ; msb = imm5u; // RV32 ; msb = imm6u; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]);
+:bitrevi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x74 unimpl
+
+
+# bpick rt, ra, rb, rc ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0)
+:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x00 unimpl
+
+
+# bpick rt, ra, rb, rc ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0)
+:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x04 unimpl
+
+
+# clo16 rt, ra
+:clo16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x0a unimpl
+
+
+# clo32 rt, ra ; rt.W[_x_] = CLO(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)
+:clo32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x12 unimpl
+
+
+# clo8 rt, ra
+:clo8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x02 unimpl
+
+
+# clrs16 rt, ra
+:clrs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x08 unimpl
+
+
+# clrs32 rt, ra ; rt.W[_x_] = CLRS(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)
+:clrs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x10 unimpl
+
+
+# clrs8 rt, ra
+:clrs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x00 unimpl
+
+
+# clz16 rt, ra
+:clz16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x09 unimpl
+
+
+# clz32 rt, ra ; rt.W[_x_] = CLZ(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0)
+:clz32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x11 unimpl
+
+
+# clz8 rt, ra
+:clz8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x01 unimpl
+
+
+# cmpeq16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] == rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:cmpeq16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x26 unimpl
+
+
+# cmpeq8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] == rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:cmpeq8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x27 unimpl
+
+
+# cras16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3)
+:cras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x22 unimpl
+
+
+# crsa16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3)
+:crsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x23 unimpl
+
+
+# insb rt, ra, imm3u ; byte_idx = imm2u; // RV32 ; byte_idx = imm3u; // RV64 ; rt.B[byte_idx] = ra.B[0];
+:insb rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x00 unimpl
+
+
+# kabs16 rt, ra ; rt.H[_x_] = SAT.Q15(ABS(ra.H[_x_])); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:kabs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x11 unimpl
+
+
+# kabs32 rt, ra ; rt.W[_x_] = SAT.Q31(ABS(ra.W[_x_])); ; (RV64: __x__=1..0)
+:kabs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x12 unimpl
+
+
+# kabs8 rt, ra ; rt.B[_x_] = SAT.Q7(ABS(ra.B[_x_])); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:kabs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x10 unimpl
+
+
+# kabsw rt, ra ; rt = SAT.Q31(ABS(ra)); // RV32 ; rt = SE(SAT.Q31(ABS(ra.W[_0_]))); // RV64
+:kabsw rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x14 unimpl
+
+
+# kadd16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:kadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x08 unimpl
+
+
+# kadd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 + b64); + ; + ; r[tU].r[tL] = t64;
+:kadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x48 unimpl
+
+
+# kadd8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:kadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0c unimpl
+
+
+:kaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x02 unimpl
+
+
+:kaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x00 unimpl
+
+
+# kcras16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:kcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0a unimpl
+
+
+# kcrsa16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:kcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0b unimpl
+
+
+:kdmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x69 unimpl
+
+
+:kdmabb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6b unimpl
+
+
+:kdmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x71 unimpl
+
+
+:kdmabt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x74 unimpl
+
+
+:kdmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x79 unimpl
+
+
+:kdmatt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7c unimpl
+
+
+:kdmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x05 unimpl
+
+
+:kdmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6c unimpl
+
+
+:kdmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0d unimpl
+
+
+:kdmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x75 unimpl
+
+
+:kdmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x15 unimpl
+
+
+:kdmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7d unimpl
+
+
+# khm16 rt, ra, rb ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_x_]) >> 15); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:khm16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x43 unimpl
+
+
+# khm8 rt, ra, rb ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_x_]) >> 7); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:khm8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x47 unimpl
+
+
+:khmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x06 unimpl
+
+
+:khmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6d unimpl
+
+
+:khmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0e unimpl
+
+
+:khmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x76 unimpl
+
+
+:khmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x16 unimpl
+
+
+:khmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7e unimpl
+
+
+# khmx16 rt, ra, rb ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_y_]) >> 15); ; (RV32: (_x,y_)=(1,0), (0,1), + ; RV64: (_x,y_)=(3,2),(2,3),(1,0), (0,1))
+:khmx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4b unimpl
+
+
+# khmx8 rt, ra, rb ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_y_]) >> 7); ; (RV32: (_x,y_)=(3,2),(2,3),(1,0), (0,1), + ; RV64: (_x,y_)=(7,6),(6,7),(5,4), (4,5), (3,2), (2,3), (1,0), (0,1))
+:khmx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4f unimpl
+
+
+# kmabb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2d unimpl
+
+
+# kmabt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x35 unimpl
+
+
+# kmada rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x24 unimpl
+
+
+# kmadrs rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0] - ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmadrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x36 unimpl
+
+
+# kmads rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmads rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2e unimpl
+
+
+# kmar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64;
+:kmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4a unimpl
+
+
+# kmatt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3d unimpl
+
+
+# kmaxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmaxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x25 unimpl
+
+
+# kmaxds rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmaxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3e unimpl
+
+
+# kmda rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1c unimpl
+
+
+# kmmac rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmac rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x30 unimpl
+
+
+:kmmac.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x38 unimpl
+
+
+# kmmawb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[0])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmawb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x23 unimpl
+
+
+:kmmawb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2b unimpl
+
+
+# kmmawb2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = SAT.Q31(rt.W[x] + t[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmawb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x67 unimpl
+
+
+:kmmawb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6e unimpl
+
+
+# kmmawt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[1])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmawt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x33 unimpl
+
+
+:kmmawt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3b unimpl
+
+
+# kmmsb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmsb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x21 unimpl
+
+
+:kmmsb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x29 unimpl
+
+
+# kmmwb2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmwb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x47 unimpl
+
+
+:kmmwb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4f unimpl
+
+
+# kmmwt2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x57 unimpl
+
+
+# kmmwt2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x77 unimpl
+
+
+:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5f unimpl
+
+
+:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7f unimpl
+
+
+# kmsda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmsda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x26 unimpl
+
+
+# kmsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 – ra*rb); + ; + ; r[tU].r[tL] = t64;
+:kmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4b unimpl
+
+
+# kmsxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmsxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x27 unimpl
+
+
+# kmxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kmxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1d unimpl
+
+
+:ksll rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x13 unimpl
+
+
+# ksll16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << im4u); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ksll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x32 unimpl
+
+
+# ksll8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[2:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ksll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x36 unimpl
+
+
+:kslli rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1b unimpl
+
+
+# kslra16 rt, ra, rb ; if (rb[4:0] < 0) + ; rt.H[_x_] = ra.H[_x_] s>> -rb[4:0]; ; if (rb[4:0] > 0) + ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << rb[4:0]); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:kslra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2b unimpl
+
+
+:kslra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x33 unimpl
+
+
+# kslra8 rt, ra, rb ; if (rb[3:0] < 0) + ; rt.B[_x_] = ra.B[_x_] s>> -rb[3:0]; ; if (rb[3:0] > 0) + ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[3:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:kslra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2f unimpl
+
+
+:kslra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x37 unimpl
+
+
+:kslraw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x37 unimpl
+
+
+:kslraw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3f unimpl
+
+
+# ksub16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x09 unimpl
+
+
+# ksub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 - b64); + ; + ; r[tU].r[tL] = t64;
+:ksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x49 unimpl
+
+
+# ksub8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0d unimpl
+
+
+:ksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x03 unimpl
+
+
+:ksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x01 unimpl
+
+
+# kwmmul rt, ra, rb ; rt.W[_x_] = SAT.Q31((ra.W[_x_]*rb.W[_x_] << 1)[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:kwmmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x31 unimpl
+
+
+:kwmmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x39 unimpl
+
+
+# maddr32 rt, ra, tb ; 11
+:maddr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x62 unimpl
+
+
+# maxw rt, ra, rb ; if (ra.W[0] >= rb.W[0]) \{ ; rt = SE(ra.W[0]); ; else \{ ; rt = SE(rb.W[0]); ; }
+:maxw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x79 unimpl
+
+
+# minw rt, ra, rb ; if (ra.W[0] >= rb.W[0]) \{ ; rt = SE(rb.W[0]); ; else \{ ; rt = SE(ra.W[0]); ; }
+:minw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x78 unimpl
+
+
+# msubr32 rt, ra, tb ; === ; <<< ; === RV64 Only Instructions ; The following tables list instructions that are only present in RV64. ; There are 30 SIMD 32-bit addition or subtraction instructions. ; .(RV64 Only) SIMD 32-bit Add/Subtract Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",]
+:msubr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x63 unimpl
+
+
+:mtlbi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7c unimpl
+
+
+:mtlei rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7d unimpl
+
+
+# mulr64 rt, ra, rb ; RV32: ; mres[63:0] = ra u* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] u* rb.W[0];
+:mulr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x78 unimpl
+
+
+# mulsr64 rt, ra, rb ; RV32: ; mres[63:0] = ra s* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] s* rb.W[0];
+:mulsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x70 unimpl
+
+
+:oneop rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x56 unimpl
+
+
+:oneop2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x57 unimpl
+
+
+# pbsad rt, ra, rb ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:pbsad rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7e unimpl
+
+
+# pbsada rt, ra, rb ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = rt + SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:pbsada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7f unimpl
+
+
+# pkbb16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:pkbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x07 unimpl
+
+
+# pkbt16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:pkbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0f unimpl
+
+
+# pktb16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:pktb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1f unimpl
+
+
+# pktt16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:pktt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x17 unimpl
+
+
+# radd16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:radd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x00 unimpl
+
+
+# radd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 + b64) s>>1; + ; + ; r[tU].r[tL] = t64;
+:radd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x40 unimpl
+
+
+# radd8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] + rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:radd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x04 unimpl
+
+
+# raddw rt, ra, rb ; res = (ra.W[0] + rb.W[0]) s>> 1; ; rt = SE(res);
+:raddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x10 unimpl
+
+
+# rcras16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:rcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x02 unimpl
+
+
+# rcrsa16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:rcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x03 unimpl
+
+
+# rsub16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:rsub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x01 unimpl
+
+
+# rsub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 - b64) s>>1; + ; + ; r[tU].r[tL] = t64;
+:rsub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x41 unimpl
+
+
+# rsub8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] - rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:rsub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x05 unimpl
+
+
+# rsubw rt, ra, rb ; res = (ra.W[0] - rb.W[0]) s>> 1; ; rt = SE(res);
+:rsubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x11 unimpl
+
+
+:sclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x42 unimpl
+
+:uclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x42 unimpl
+
+
+# sclip32 rt, ra, imm5u ; n = imm5u; + ; rt = SAT.Qn(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:sclip32 rd,rs1,imm5u is op0006=0x3f & rd & rs1 & imm5u & funct3=0x0 & funct7=0x72 unimpl
+
+
+:sclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x46 unimpl
+
+:uclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=2 & funct3=0x0 & funct7=0x46 unimpl
+
+
+# scmple16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] {le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:scmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0e unimpl
+
+
+# scmple8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] {le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:scmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0f unimpl
+
+
+# scmplt16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:scmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x06 unimpl
+
+
+# scmplt8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:scmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x07 unimpl
+
+
+# sll16 rt, ra, rb ; rt.H[_x_] = ra.H__x__ << rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:sll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2a unimpl
+
+
+# sll8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] << rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:sll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2e unimpl
+
+
+:slli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x3a unimpl
+
+
+:kslli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x3a unimpl
+
+
+:slli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3e unimpl
+
+
+:kslli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3e unimpl
+
+
+# smal rt, ra, rb ; RV32: ; a64 = r[aU].r[aL]; + ; t64 = a64 + rb.W[_0_].H[1]*rb.W[_0_].H[0]; + ; r[tU].r[tL] = t64; ; RV64: ; a64 = ra; + ; rt = a64 + rb.W[_1_].H[1]*rb.W[_1_].H[0] + rb.W[_0_].H[1]*rb.W[_0_].H[0];
+:smal rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2f unimpl
+
+
+# smalbb rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;
+:smalbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x44 unimpl
+
+
+# smalbt rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smalbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4c unimpl
+
+
+# smalda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;
+:smalda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x46 unimpl
+
+
+# smaldrs rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L - ra.H*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smaldrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4d unimpl
+
+
+# smalds rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;
+:smalds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x45 unimpl
+
+
+# smaltt rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smaltt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x54 unimpl
+
+
+# smalxda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smalxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4e unimpl
+
+
+# smalxds rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smalxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x55 unimpl
+
+
+# smaqa rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are signed numbers.
+:smaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x64 unimpl
+
+
+# smaqa.su rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] + ; ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra are signed numbers. ; Elements of rb are unsigned numbers.
+:smaqa.su rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x65 unimpl
+
+
+# smar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // signed + ; + ; r[tU].r[tL] = t64;
+:smar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x42 unimpl
+
+
+# smax16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] > rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:smax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x41 unimpl
+
+
+# smax8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] > rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:smax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x45 unimpl
+
+
+# smbb16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[0]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x04 unimpl
+
+
+# smbt16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0c unimpl
+
+
+# smdrs rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[0]*rb.W[_x_].H[0]) - (ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:smdrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x34 unimpl
+
+
+# smds rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[1]) - (ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:smds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2c unimpl
+
+
+# smin16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:smin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x40 unimpl
+
+
+# smin8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:smin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x44 unimpl
+
+
+# smmul rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_])[63:32]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x20 unimpl
+
+
+:smmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x28 unimpl
+
+
+# smmwb rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[0])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smmwb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x22 unimpl
+
+
+:smmwb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2a unimpl
+
+
+# smmwt rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[1])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smmwt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x32 unimpl
+
+
+:smmwt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3a unimpl
+
+
+# smslda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64;
+:smslda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x56 unimpl
+
+
+# smslxda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64;
+:smslxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5e unimpl
+
+
+# smsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // signed + ; + ; r[tU].r[tL] = t64;
+:smsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x43 unimpl
+
+
+# smtt16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[1]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0)
+:smtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x14 unimpl
+
+
+# smul16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_0_]; ; r[tH] = ra.H[_1_] s* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_1_];
+:smul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x50 unimpl
+
+
+:smul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x60 unimpl
+
+
+# smul8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_3_];
+:smul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x54 unimpl
+
+
+# smulx16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_1_]; ; r[tH] = ra.H[_1_] s* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_0_];
+:smulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x51 unimpl
+
+
+:smulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x61 unimpl
+
+
+# smulx8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_2_];
+:smulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x55 unimpl
+
+
+# smxds rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[0]) - (ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:smxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3c unimpl
+
+
+:sra.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x12 unimpl
+
+
+# sra16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] s>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:sra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x28 unimpl
+
+
+:sra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x30 unimpl
+
+
+# sra8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] s>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:sra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2c unimpl
+
+
+:sra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x34 unimpl
+
+
+:srai.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6a unimpl
+
+
+:srai16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x38 unimpl
+
+
+:srai16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x38 unimpl
+
+
+:srai8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3c unimpl
+
+
+:srai8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3c unimpl
+
+
+:sraiw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1a unimpl
+
+
+# srl16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] u>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:srl16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x29 unimpl
+
+
+:srl16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x31 unimpl
+
+
+# srl8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] u>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:srl8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2d unimpl
+
+
+:srl8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x35 unimpl
+
+
+:srli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x39 unimpl
+
+
+:srli16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x39 unimpl
+
+
+:srli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3d unimpl
+
+
+:srli8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3d unimpl
+
+
+# sub16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:sub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x21 unimpl
+
+
+# sub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 - b64; + ; + ; r[tU].r[tL] = t64;
+:sub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x61 unimpl
+
+
+# sub8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] - rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:sub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x25 unimpl
+
+
+# sunpkd810 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0)
+:sunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x08 unimpl
+
+
+# sunpkd820 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0)
+:sunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x09 unimpl
+
+
+# sunpkd830 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0)
+:sunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0a unimpl
+
+
+# sunpkd831 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1)
+:sunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0b unimpl
+
+
+# sunpkd832 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2)
+:sunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x13 unimpl
+
+
+# swap16 rt, ra ; === ; <<< ; ==== 8-bit Misc Instructions ; There are 11 instructions here. ; .SIMD 8-bit Miscellaneous Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",]
+:swap16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x19 unimpl
+
+
+# swap8 rt, ra ; === ; <<< ; ==== 8-bit Unpacking Instructions ; There are 8 instructions here. ; .8-bit Unpacking Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",]
+:swap8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x18 unimpl
+
+
+# uclip32 rt, ra, imm5u ; m = imm5u; + ; rt = SAT.Um(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0)
+:uclip32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7a unimpl
+
+
+# ucmple16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u{le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ucmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1e unimpl
+
+
+# ucmple8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u{le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ucmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1f unimpl
+
+
+# ucmplt16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ucmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x16 unimpl
+
+
+# ucmplt8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ucmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x17 unimpl
+
+
+# ukadd16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ukadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x18 unimpl
+
+
+# ukadd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 + b64); + ; + ; r[tU].r[tL] = t64;
+:ukadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x58 unimpl
+
+
+# ukadd8 rt, ra, rb ; rt.B[_x_] = SAT.U8(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ukadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1c unimpl
+
+
+:ukaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0a unimpl
+
+
+:ukaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x08 unimpl
+
+
+# ukcras16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:ukcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1a unimpl
+
+
+# ukcrsa16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:ukcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1b unimpl
+
+
+# ukmar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64;
+:ukmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5a unimpl
+
+
+# ukmsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 - ra*rb); + ; + ; r[tU].r[tL] = t64;
+:ukmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5b unimpl
+
+
+# uksub16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:uksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x19 unimpl
+
+
+# uksub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 - b64); + ; + ; r[tU].r[tL] = t64;
+:uksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x59 unimpl
+
+
+# uksub8 rt, ra, rb ; rt.B[_x_] = SAT.U8(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:uksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1d unimpl
+
+
+:uksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0b unimpl
+
+
+:uksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x09 unimpl
+
+
+# umaqa rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are unsigned numbers.
+:umaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x66 unimpl
+
+
+# umar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64;
+:umar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x52 unimpl
+
+
+# umax16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u> rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:umax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x49 unimpl
+
+
+# umax8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u> rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:umax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4d unimpl
+
+
+# umin16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:umin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x48 unimpl
+
+
+# umin8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:umin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4c unimpl
+
+
+# umsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64;
+:umsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x53 unimpl
+
+
+# umul16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_0_]; ; r[tH] = ra.H[_1_] u* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_1_];
+:umul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x58 unimpl
+
+
+:umul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x68 unimpl
+
+
+# umul8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_3_];
+:umul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5c unimpl
+
+
+# umulx16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_1_]; ; r[tH] = ra.H[_1_] u* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_0_];
+:umulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x59 unimpl
+
+
+:umulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x69 unimpl
+
+
+# umulx8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_2_];
+:umulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5d unimpl
+
+
+# uradd16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:uradd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x10 unimpl
+
+
+# uradd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) + CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64;
+:uradd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x50 unimpl
+
+
+# uradd8 rt, ra, rb ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) + CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:uradd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x14 unimpl
+
+
+# uraddw rt, ra, rb ; res = (CONCAT(1'b0,ra.W[0]) + CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res);
+:uraddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x18 unimpl
+
+
+# urcras16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:urcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x12 unimpl
+
+
+# urcrsa16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:urcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x13 unimpl
+
+
+# ursub16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0)
+:ursub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x11 unimpl
+
+
+# ursub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) - CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64;
+:ursub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x51 unimpl
+
+
+# ursub8 rt, ra, rb ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) - CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0)
+:ursub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x15 unimpl
+
+
+# ursubw rt, ra, rb ; res = (CONCAT(1'b0,ra.W[0]) - CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res);
+:ursubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x19 unimpl
+
+
+# wext rt, ra, rb ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = rb[4:0]; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword);
+:wext rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x67 unimpl
+
+
+# wexti rt, ra, imm5u ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = imm5u; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword);
+:wexti rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x6f unimpl
+
+
+# zunpkd810 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0)
+:zunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0c unimpl
+
+
+# zunpkd820 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0)
+:zunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0d unimpl
+
+
+# zunpkd830 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0)
+:zunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0e unimpl
+
+
+# zunpkd831 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1)
+:zunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0f unimpl
+
+
+# zunpkd832 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2)
+:zunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x17 unimpl
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc
index a419cc53b3..b0339867b1 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc
@@ -1,23 +1,13 @@
# RV32Q Standard Extension
-#TODO fix q
-#FIXME fix q
-@if FPSIZE == "128"
-
-# fadd.q D,S,T 06007053 fe00707f SIMPLE (0, 0)
-:fadd.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x3
-{
- frd = frs1 f+ frs2;
-}
-
# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0)
-:fadd.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3
+:fadd.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3
{
frd = frs1 f+ frs2;
}
# fclass.q d,S e6001053 fff0707f SIMPLE (0, 0)
-:fclass.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0
+:fclass.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0
{
#TODO
# rd = 0;
@@ -35,91 +25,57 @@
-# fcvt.d.q D,S 42307053 fff0707f SIMPLE (0, 0)
-:fcvt.d.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x21 & op2024=0x3
-{
- #TODO quad to double
-}
-
# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0)
-:fcvt.d.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3
+:fcvt.d.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3
{
#TODO double to quad
}
# fcvt.q.d D,S 46100053 fff0707f SIMPLE (0, 0)
-:fcvt.q.d frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1
+:fcvt.q.d frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1
{
frd = float2float(frs1);
}
# fcvt.q.s D,S 46000053 fff0707f SIMPLE (0, 0)
-:fcvt.q.s frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0
+:fcvt.q.s frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0
{
frd = float2float(frs1);
}
# fcvt.q.w D,s d6000053 fff0707f SIMPLE (0, 0)
-:fcvt.q.w frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0
+:fcvt.q.w frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0
{
frd = int2float(rs1);
}
# fcvt.q.wu D,s d6100053 fff0707f SIMPLE (0, 0)
-:fcvt.q.wu frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1
+:fcvt.q.wu frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1
{
frd = int2float(rs1);
}
-# fcvt.s.q D,S 40307053 fff0707f SIMPLE (0, 0)
-:fcvt.s.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x3
-{
- frd = float2float(frs1);
-}
-
# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0)
-:fcvt.s.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3
+:fcvt.s.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3
{
frd = float2float(frs1);
}
-# fcvt.w.q d,S c6007053 fff0707f SIMPLE (0, 0)
-:fcvt.w.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x0
-{
- rd = trunc(frs1);
-}
-
# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0)
-:fcvt.w.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
-{
- rd = trunc(frs1);
-}
-
-# fcvt.wu.q d,S c6107053 fff0707f SIMPLE (0, 0)
-:fcvt.wu.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x1
+:fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
{
rd = trunc(frs1);
}
# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0)
-:fcvt.wu.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
+:fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
{
rd = trunc(frs1);
}
-# fdiv.q D,S,T 1e007053 fe00707f SIMPLE (0, 0)
-:fdiv.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xf
-{
- local tfrs1:$(QFLEN) = frs1;
- local tfrs2:$(QFLEN) = frs2;
- local result:$(QFLEN) = tfrs1 f/ tfrs2;
- frd = result;
-}
-
-
# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0)
-:fdiv.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf
+:fdiv.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf
{
local tfrs1:$(QFLEN) = frs1;
local tfrs2:$(QFLEN) = frs2;
@@ -129,20 +85,20 @@
# feq.q d,S,T a6002053 fe00707f SIMPLE (0, 0)
-:feq.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53
+:feq.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53
{
rd = zext(frs1 f== frs2);
}
# fle.q d,S,T a6000053 fe00707f SIMPLE (0, 0)
-:fle.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53
+:fle.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53
{
rd = zext(frs1 f<= frs2);
}
# flq D,o(s) 00004007 0000707f OWORD|DREF (0, 16)
-:flq frd,immI(rs1) is RV32 & RVQ & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4
+:flq frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4
{
local ea:$(XLEN) = immI + rs1;
frd = *[ram]:16 ea;
@@ -150,27 +106,21 @@
# flt.q d,S,T a6001053 fe00707f SIMPLE (0, 0)
-:flt.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53
+:flt.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53
{
rd = zext(frs1 f< frs2);
}
-# fmadd.q D,S,T,R 06007043 0600707f SIMPLE (0, 0)
-:fmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x3
-{
- frd = (frs1 f* frs2) f+ frs3;
-}
-
# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0)
-:fmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3
+:fmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3
{
frd = (frs1 f* frs2) f+ frs3;
}
# fmax.q D,S,T 2e001053 fe00707f SIMPLE (0, 0)
-:fmax.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17
+:fmax.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17
{
local tmpfrs1 = frs1;
local tmpfrs2 = frs2;
@@ -184,7 +134,7 @@
}
# fmin.q D,S,T 2e000053 fe00707f SIMPLE (0, 0)
-:fmin.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17
+:fmin.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17
{
local tmpfrs1 = frs1;
local tmpfrs2 = frs2;
@@ -197,72 +147,50 @@
frd = tmpfrs1;
}
-# fmsub.q D,S,T,R 06007047 0600707f SIMPLE (0, 0)
-:fmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x3
-{
- frd = (frs1 f* frs2) f- frs3;
-}
-
# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0)
-:fmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3
+:fmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3
{
frd = (frs1 f* frs2) f- frs3;
}
-# fmul.q D,S,T 16007053 fe00707f SIMPLE (0, 0)
-:fmul.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xb
-{
- frd = frs1 f* frs2;
-}
-
# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0)
-:fmul.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb
+:fmul.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb
{
frd = frs1 f* frs2;
}
# fmv.q.x D,s f6000053 fff0707f SIMPLE (64, 0)
-:fmv.q.x frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0
+:fmv.q.x frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0
{
frd = int2float(rs1);
}
# fmv.x.q d,S e6000053 fff0707f SIMPLE (64, 0)
-:fmv.x.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0
+:fmv.x.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0
{
- rd = trunc(frs1);
+ local tmpreg:4 = &frs1;
+ local tmp:4 = *[register]:4 tmpreg;
+ assignW(rd, tmp);
}
-# fnmadd.q D,S,T,R 0600704f 0600707f SIMPLE (0, 0)
-:fnmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x3
-{
- frd = (f- (frs1 f* frs2)) f- frs3;
-}
-
# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0)
-:fnmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3
+:fnmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f- frs3;
}
-# fnmsub.q D,S,T,R 0600704b 0600707f SIMPLE (0, 0)
-:fnmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x3
-{
- frd = (f- (frs1 f* frs2)) f+ frs3;
-}
-
# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0)
-:fnmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3
+:fnmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3
{
frd = (f- (frs1 f* frs2)) f+ frs3;
}
# fsgnj.q D,S,T 26000053 fe00707f SIMPLE (0, 0)
-:fsgnj.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13
+:fsgnj.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13
{ local tmp = frs1;
tmp[127,1] = frs2[127,1];
frd = tmp;
@@ -270,7 +198,7 @@
# fsgnjn.q D,S,T 26001053 fe00707f SIMPLE (0, 0)
-:fsgnjn.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13
+:fsgnjn.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13
{
local tmp = frs1;
tmp[127,1] = !frs2[127,1];
@@ -279,7 +207,7 @@
# fsgnjx.q D,S,T 26002053 fe00707f SIMPLE (0, 0)
-:fsgnjx.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13
+:fsgnjx.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13
{
local tmp = frs1;
tmp[127,1] = tmp[127,1] ^ frs2[127,1];
@@ -287,36 +215,22 @@
}
-:fsq frs2,immS(rs1) is RV32 & RVQ & frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4
+:fsq frs2,immS(rs1) is frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4
{
local ea:$(XLEN) = immS + rs1;
*[ram]:$(QFLEN) ea = frs2;
}
-# fsqrt.q D,S 5e007053 fff0707f SIMPLE (0, 0)
-:fsqrt.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2f & op2024=0x0
-{
- frd = sqrt(frs1);
-}
-
# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0)
-:fsqrt.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0
+:fsqrt.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0
{
frd = sqrt(frs1);
}
-# fsub.q D,S,T 0e007053 fe00707f SIMPLE (0, 0)
-:fsub.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x7
-{
- frd = frs1 f- frs2;
-}
-
# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0)
-:fsub.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7
+:fsub.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7
{
frd = frs1 f- frs2;
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc
index 7b7d500206..cc9553d19e 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc
@@ -1,8 +1,7 @@
# RV64A Standard Extension (in addition to RV32A)
-
# amoadd.d d,t,0(s) 0000302f fe00707f QWORD|DREF (64, 8)
-:amoadd.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl
+:amoadd.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -14,7 +13,7 @@
# amoand.d d,t,0(s) 6000302f fe00707f QWORD|DREF (64, 8)
-:amoand.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl
+:amoand.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -26,7 +25,7 @@
# amomax.d d,t,0(s) a000302f fe00707f QWORD|DREF (64, 8)
-:amomax.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl
+:amomax.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -38,7 +37,7 @@
# amomaxu.d d,t,0(s) e000302f fe00707f QWORD|DREF (64, 8)
-:amomaxu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl
+:amomaxu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -50,7 +49,7 @@
# amomin.d d,t,0(s) 8000302f fe00707f QWORD|DREF (64, 8)
-:amomin.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl
+:amomin.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -62,7 +61,7 @@
# amominu.d d,t,0(s) c000302f fe00707f QWORD|DREF (64, 8)
-:amominu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl
+:amominu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -74,7 +73,7 @@
# amoor.d d,t,0(s) 4000302f fe00707f QWORD|DREF (64, 8)
-:amoor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl
+:amoor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -86,7 +85,7 @@
# amoswap.d d,t,0(s) 0800302f fe00707f QWORD|DREF (64, 8)
-:amoswap.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl
+:amoswap.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -97,7 +96,7 @@
# amoxor.d d,t,0(s) 2000302f fe00707f QWORD|DREF (64, 8)
-:amoxor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl
+:amoxor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl
{
local tmprs1 = rs1;
local tmprs2 = rs2L;
@@ -109,7 +108,7 @@
# lr.d d,0(s) 1000302f fff0707f QWORD|DREF (64, 8)
-:lr.d^aqrl rdL,(rs1) is RV64 & RVA & rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl
+:lr.d^aqrl rdL,(rs1) is rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl
{
RESERVE_ADDRESS = rs1;
RESERVE = 1;
@@ -119,14 +118,12 @@
# sc.d d,t,0(s) 1800302f fe00707f QWORD|DREF (64, 8)
-:sc.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl
+:sc.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl
{
local tmprs2 = rs2L;
local tmprs1 = rs1;
rdL = 1;
- if (RESERVE == 0) goto inst_next;
- if (RESERVE_ADDRESS != rs1) goto inst_next;
- if (RESERVE_LENGTH != 8) goto inst_next;
+ if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 8)) goto inst_next;
*[ram]:8 tmprs1 = tmprs2;
rdL = 0;
RESERVE_ADDRESS = 0;
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc
new file mode 100644
index 0000000000..e836096fcd
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc
@@ -0,0 +1,109 @@
+# RV64 Bitmanip Extension
+
+#TODO fix op2031
+:addiwu rd, rs1, op2031 is op0006=0x1b & op1214=0x4 & rd & op2031 & rs1 unimpl
+
+:addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:addwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:bdepw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:bextw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:bfpw rd, rs1, rs2 is op0006=0x3b & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:bmatflip rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x3 & op2531=0x30 & rd & rs1 unimpl
+
+:bmator rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:bmatxor rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:clmulhw rd, rs1, rs2 is op0006=0x3b & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clmulrw rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clmulw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl
+
+:clzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x13 & op2531=0x30 & rd & rs1 unimpl
+
+:crc32c.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1b & op2531=0x30 & rd & rs1 unimpl
+
+:ctzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl
+
+:fslw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl
+
+#TODO fix op2024
+:fsriw rd, rs1, rs3, op2024 is op0006=0x1b & op1214=0x5 & op2526=0x2 & op2024 & rd & rs1 & rs3 unimpl
+
+:fsrw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl
+
+#TODO fix op2024
+:gorciw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x14 & op2024 & rd & rs1 unimpl
+
+:gorcw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:greviw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x34 & op2024 & rd & rs1 unimpl
+
+:grevw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl
+
+:packuw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:packw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+:pcntw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl
+
+:rolw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:roriw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x30 & op2024 & rd & rs1 unimpl
+
+:rorw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:sbclriw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x24 & op2024 & rd & rs1 unimpl
+
+:sbclrw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:sbextw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:sbinviw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x34 & op2024 & rd & rs1 unimpl
+
+:sbinvw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:sbsetiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x14 & op2024 & rd & rs1 unimpl
+
+:sbsetw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl
+
+:sh1addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:sh2addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:sh3addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:shflw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2026
+:slliu.w rd, rs1, op2026 is op0006=0x1b & op1214=0x1 & op2731=0x1 & op2026 & rd & rs1 unimpl
+
+#TODO fix op2024
+:sloiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x10 & op2024 & rd & rs1 unimpl
+
+:slow rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+#TODO fix op2024
+:sroiw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x10 & op2024 & rd & rs1 unimpl
+
+:srow rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl
+
+:subu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x24 & rd & rs1 & rs2 unimpl
+
+:subwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x25 & rd & rs1 & rs2 unimpl
+
+:unshflw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc
index ff6b579308..0436594765 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc
@@ -1,35 +1,15 @@
# RV64D Standard Extension (in addition to RV32D)
-@if FPSIZE == "64"
-
-# fcvt.d.l D,s d2207053 fff0707f SIMPLE (64, 0)
-:fcvt.d.l frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x2
-{
- local tmp:8 = int2float(rs1L);
- frd = tmp;
-}
-
-
# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0)
-:fcvt.d.l frd,rs1L,FRM is RV64 & RVD & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
+:fcvt.d.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
{
local tmp:8 = int2float(rs1L);
frd = tmp;
}
-# fcvt.d.lu D,s d2307053 fff0707f SIMPLE (64, 0)
-:fcvt.d.lu frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x3
-{
- #ATTN unsigned can be an issue here
- local u64:$(XLEN2) = zext(rs1L);
- local tmp:8 = int2float(u64);
- frd = tmp;
-}
-
-
# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0)
-:fcvt.d.lu frd,rs1L,FRM is RV64 & RVD & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
+:fcvt.d.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
@@ -38,30 +18,15 @@
}
-# fcvt.l.d d,S c2207053 fff0707f SIMPLE (64, 0)
-:fcvt.l.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x2
-{
- rdL = trunc(frs1D);
-}
-
-
# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0)
-:fcvt.l.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
+:fcvt.l.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
{
rdL = trunc(frs1D);
}
-# fcvt.lu.d d,S c2307053 fff0707f SIMPLE (64, 0)
-:fcvt.lu.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x3
-{
- #TODO unsigned
- rdL = trunc(frs1D);
-}
-
-
# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0)
-:fcvt.lu.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
+:fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1D);
@@ -69,14 +34,14 @@
# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0)
-:fmv.d.x frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0
+:fmv.d.x frd,rs1L is frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0
{
frd = rs1L;
}
-:fmv.x.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0
+:fmv.x.d rdL,frs1D is frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0
{
- rdL = frs1D;
+ local tmpreg:4 = &frs1D;
+ local tmp:8 = *[register]:8 tmpreg;
+ rdL = tmp;
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc
index 61ae948d92..9a88490281 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc
@@ -1,70 +1,33 @@
# RV64F Standard Extension (in addition to RV32F)
-@if FPSIZE != ""
-
-# fcvt.l.s d,S c0207053 fff0707f SIMPLE (64, 0)
-:fcvt.l.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x2
-{
- rdL = trunc(frs1S);
-}
-
-
# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0)
-:fcvt.l.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2
+:fcvt.l.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2
{
rdL = trunc(frs1S);
}
-# fcvt.lu.s d,S c0307053 fff0707f SIMPLE (64, 0)
-:fcvt.lu.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x3
-{
- #TODO unsigned
- rdL = trunc(frs1S);
-}
-
-
# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0)
-:fcvt.lu.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
+:fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
{
#TODO unsigned
rdL = trunc(frs1S);
}
-# fcvt.s.l D,s d0207053 fff0707f SIMPLE (64, 0)
-:fcvt.s.l frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x2
-{
- local tmp:4 = int2float(rs1L);
- fassignS(frd, tmp);
-}
-
-
# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0)
-:fcvt.s.l frd,rs1L,FRM is RV64 & RVF & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2
+:fcvt.s.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2
{
local tmp:4 = int2float(rs1L);
fassignS(frd, tmp);
}
-# fcvt.s.lu D,s d0307053 fff0707f SIMPLE (64, 0)
-:fcvt.s.lu frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x3
-{
- #ATTN unsigned can be an issue here
- local u64:$(XLEN2) = zext(rs1L);
- local tmp:4 = int2float(u64);
- fassignS(frd, tmp);
-}
-
-
# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0)
-:fcvt.s.lu frd,rs1L,FRM is RV64 & RVF & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3
+:fcvt.s.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3
{
#ATTN unsigned can be an issue here
local u64:$(XLEN2) = zext(rs1L);
local tmp:4 = int2float(u64);
fassignS(frd, tmp);
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc
index b6f6d6faeb..c0ad6f0d37 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc
@@ -1,14 +1,13 @@
# RV64I Base Instruction Set (in addition to RV32I)
-
# addiw d,s,j 0000001b 0000707f SIMPLE (64, 0)
-:addiw rd,rs1,immI is RV64 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031>0
+:addiw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0
{
local result = rs1 + immI;
rd = sext(result:4);
}
-:sext.w rd,rs1 is RV64 & RVI & rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0
+:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0
{
local result = rs1;
rd = sext(result:4);
@@ -17,7 +16,7 @@
# addw d,s,t 0000003b fe00707f SIMPLE (64, 0)
-:addw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0
+:addw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
@@ -27,7 +26,7 @@
# ld d,o(s) 00003003 0000707f QWORD|DREF (64, 8)
-:ld rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3
+:ld rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3
{
local ea:$(XLEN) = rs1 + immI;
rd = *[ram]:8 ea;
@@ -35,7 +34,7 @@
# lwu d,o(s) 00006003 0000707f DWORD|DREF (64, 4)
-:lwu rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6
+:lwu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6
{
local ea:$(XLEN) = rs1 + immI;
rd = zext(*[ram]:4 ea);
@@ -43,7 +42,7 @@
# sd t,q(s) 00003023 0000707f QWORD|DREF (64, 8)
-:sd rs2,immS(rs1) is RV64 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3
+:sd rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3
{
local ea:$(XLEN) = rs1 + immS;
*[ram]:8 ea = rs2;
@@ -51,7 +50,7 @@
# slliw d,s,< 0000101b fe00707f SIMPLE (64, 0)
-:slliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0
+:slliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0
{
local tmp:4 = rs1:4;
tmp = tmp << shamt5;
@@ -60,7 +59,7 @@
# sllw d,s,t 0000103b fe00707f SIMPLE (64, 0)
-:sllw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0
+:sllw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
@@ -70,7 +69,7 @@
# sraiw d,s,< 4000501b fe00707f SIMPLE (64, 0)
-:sraiw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20
+:sraiw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20
{
local tmp:4 = rs1:4;
tmp = tmp s>> shamt5;
@@ -79,7 +78,7 @@
# sraw d,s,t 4000503b fe00707f SIMPLE (64, 0)
-:sraw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20
+:sraw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
@@ -89,7 +88,7 @@
# srliw d,s,< 0000501b fe00707f SIMPLE (64, 0)
-:srliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0
+:srliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0
{
local tmp:4 = rs1:4;
tmp = tmp >> shamt5;
@@ -98,7 +97,7 @@
# srlw d,s,t 0000503b fe00707f SIMPLE (64, 0)
-:srlw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0
+:srlw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0
{
local shift:$(XLEN) = rs2 & 0x1f;
local tmp:4 = rs1:4;
@@ -108,14 +107,14 @@
# subw d,s,t 4000003b fe00707f SIMPLE (64, 0)
-:subw rd,rs1W,rs2W is RV64 & RVI & rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20
+:subw rd,rs1W,rs2W is rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20
{
local result = rs1W - rs2W;
rd = sext(result);
}
# negw d,t 4000003b fe0ff07f ALIAS (64, 0)
-:negw rd,rs2W is RV64 & RVI & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
+:negw rd,rs2W is rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0
{
local tmp = -rs2W;
rd = sext(tmp);
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc
new file mode 100644
index 0000000000..fc79f408ca
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc
@@ -0,0 +1,35 @@
+# RV64 Crypto Extension
+# NOTE 0.6.2
+
+# 0001010 rs2 rs1 010 rd 0101011 saes64.decs
+:saes64.decs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x0a unimpl
+
+# 0001001 rs2 rs1 010 rd 0101011 saes64.decsm
+:saes64.decsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x09 unimpl
+
+# 0001000 rs2 rs1 010 rd 0101011 saes64.encs
+:saes64.encs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x08 unimpl
+
+# 0000111 rs2 rs1 010 rd 0101011 saes64.encsm
+:saes64.encsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x07 unimpl
+
+# 0000110 00001 rs1 010 rd 0101011 saes64.imix
+:saes64.imix rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x2 & op2024=0x01 & op2531=0x06 unimpl
+
+# 0000100 0 rcon rs1 010 rd 0101011 saes64.ks1
+:saes64.ks1 rd, rs1, rcon is rd & rs1 & rcon & op0006=0x5b & op1214=0x2 & op2424=0x0 & op2531=0x04 unimpl
+
+# 0000101 rs2 rs1 010 rd 0101011 saes64.ks2
+:saes64.ks2 rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x05 unimpl
+
+# 0000111 00100 rs1 111 rd 0101011 ssha512.sig0
+:ssha512.sig0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x04 & op2531=0x07 unimpl
+
+# 0000111 00101 rs1 111 rd 0101011 ssha512.sig1
+:ssha512.sig1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x05 & op2531=0x07 unimpl
+
+# 0000111 00110 rs1 111 rd 0101011 ssha512.sum0
+:ssha512.sum0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x06 & op2531=0x07 unimpl
+
+# 0000111 00111 rs1 111 rd 0101011 ssha512.sum1
+:ssha512.sum1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x07 & op2531=0x07 unimpl
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc
index 53dc93a7dd..8da116d62e 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc
@@ -1,8 +1,7 @@
# RV64M Standard Exention (in addition to RV32M)
-
# divuw d,s,t 0200503b fe00707f SIMPLE (64, 0)
-:divuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1
+:divuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
@@ -11,7 +10,7 @@
# divw d,s,t 0200403b fe00707f SIMPLE (64, 0)
-:divw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1
+:divw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
@@ -20,7 +19,7 @@
# mulw d,s,t 0200003b fe00707f SIMPLE (64, 0)
-:mulw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1
+:mulw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1
{
local tmp:4 = rs1:4 * rs2:4;
rd = sext(tmp);
@@ -28,7 +27,7 @@
# remuw d,s,t 0200703b fe00707f SIMPLE (64, 0)
-:remuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1
+:remuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
@@ -37,7 +36,7 @@
# remw d,s,t 0200603b fe00707f SIMPLE (64, 0)
-:remw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1
+:remw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc
new file mode 100644
index 0000000000..33bc3839f4
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc
@@ -0,0 +1,294 @@
+# RV64 P Extension
+
+
+# add32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0)
+:add32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x20 unimpl
+
+
+# cras32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x_]; ; (RV64: __x__=1)
+:cras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x22 unimpl
+
+
+# crsa32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x_]; ; (RV64: __x__=1)
+:crsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x23 unimpl
+
+
+# kadd32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); ; (RV64: __x__=1..0)
+:kadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x08 unimpl
+
+
+# kcras32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1)
+:kcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0a unimpl
+
+
+# kcrsa32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1)
+:kcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0b unimpl
+
+
+:kmabb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2d unimpl
+
+
+:kmabt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x35 unimpl
+
+
+:kmadrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x36 unimpl
+
+
+:kmads32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2e unimpl
+
+
+:kmatt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3d unimpl
+
+
+:kmaxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x25 unimpl
+
+
+:kmaxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3e unimpl
+
+
+:kmda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1c unimpl
+
+
+:kmsda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x26 unimpl
+
+
+:kmsxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x27 unimpl
+
+
+:kmxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1d unimpl
+
+
+# ksll32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[4:0]); ; (RV64: __x__=1..0)
+:ksll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x32 unimpl
+
+
+# kslli32 rt, ra, im5u ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << im5u); ; (RV64: __x__=1..0)
+:kslli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x42 unimpl
+
+
+# kslra32 rt, ra, rb ; if (rb[5:0] < 0) + ; rt.W[_x_] = ra.W[_x_] s>> -rb[5:0]; ; if (rb[5:0] > 0) + ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[5:0]); ; (RV64: __x__=1..0)
+:kslra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2b unimpl
+
+
+:kslra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x33 unimpl
+
+
+# kstas16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:kstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x62 unimpl
+
+
+# kstas32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1)
+:kstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x60 unimpl
+
+
+# kstsa16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:kstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x63 unimpl
+
+
+# kstsa32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1)
+:kstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x61 unimpl
+
+
+# ksub32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0)
+:ksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x09 unimpl
+
+
+# pkbb32 rt, ra, rb ; rt = CONCAT(ra.W[_0_], rb.W[_0_]);
+:pkbb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x07 unimpl
+
+
+# pkbt32 rt, ra, rb ; rt = CONCAT(ra.W[_0_], rb.W[_1_]);
+:pkbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0f unimpl
+
+
+# pktb32 rt, ra, rb ; rt = CONCAT(ra.W[_1_], rb.W[_0_]);
+:pktb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1f unimpl
+
+
+# pktt32 rt, ra, rb ; rt = CONCAT(ra.W[_1_], rb.W[_1_]);
+:pktt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x17 unimpl
+
+
+# radd32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0)
+:radd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x00 unimpl
+
+
+# rcras32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x_]) s>> 1; ; (RV64: __x__=1)
+:rcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x02 unimpl
+
+
+# rcrsa32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1)
+:rcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x03 unimpl
+
+
+# rstas16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:rstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5a unimpl
+
+
+# rstas32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1)
+:rstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x58 unimpl
+
+
+# rstsa16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:rstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5b unimpl
+
+
+# rstsa32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1)
+:rstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x59 unimpl
+
+
+# rsub32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0)
+:rsub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x01 unimpl
+
+
+# sll32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] << rb[4:0]; ; (RV64: __x__=1..0)
+:sll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2a unimpl
+
+
+# slli32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] << im5u; ; (RV64: __x__=1..0)
+:slli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3a unimpl
+
+
+# smax32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] > rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)
+:smax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x49 unimpl
+
+
+:smbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0c unimpl
+
+
+:smdrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x34 unimpl
+
+
+:smds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2c unimpl
+
+
+# smin32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] < rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)
+:smin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x48 unimpl
+
+
+:smtt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x14 unimpl
+
+
+:smxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3c unimpl
+
+
+# sra32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] s>> rb[4:0]; ; (RV64: __x__=1..0)
+:sra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x28 unimpl
+
+
+:sra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x30 unimpl
+
+
+# srai32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] s>> im5u; ; (RV64: __x__=1..0)
+:srai32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x38 unimpl
+
+
+:srai32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x40 unimpl
+
+
+# srl32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] u>> rb[4:0]; ; (RV64: __x__=1..0)
+:srl32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x29 unimpl
+
+
+:srl32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x31 unimpl
+
+
+# srli32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] u>> im5u; ; (RV64: __x__=1..0)
+:srli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x39 unimpl
+
+
+:srli32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x41 unimpl
+
+
+# stas16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3)
+:stas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7a unimpl
+
+
+# stas32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x-1_]; ; (RV64: __x__=1)
+:stas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x78 unimpl
+
+
+# stsa16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3)
+:stsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7b unimpl
+
+
+# stsa32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x-1_]; ; (RV64: __x__=1)
+:stsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x79 unimpl
+
+
+# sub32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; ; (RV64: __x__=1..0)
+:sub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x21 unimpl
+
+
+# ukadd32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0)
+:ukadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x18 unimpl
+
+
+# ukcras32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1)
+:ukcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1a unimpl
+
+
+# ukcrsa32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1)
+:ukcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1b unimpl
+
+
+# ukstas16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:ukstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x72 unimpl
+
+
+# ukstas32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1)
+:ukstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x70 unimpl
+
+
+# ukstsa16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3)
+:ukstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x73 unimpl
+
+
+# ukstsa32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1)
+:ukstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x71 unimpl
+
+
+# uksub32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0)
+:uksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x19 unimpl
+
+
+# umax32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] u> rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)
+:umax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x51 unimpl
+
+
+# umin32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] u< rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0)
+:umin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x50 unimpl
+
+
+# uradd32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0)
+:uradd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x10 unimpl
+
+
+# urcras32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1)
+:urcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x12 unimpl
+
+
+# urcrsa32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1)
+:urcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x13 unimpl
+
+
+# urstas16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:urstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6a unimpl
+
+
+# urstas32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1)
+:urstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x68 unimpl
+
+
+# urstsa16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3)
+:urstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6b unimpl
+
+
+# urstsa32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1)
+:urstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x69 unimpl
+
+
+# ursub32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0)
+:ursub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x11 unimpl
+
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc
index 6e7cc1e4ee..51849d3a64 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc
@@ -1,62 +1,28 @@
# RV64Q Standard Extension (in addition to RV32Q)
-#TODO fix q
-#FIXME fix q
-@if FPSIZE == "128"
-
-# fcvt.l.q d,S c6207053 fff0707f SIMPLE (64, 0)
-:fcvt.l.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x2
-{
- rd = trunc(frs1);
-}
-
-
# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0)
-:fcvt.l.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2
-{
- rd = trunc(frs1);
-}
-
-
-# fcvt.lu.q d,S c6307053 fff0707f SIMPLE (64, 0)
-:fcvt.lu.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x3
+:fcvt.l.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2
{
rd = trunc(frs1);
}
# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0)
-:fcvt.lu.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3
+:fcvt.lu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3
{
rd = trunc(frs1);
}
-# fcvt.q.l D,s d6207053 fff0707f SIMPLE (64, 0)
-:fcvt.q.l frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x2
-{
- frd = int2float(rs1);
-}
-
-
# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0)
-:fcvt.q.l frd,rs1,FRM is RV64 & RVQ & frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2
-{
- frd = int2float(rs1);
-}
-
-
-# fcvt.q.lu D,s d6307053 fff0707f SIMPLE (64, 0)
-:fcvt.q.lu frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x3
+:fcvt.q.l frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2
{
frd = int2float(rs1);
}
# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0)
-:fcvt.q.lu frd,rs1,FRM is RV64 & RVQ & frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3
+:fcvt.q.lu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3
{
frd = int2float(rs1);
}
-
-@endif
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
index 48d96195be..6d5cd7dd72 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
@@ -1,54 +1,48 @@
# RVC Standard Extension for Compressed Instructions
-
-# c.add d,CV 00009002 0000f003 SIMPLE (0, 0)
-:c.add crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1
+# c.add d,CV 00009002 0000f003 SIMPLE (0, 0)
+:c.add crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1
{
crd = crd + crs2;
}
-# c.ebreak 00009002 0000ffff SIMPLE (0, 0)
-:c.ebreak is RVC & cop0001=0x2 & cop1315=0x4 & cop0212=0x400
-{
-}
-
# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0)
# There may be other nop forms here if (cop0711=0) or (cop1212=0 & cop0206=0)
-:c.addi crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x0
+:c.addi crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x0
{
crd = crd + cimmI;
}
-:c.nop is RVC & cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0
+:c.nop is cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0
{
local NOP:1 = 0;
NOP = NOP;
}
# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0)
-:c.addi16sp sp,caddi16spimm is RVC & cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3
+:c.addi16sp sp,caddi16spimm is cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3
{
sp = sp + caddi16spimm;
}
# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0)
-:c.addi4spn cr0204s,sp,caddi4spnimm is RVC & caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0
+:c.addi4spn cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0
{
cr0204s = sp + caddi4spnimm;
}
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0)
-:c.addiw crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x1
+:c.addiw crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x1
{
- local tmp:8 = crd + cimmI;
- crd = sext(tmp:4);
+ local tmp:$(XLEN) = crd + cimmI;
+ crd = sext(tmp:$(WXLEN));
}
@endif
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.addw Cs,Ct 00009c21 0000fc63 SIMPLE (64, 0)
-:c.addw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7
+:c.addw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7
{
local tmp:4 = cr0709s:4 + cr0204s:4;
cr0709s = sext(tmp);
@@ -56,110 +50,118 @@
@endif
# c.and Cs,Ct 00008c61 0000fc63 SIMPLE (0, 0)
-:c.and cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3
+:c.and cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3
{
cr0709s = cr0709s & cr0204s;
}
# c.andi Cs,Co 00008801 0000ec03 SIMPLE (0, 0)
-:c.andi cr0709s,cimmI is RVC & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2
+:c.andi cr0709s,cimmI is cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2
{
cr0709s = cr0709s & cimmI;
}
# c.beqz Cs,Cp 0000c001 0000e003 CONDBRANCH (0, 0)
-:c.beqz cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x6
+:c.beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6
{
if (cr0709s == 0) goto cbimm;
}
# c.bnez Cs,Cp 0000e001 0000e003 CONDBRANCH (0, 0)
-:c.bnez cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x7
+:c.bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7
{
if (cr0709s != 0) goto cbimm;
}
-@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64"
+# c.ebreak 00009002 0000ffff SIMPLE (0, 0)
+:c.ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400
+{
+ ebreak();
+}
+
+@if ADDRSIZE == "32" || ADDRSIZE == "64"
+@if FPSIZE == "64"
# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8)
-:c.fld cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm
+:c.fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm
{
- local ea:$(XLEN) = cldimm + cr0709s;
- cfr0204s = *[ram]:8 ea;
+ local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;
+ cfr0204s = *[ram]:$(DFLEN) ea;
}
-@endif
-@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64"
+
# c.fldsp D,Cn(Cc) 00002002 0000e003 QWORD|DREF (0, 8)
-:c.fldsp cfrd,cldspimm(sp) is RVC & RVD & cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm
+:c.fldsp cfrd,cldspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm
{
- local ea:$(XLEN) = cldspimm + sp;
- cfrd = *[ram]:8 ea;
+ local ea:$(XLEN) = cldspimm:$(XLEN) + sp;
+ cfrd = *[ram]:$(DFLEN) ea;
}
@endif
+@endif
-@if ADDRSIZE == "32" && FPSIZE != ""
+@if ADDRSIZE == "32"
+@if FPSIZE != "0"
# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4)
-:c.flw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm
+:c.flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm
{
- local ea:$(XLEN) = clwimm + cr0709s;
- cfr0204s = *[ram]:4 ea;
+ local ea:$(XLEN) = clwimm:$(XLEN) + cr0709s;
+ cfr0204s = *[ram]:$(SFLEN) ea;
+}
+
+
+# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4)
+:c.flwsp cfrd,clwspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm
+{
+ local ea:$(XLEN) = clwspimm:$(XLEN) + sp;
+ cfrd = *[ram]:$(SFLEN) ea;
}
@endif
-
-@if ADDRSIZE == "32" && FPSIZE != ""
-# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4)
-:c.flwsp cfrd,clwspimm(sp) is RVC & RVF & cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm
-{
- local ea:$(XLEN) = clwspimm + sp;
- cfrd = *[ram]:4 ea;
-}
@endif
@if ADDRSIZE == "32" || ADDRSIZE == "64"
+@if FPSIZE == "64"
# c.fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF (0, 8)
-:c.fsd cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm
+:c.fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm
{
local ea:$(XLEN) = cldimm + cr0709s;
*[ram]:8 ea = cfr0204s;
}
-@endif
-@if ADDRSIZE == "32" || ADDRSIZE == "64"
# c.fsdsp CT,CN(Cc) 0000a002 0000e003 QWORD|DREF (0, 8)
-:c.fsdsp cfr0206,csdspimm(sp) is RVC & RVD & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm
+:c.fsdsp cfr0206,csdspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm
{
local ea:$(XLEN) = csdspimm + sp;
*[ram]:8 ea = cfr0206;
}
@endif
+@endif
@if ADDRSIZE == "32"
+@if FPSIZE == "32"
# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4)
-:c.fsw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm
+:c.fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
*[ram]:4 ea = cfr0204s;
}
-@endif
-@if ADDRSIZE == "32"
# c.fswsp CT,CM(Cc) 0000e002 0000e003 DWORD|DREF (32, 4)
-:c.fswsp cfr0206,cswspimm(sp) is RVC & RVF & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm
+:c.fswsp cfr0206,cswspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm
{
local ea:$(XLEN) = cswspimm + sp;
*[ram]:4 ea = cfr0206:4;
}
@endif
+@endif
# c.j Ca 0000a001 0000e003 BRANCH (0, 0)
-:c.j cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x5
+:c.j cjimm is cjimm & cop0001=0x1 & cop1315=0x5
{
goto cjimm;
}
@if ADDRSIZE == "32"
# c.jal Ca 00002001 0000e003 JSR (32, 0)
-:c.jal cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x1
+:c.jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1
{
ra = inst_next;
call cjimm;
@@ -167,162 +169,160 @@
@endif
# c.jalr d 00009002 0000f07f JSR (0, 0)
-:c.jalr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1
+:c.jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1
{
ra = inst_next;
call [crd];
}
# c.jr d 00008002 0000f07f BRANCH (0, 0)
-:c.jr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0
+:c.jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0
{
goto [crd];
}
# ret 00008082 0000ffff BRANCH|ALIAS (0, 0)
-:ret is RVC & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1
+:ret is cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1
{
return [ra];
}
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF (64, 8)
-:c.ld cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm
+:c.ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm
{
- local ea:$(XLEN) = cldimm + cr0709s;
- zassignD(cr0204s, *[ram]:8 ea);
+ local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;
+ assignD(cr0204s, *[ram]:$(DXLEN) ea);
}
@endif
@if ADDRSIZE == "128"
-:c.lq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm
+:c.lq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm
{
- local ea:$(XLEN) = clqimm + cr0709s;
- cr0204s = *[ram]:16 ea;
+ local ea:$(XLEN) = clqimm:$(XLEN) + cr0709s;
+ cr0204s = *[ram]:$(QXLEN) ea;
}
@endif
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8)
-:c.ldsp crd,cldspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm
+:c.ldsp crd,cldspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm
{
local ea:$(XLEN) = cldspimm + sp;
- zassignD(crd, *[ram]:8 ea);
+ assignD(crd, *[ram]:$(DXLEN) ea);
}
@endif
@if ADDRSIZE == "128"
-:c.lqsp crd,clqspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & clqspimm
+:c.lqsp crd,clqspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x1 & clqspimm
{
local ea:$(XLEN) = clqspimm + sp;
- crd = *[ram]:16 ea;
+ crd = *[ram]:$(QXLEN) ea;
}
@endif
# c.li d,Co 00004001 0000e003 SIMPLE (0, 0)
-:c.li crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x2
+:c.li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2
{
crd = cimmI;
}
# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0)
-:c.lui crd,cbigimm is RVC & crd & cbigimm & cop0001=0x1 & cop1315=0x3
+:c.lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3
{
- crd = cbigimm << 12;
+ crd = cbigimm;
}
# c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4)
-:c.lw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm
+:c.lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
- zassignW(cr0204s, *[ram]:4 ea);
+ assignW(cr0204s, *[ram]:4 ea);
}
# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0)
-:c.lwsp crd,clwspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm
+:c.lwsp crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm
{
local ea:$(XLEN) = clwspimm + sp;
- zassignW(crd, *[ram]:4 ea);
+ assignW(crd, *[ram]:4 ea);
}
# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0)
-:c.mv crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0
+:c.mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0
{
crd = crs2;
}
# c.or Cs,Ct 00008c41 0000fc63 SIMPLE (0, 0)
-:c.or cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3
+:c.or cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3
{
cr0709s = cr0709s | cr0204s;
}
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF (64, 8)
-:c.sd cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm
+:c.sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm
{
- local ea:$(XLEN) = cldimm + cr0709s;
- *[ram]:8 ea = cr0204s:8;
+ local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s;
+ *[ram]:$(DXLEN) ea = cr0204s:$(DXLEN);
}
-@endif
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
# c.sdsp CV,CN(Cc) 0000e002 0000e003 QWORD|DREF (64, 8)
-:c.sdsp crs2,csdspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm
+:c.sdsp crs2,csdspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm
{
- local ea:$(XLEN) = csdspimm + sp;
- *[ram]:8 ea = crs2:8;
+ local ea:$(XLEN) = csdspimm:$(XLEN) + sp;
+ *[ram]:$(DXLEN) ea = crs2:$(DXLEN);
}
@endif
# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0)
-:c.slli crd,c6imm is RVC & crd & c6imm & cop0001=0x2 & cop1315=0x0
+:c.slli crd,c6imm is crd & c6imm & cop0001=0x2 & cop1315=0x0
{
crd = crd << c6imm;
}
#TODO hint?
# c.slli64 d 00000002 0000f07f SIMPLE (0, 0)
-:c.slli64 crd is RVC & crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0
+:c.slli64 crd is crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0
{
crd = crd << 0;
}
# c.srai Cs,C> 00008401 0000ec03 SIMPLE (0, 0)
-:c.srai cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1
+:c.srai cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1
{
cr0709s = cr0709s s>> c6imm;
}
#TODO hint?
# c.srai64 Cs 00008401 0000fc7f SIMPLE (0, 0)
-:c.srai64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1
+:c.srai64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1
{
cr0709s = cr0709s s>> 0;
}
# c.srli Cs,C> 00008001 0000ec03 SIMPLE (0, 0)
-:c.srli cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0
+:c.srli cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0
{
cr0709s = cr0709s >> c6imm;
}
#TODO hint?
# c.srli64 Cs 00008001 0000fc7f SIMPLE (0, 0)
-:c.srli64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0
+:c.srli64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0
{
cr0709s = cr0709s >> 0;
}
# c.sub Cs,Ct 00008c01 0000fc63 SIMPLE (0, 0)
-:c.sub cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3
+:c.sub cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3
{
cr0709s = cr0709s - cr0204s;
}
-@if ADDRSIZE == "64" || ADDRSIZE == "128"
+@if (ADDRSIZE == "64") || (ADDRSIZE == "128")
# c.subw Cs,Ct 00009c01 0000fc63 SIMPLE (64, 0)
-:c.subw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7
+:c.subw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7
{
local tmp:4 = cr0709s:4 - cr0204s:4;
cr0709s = sext(tmp);
@@ -330,22 +330,20 @@
@endif
# c.sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF (0, 4)
-:c.sw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm
+:c.sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm
{
local ea:$(XLEN) = clwimm + cr0709s;
*[ram]:4 ea = cr0204s:4;
}
@if ADDRSIZE == "128"
-:c.sq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm
+:c.sq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm
{
local ea:$(XLEN) = clqimm + cr0709s;
*[ram]:16 ea = cr0204s;
}
-@endif
-@if ADDRSIZE == "128"
-:c.sqsp crs2,csqspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm
+:c.sqsp crs2,csqspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm
{
local ea:$(XLEN) = csqspimm + sp;
*[ram]:16 ea = crs2;
@@ -353,20 +351,20 @@
@endif
# c.swsp CV,CM(Cc) 0000c002 0000e003 DWORD|DREF (0, 4)
-:c.swsp crs2,cswspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm
+:c.swsp crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm
{
local ea:$(XLEN) = cswspimm + sp;
*[ram]:4 ea = crs2:4;
}
# c.unimp 00000000 0000ffff SIMPLE (0, 0)
-:c.unimp is RVC & cop0001=0x0 & cop1315=0x0 & cop0212=0x0
+:c.unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0
{
trap();
}
# c.xor Cs,Ct 00008c21 0000fc63 SIMPLE (0, 0)
-:c.xor cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3
+:c.xor cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3
{
cr0709s = cr0709s ^ cr0204s;
}
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc
new file mode 100644
index 0000000000..f21ed223f0
--- /dev/null
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc
@@ -0,0 +1,1955 @@
+# Vector
+
+# sew: "e8" is vsew=0 {}
+# sew: "e16" is vsew=1 {}
+# sew: "e32" is vsew=2 {}
+# sew: "e64" is vsew=3 {}
+# sew: "e128" is vsew=4 {}
+# sew: "e256" is vsew=5 {}
+# sew: "e512" is vsew=6 {}
+# sew: "e1024" is vsew=7 {}
+
+# vmul: "m1" is vlmul=0 {}
+# vmul: "m2" is vlmul=1 {}
+# vmul: "m4" is vlmul=2 {}
+# vmul: "m8" is vlmul=3 {}
+# vmul: "mf8" is vlmul=5 {}
+# vmul: "mf4" is vlmul=6 {}
+# vmul: "mf2" is vlmul=7 {}
+
+# vmask: "mu" is vma=0 {}
+# vmask: "ma" is vma=1 {}
+# vtail: "tu" is vta=0 {}
+# vtail: "ta" is vta=1 {}
+
+#TODO possible tables
+# mop=0 unit-stride VLE
+# mop=2 strided VLSE
+# mop=3 indexed VLXEI
+# mop=0 unit-stride VSE
+# mop=1 indexed-unordered VSUXEI
+# mop=2 strided VSSE
+# mop=3 indexed-ordered VSXEI
+# lumop=0 unit-stride
+# lumop=8 unit-stride,whole registers
+# lumop=16 unit-stride fault-only-first
+# sumop=0 unit-stride
+# sumop=8 unit-stride,whole registers
+# sumop=16 unit-stride fault-only-first
+# nfields imm is nf [ imm = nf + 1; ] { export *[const]:1 imm; }
+
+
+# vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1)
+:vaadd.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1)
+:vaadd.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1)
+:vaaddu.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1)
+:vaaddu.vx vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vadc.vim vd, vs2, simm5, v0 # Vector-immediate
+:vadc.vim vd, vs2, simm5, v0 is op2631=0x10 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl
+
+# vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vadc.vvm vd, vs2, vs1, v0 # Vector-vector
+:vadc.vvm vd, vs2, vs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl
+
+# vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vadc.vxm vd, vs2, rs1, v0 # Vector-scalar
+:vadc.vxm vd, vs2, rs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl
+
+# vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vadd.vi vd, vs2, simm5, vm # vector-immediate
+:vadd.vi vd, vs2, simm5, vm is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vadd.vv vd, vs2, vs1, vm # Vector-vector
+:vadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vadd.vx vd, vs2, rs1, vm # vector-scalar
+:vadd.vx vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoaddei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoaddei16.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoaddei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoaddei16.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoaddei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoaddei32.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoaddei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoaddei32.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoaddei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoaddei64.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoaddei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoaddei64.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoaddei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoaddei8.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoaddei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoaddei8.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoandei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoandei16.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoandei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoandei16.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoandei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoandei32.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoandei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoandei32.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoandei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoandei64.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoandei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoandei64.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoandei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoandei8.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoandei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoandei8.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamomaxei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxei16.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamomaxei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxei16.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamomaxei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxei32.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamomaxei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxei32.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamomaxei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxei64.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamomaxei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxei64.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamomaxei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxei8.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamomaxei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxei8.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamomaxuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamomaxuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamomaxuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamomaxuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamomaxuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamomaxuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamomaxuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamomaxuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamomaxuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamomaxuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamominei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominei16.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamominei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominei16.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamominei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominei32.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamominei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominei32.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamominei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominei64.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamominei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominei64.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamominei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominei8.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamominei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominei8.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamominuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamominuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamominuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamominuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamominuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamominuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamominuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamominuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamominuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamominuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoswapei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoswapei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoswapei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoswapei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoswapei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoswapei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoswapei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoswapei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoswapei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoswapei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoswapei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoswapei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoswapei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoswapei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoswapei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoswapei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoxorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoxorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f
+# vamoxorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoxorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoxorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoxorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f
+# vamoxorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoxorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoxorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoxorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f
+# vamoxorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoxorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl
+
+# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoxorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1
+:vamoxorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl
+
+# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f
+# vamoxorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0
+:vamoxorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl
+
+# vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vand.vi vd, vs2, simm5, vm # vector-immediate
+:vand.vi vd, vs2, simm5, vm is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vand.vv vd, vs2, vs1, vm # Vector-vector
+:vand.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vand.vx vd, vs2, rs1, vm # vector-scalar
+:vand.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1)
+:vasub.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1)
+:vasub.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1)
+:vasubu.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1)
+:vasubu.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled
+:vcompress.vm vd, vs2, vs1 is op2631=0x17 & op2525=0x1 & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vdiv.vv vd, vs2, vs1, vm # Vector-vector
+:vdiv.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vdiv.vx vd, vs2, rs1, vm # vector-scalar
+:vdiv.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vdivu.vv vd, vs2, vs1, vm # Vector-vector
+:vdivu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vdivu.vx vd, vs2, rs1, vm # vector-scalar
+:vdivu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vdot.vv vd, vs2, vs1, vm # Vector-vector
+:vdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vdotu.vv 31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vdotu.vv vd, vs2, vs1, vm # Vector-vector
+:vdotu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfadd.vf vd, vs2, rs1, vm # vector-scalar
+:vfadd.vf vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfadd.vv vd, vs2, vs1, vm # Vector-vector
+:vfadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
+# vfclass.v vd, vs2, vm # Vector-vector
+:vfclass.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57
+# vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float.
+:vfcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57
+# vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float.
+:vfcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57
+# vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating.
+:vfcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57
+# vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating.
+:vfcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57
+# vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer.
+:vfcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
+# vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer.
+:vfcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfdiv.vf vd, vs2, rs1, vm # vector-scalar
+:vfdiv.vf vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfdiv.vv vd, vs2, vs1, vm # Vector-vector
+:vfdiv.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfdot.vv vd, vs2, vs1, vm # Vector-vector
+:vfdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57
+# vfirst.m rd, vs2, vm
+:vfirst.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57 unimpl
+
+# vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i]
+:vfmacc.vf vd, rs1, vs2, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vfmacc.vv vd, vs1, vs2, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i]
+:vfmadd.vf vd, rs1, vs2, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i]
+:vfmadd.vv vd, vs1, vs2, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmax.vf vd, vs2, rs1, vm # vector-scalar
+:vfmax.vf vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmax.vv vd, vs2, vs1, vm # Vector-vector
+:vfmax.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i]
+:vfmerge.vfm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x5 & v0 & vd & op0006=0x57 unimpl
+
+# vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmin.vf vd, vs2, rs1, vm # vector-scalar
+:vfmin.vf vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmin.vv vd, vs2, vs1, vm # Vector-vector
+:vfmin.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i]
+:vfmsac.vf vd, rs1, vs2, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i]
+:vfmsac.vv vd, vs1, vs2, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i]
+:vfmsub.vf vd, rs1, vs2, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i]
+:vfmsub.vv vd, vs1, vs2, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfmul.vf vd, vs2, rs1, vm # vector-scalar
+:vfmul.vf vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfmul.vv vd, vs2, vs1, vm # Vector-vector
+:vfmul.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57
+# vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0)
+:vfmv.f.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x1 & rd & op0006=0x57 unimpl
+
+# vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57
+# vfmv.s.f vd, rs1 # vd[0] = f[rs1] (vs2=0)
+:vfmv.s.f vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57
+# vfmv.v.f vd, rs1 # vd[i] = f[rs1]
+:vfmv.v.f vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57
+# vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float.
+:vfncvt.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57
+# vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float.
+:vfncvt.f.x.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57
+# vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float.
+:vfncvt.f.xu.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57
+# vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float,
+:vfncvt.rod.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57
+# vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating.
+:vfncvt.rtz.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57
+# vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating.
+:vfncvt.rtz.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57
+# vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer.
+:vfncvt.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57
+# vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer.
+:vfncvt.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i]
+:vfnmacc.vf vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i]
+:vfnmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i]
+:vfnmadd.vf vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i]
+:vfnmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]
+:vfnmsac.vf vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
+:vfnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i]
+:vfnmsub.vf vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i]
+:vfnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i]
+:vfrdiv.vf vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfredmax.vs vd, vs2, vs1, vm # Maximum value
+:vfredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfredmin.vs vd, vs2, vs1, vm # Minimum value
+:vfredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfredosum.vs vd, vs2, vs1, vm # Ordered sum
+:vfredosum.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfredsum.vs vd, vs2, vs1, vm # Unordered sum
+:vfredsum.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i]
+:vfrsub.vf vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfsgnj.vf vd, vs2, rs1, vm # vector-scalar
+:vfsgnj.vf vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfsgnj.vv vd, vs2, vs1, vm # Vector-vector
+:vfsgnj.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar
+:vfsgnjn.vf vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector
+:vfsgnjn.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar
+:vfsgnjx.vf vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector
+:vfsgnjx.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
+:vfslide1down.vf vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i]
+:vfslide1up.vf vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57
+# vfsqrt.v vd, vs2, vm # Vector-vector square root
+:vfsqrt.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1]
+:vfsub.vf vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfsub.vv vd, vs2, vs1, vm # Vector-vector
+:vfsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwadd.vf vd, vs2, rs1, vm # vector-scalar
+:vfwadd.vf vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwadd.vv vd, vs2, vs1, vm # vector-vector
+:vfwadd.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwadd.wf vd, vs2, rs1, vm # vector-scalar
+:vfwadd.wf vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwadd.wv vd, vs2, vs1, vm # vector-vector
+:vfwadd.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57
+# vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.
+:vfwcvt.f.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57
+# vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float.
+:vfwcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57
+# vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.
+:vfwcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57
+# vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating.
+:vfwcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57
+# vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating.
+:vfwcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57
+# vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer.
+:vfwcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57
+# vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.
+:vfwcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i]
+:vfwmacc.vf vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vfwmacc.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i]
+:vfwmsac.vf vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i]
+:vfwmsac.vv vd, vs1, vs2, vm is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwmul.vf vd, vs2, rs1, vm # vector-scalar
+:vfwmul.vf vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwmul.vv vd, vs2, vs1, vm # vector-vector
+:vfwmul.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i]
+:vfwnmacc.vf vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i]
+:vfwnmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i]
+:vfwnmsac.vf vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
+:vfwnmsac.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwredosum.vs vd, vs2, vs1, vm # Ordered sum
+:vfwredosum.vs vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwredsum.vs vd, vs2, vs1, vm # Unordered sum
+:vfwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwsub.vf vd, vs2, rs1, vm # vector-scalar
+:vfwsub.vf vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwsub.vv vd, vs2, vs1, vm # vector-vector
+:vfwsub.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vfwsub.wf vd, vs2, rs1, vm # vector-scalar
+:vfwsub.wf vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vfwsub.wv vd, vs2, vs1, vm # vector-vector
+:vfwsub.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57
+# vid.v vd, vm # Write element ID to destination.
+:vid.v vd, vm is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57
+# viota.m vd, vs2, vm
+:viota.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07
+# vl1re16.v vd, (rs1)
+:vl1re16.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07
+# vl1re32.v vd, (rs1)
+:vl1re32.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07
+# vl1re64.v vd, (rs1)
+:vl1re64.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07
+# vl1re8.v vd, (rs1)
+:vl1re8.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07
+# vl2re16.v vd, (rs1)
+:vl2re16.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07
+# vl2re32.v vd, (rs1)
+:vl2re32.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07
+# vl2re64.v vd, (rs1)
+:vl2re64.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07
+# vl2re8.v vd, (rs1)
+:vl2re8.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07
+# vl4re16.v vd, (rs1)
+:vl4re16.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07
+# vl4re32.v vd, (rs1)
+:vl4re32.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07
+# vl4re64.v vd, (rs1)
+:vl4re64.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07
+# vl4re8.v vd, (rs1)
+:vl4re8.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07
+# vl8re16.v vd, (rs1)
+:vl8re16.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07
+# vl8re32.v vd, (rs1)
+:vl8re32.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07
+# vl8re64.v vd, (rs1)
+:vl8re64.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07
+# vl8re8.v vd, (rs1)
+:vl8re8.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07
+# vle1024.v vd, (rs1), vm # 1024-bit unit-stride load
+:vle1024.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07
+# vle1024ff.v vd, (rs1), vm # 1024-bit unit-stride fault-only-first load
+:vle1024ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07
+# vle128.v vd, (rs1), vm # 128-bit unit-stride load
+:vle128.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
+# vle128ff.v vd, (rs1), vm # 128-bit unit-stride fault-only-first load
+:vle128ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07
+# vle16.v vd, (rs1), vm # 16-bit unit-stride load
+:vle16.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
+# vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load
+:vle16ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07
+# vle256.v vd, (rs1), vm # 256-bit unit-stride load
+:vle256.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
+# vle256ff.v vd, (rs1), vm # 256-bit unit-stride fault-only-first load
+:vle256ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07
+# vle32.v vd, (rs1), vm # 32-bit unit-stride load
+:vle32.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07
+# vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load
+:vle32ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07
+# vle512.v vd, (rs1), vm # 512-bit unit-stride load
+:vle512.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07
+# vle512ff.v vd, (rs1), vm # 512-bit unit-stride fault-only-first load
+:vle512ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07
+# vle64.v vd, (rs1), vm # 64-bit unit-stride load
+:vle64.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07
+# vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load
+:vle64ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07
+# vle8.v vd, (rs1), vm # 8-bit unit-stride load
+:vle8.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
+# vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load
+:vle8ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07
+# vlse1024.v vd, (rs1), rs2, vm # 1024-bit strided load
+:vlse1024.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07
+# vlse128.v vd, (rs1), rs2, vm # 128-bit strided load
+:vlse128.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07
+# vlse16.v vd, (rs1), rs2, vm # 16-bit strided load
+:vlse16.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07
+# vlse256.v vd, (rs1), rs2, vm # 256-bit strided load
+:vlse256.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07
+# vlse32.v vd, (rs1), rs2, vm # 32-bit strided load
+:vlse32.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07
+# vlse512.v vd, (rs1), rs2, vm # 512-bit strided load
+:vlse512.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07
+# vlse64.v vd, (rs1), rs2, vm # 64-bit strided load
+:vlse64.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07
+# vlse8.v vd, (rs1), rs2, vm # 8-bit strided load
+:vlse8.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vlxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
+# vlxei1024.v vd, (rs1), vs2, vm # 1024-bit indexed load of SEW data
+:vlxei1024.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vlxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
+# vlxei128.v vd, (rs1), vs2, vm # 128-bit indexed load of SEW data
+:vlxei128.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vlxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
+# vlxei16.v vd, (rs1), vs2, vm # 16-bit indexed load of SEW data
+:vlxei16.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vlxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07
+# vlxei256.v vd, (rs1), vs2, vm # 256-bit indexed load of SEW data
+:vlxei256.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl
+
+# vlxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
+# vlxei32.v vd, (rs1), vs2, vm # 32-bit indexed load of SEW data
+:vlxei32.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vlxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07
+# vlxei512.v vd, (rs1), vs2, vm # 512-bit indexed load of SEW data
+:vlxei512.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl
+
+# vlxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07
+# vlxei64.v vd, (rs1), vs2, vm # 64-bit indexed load of SEW data
+:vlxei64.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl
+
+# vlxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07
+# vlxei8.v vd, (rs1), vs2, vm # 8-bit indexed load of SEW data
+:vlxei8.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl
+
+# vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+:vmacc.vx vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmadc.vim 31..26=0x11 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmadc.vim vd, vs2, simm5, v0 # Vector-immediate
+:vmadc.vim vd, vs2, simm5, v0 is op2631=0x11 & vm & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl
+
+# vmadc.vvm 31..26=0x11 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmadc.vvm vd, vs2, vs1, v0 # Vector-vector
+:vmadc.vvm vd, vs2, vs1, v0 is op2631=0x11 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl
+
+# vmadc.vxm 31..26=0x11 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar
+:vmadc.vxm vd, vs2, rs1, v0 is op2631=0x11 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl
+
+# vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i]
+:vmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i]
+:vmadd.vx vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmand.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && vs1.mask[i]
+:vmand.mm vd, vs2, vs1 is op2631=0x19 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmandnot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && !vs1.mask[i]
+:vmandnot.mm vd, vs2, vs1 is op2631=0x18 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmax.vv vd, vs2, vs1, vm # Vector-vector
+:vmax.vv vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmax.vx vd, vs2, rs1, vm # vector-scalar
+:vmax.vx vd, vs2, rs1, vm is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmaxu.vv vd, vs2, vs1, vm # Vector-vector
+:vmaxu.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmaxu.vx vd, vs2, rs1, vm # vector-scalar
+:vmaxu.vx vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmerge.vim vd, vs2, simm5, v0 # vd[i] = v0.mask[i] ? imm : vs2[i]
+:vmerge.vim vd, vs2, simm5, v0 is op2631=0x17 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl
+
+# vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i]
+:vmerge.vvm vd, vs2, vs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl
+
+# vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i]
+:vmerge.vxm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl
+
+# vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmfeq.vf vd, vs2, rs1, vm # vector-scalar
+:vmfeq.vf vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vmfeq.vv vd, vs2, vs1, vm # Vector-vector
+:vmfeq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmfge.vf vd, vs2, rs1, vm # vector-scalar
+:vmfge.vf vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmfgt.vf vd, vs2, rs1, vm # vector-scalar
+:vmfgt.vf vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmfle.vf vd, vs2, rs1, vm # vector-scalar
+:vmfle.vf vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vmfle.vv vd, vs2, vs1, vm # Vector-vector
+:vmfle.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmflt.vf vd, vs2, rs1, vm # vector-scalar
+:vmflt.vf vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vmflt.vv vd, vs2, vs1, vm # Vector-vector
+:vmflt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57
+# vmfne.vf vd, vs2, rs1, vm # vector-scalar
+:vmfne.vf vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl
+
+# vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57
+# vmfne.vv vd, vs2, vs1, vm # Vector-vector
+:vmfne.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl
+
+# vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmin.vv vd, vs2, vs1, vm # Vector-vector
+:vmin.vv vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmin.vx vd, vs2, rs1, vm # vector-scalar
+:vmin.vx vd, vs2, rs1, vm is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vminu.vv vd, vs2, vs1, vm # Vector-vector
+:vminu.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vminu.vx vd, vs2, rs1, vm # vector-scalar
+:vminu.vx vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmnand.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] && vs1.mask[i])
+:vmnand.mm vd, vs2, vs1 is op2631=0x1d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] || vs1.mask[i])
+:vmnor.mm vd, vs2, vs1 is op2631=0x1e & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || vs1.mask[i]
+:vmor.mm vd, vs2, vs1 is op2631=0x1a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmornot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || !vs1.mask[i]
+:vmornot.mm vd, vs2, vs1 is op2631=0x1c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmsbc.vvm 31..26=0x13 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector
+:vmsbc.vvm vd, vs2, vs1, v0 is op2631=0x13 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl
+
+# vmsbc.vxm 31..26=0x13 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar
+:vmsbc.vxm vd, vs2, rs1, v0 is op2631=0x13 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl
+
+# vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57
+# vmsbf.m vd, vs2, vm
+:vmsbf.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmseq.vi vd, vs2, simm5, vm # vector-immediate
+:vmseq.vi vd, vs2, simm5, vm is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmseq.vv vd, vs2, vs1, vm # Vector-vector
+:vmseq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmseq.vx vd, vs2, rs1, vm # vector-scalar
+:vmseq.vx vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmsgt.vi vd, vs2, simm5, vm # Vector-immediate
+:vmsgt.vi vd, vs2, simm5, vm is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsgt.vx vd, vs2, rs1, vm # Vector-scalar
+:vmsgt.vx vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmsgtu.vi vd, vs2, simm5, vm # Vector-immediate
+:vmsgtu.vi vd, vs2, simm5, vm is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar
+:vmsgtu.vx vd, vs2, rs1, vm is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57
+# vmsif.m vd, vs2, vm
+:vmsif.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmsle.vi vd, vs2, simm5, vm # vector-immediate
+:vmsle.vi vd, vs2, simm5, vm is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmsle.vv vd, vs2, vs1, vm # Vector-vector
+:vmsle.vv vd, vs2, vs1, vm is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsle.vx vd, vs2, rs1, vm # vector-scalar
+:vmsle.vx vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmsleu.vi vd, vs2, simm5, vm # Vector-immediate
+:vmsleu.vi vd, vs2, simm5, vm is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmsleu.vv vd, vs2, vs1, vm # Vector-vector
+:vmsleu.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsleu.vx vd, vs2, rs1, vm # vector-scalar
+:vmsleu.vx vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmslt.vv vd, vs2, vs1, vm # Vector-vector
+:vmslt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmslt.vx vd, vs2, rs1, vm # vector-scalar
+:vmslt.vx vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmsltu.vv vd, vs2, vs1, vm # Vector-vector
+:vmsltu.vv vd, vs2, vs1, vm is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsltu.vx vd, vs2, rs1, vm # Vector-scalar
+:vmsltu.vx vd, vs2, rs1, vm is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vmsne.vi vd, vs2, simm5, vm # vector-immediate
+:vmsne.vi vd, vs2, simm5, vm is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vmsne.vv vd, vs2, vs1, vm # Vector-vector
+:vmsne.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vmsne.vx vd, vs2, rs1, vm # vector-scalar
+:vmsne.vx vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57
+# vmsof.m vd, vs2, vm
+:vmsof.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmul.vv vd, vs2, vs1, vm # Vector-vector
+:vmul.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmul.vx vd, vs2, rs1, vm # vector-scalar
+:vmul.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmulh.vv vd, vs2, vs1, vm # Vector-vector
+:vmulh.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmulh.vx vd, vs2, rs1, vm # vector-scalar
+:vmulh.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmulhsu.vv vd, vs2, vs1, vm # Vector-vector
+:vmulhsu.vv vd, vs2, vs1, vm is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmulhsu.vx vd, vs2, rs1, vm # vector-scalar
+:vmulhsu.vx vd, vs2, rs1, vm is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmulhu.vv vd, vs2, vs1, vm # Vector-vector
+:vmulhu.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vmulhu.vx vd, vs2, rs1, vm # vector-scalar
+:vmulhu.vx vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57
+# vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0)
+:vmv.s.x vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57
+# vmv.v.i vd, simm5 # vd[i] = imm
+:vmv.v.i vd, simm5 is op2631=0x17 & op2525=0x1 & op2024=0x0 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57
+# vmv.v.v vd, vs1 # vd[i] = vs1[i]
+:vmv.v.v vd, vs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57
+# vmv.v.x vd, rs1 # vd[i] = rs1
+:vmv.v.x vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 vd 6..0=0x57
+# vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0)
+:vmv.x.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x2 & rd & vd & op0006=0x57 unimpl
+
+# vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57
+# vmv1r.v vd, vs2
+:vmv1r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57
+# vmv2r.v vd, vs2
+:vmv2r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x1 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57
+# vmv4r.v vd, vs2
+:vmv4r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x3 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57
+# vmv8r.v vd, vs2
+:vmv8r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x7 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmxnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] ^^ vs1.mask[i])
+:vmxnor.mm vd, vs2, vs1 is op2631=0x1f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vmxor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] ^^ vs1.mask[i]
+:vmxor.mm vd, vs2, vs1 is op2631=0x1b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vnclip.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5))
+:vnclip.wi vd, vs2, simm5, vm is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i]))
+:vnclip.wv vd, vs2, vs1, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1]))
+:vnclip.wx vd, vs2, rs1, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vnclipu.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5))
+:vnclipu.wi vd, vs2, simm5, vm is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i]))
+:vnclipu.wv vd, vs2, vs1, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1]))
+:vnclipu.wx vd, vs2, rs1, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i]
+:vnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i]
+:vnmsac.vx vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i]
+:vnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i]
+:vnmsub.vx vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vnsra.wi vd, vs2, simm5, vm # vector-immediate
+:vnsra.wi vd, vs2, simm5, vm is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vnsra.wv vd, vs2, vs1, vm # vector-vector
+:vnsra.wv vd, vs2, vs1, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vnsra.wx vd, vs2, rs1, vm # vector-scalar
+:vnsra.wx vd, vs2, rs1, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vnsrl.wi vd, vs2, simm5, vm # vector-immediate
+:vnsrl.wi vd, vs2, simm5, vm is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vnsrl.wv vd, vs2, vs1, vm # vector-vector
+:vnsrl.wv vd, vs2, vs1, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vnsrl.wx vd, vs2, rs1, vm # vector-scalar
+:vnsrl.wx vd, vs2, rs1, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vor.vi vd, vs2, simm5, vm # vector-immediate
+:vor.vi vd, vs2, simm5, vm is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vor.vv vd, vs2, vs1, vm # Vector-vector
+:vor.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vor.vx vd, vs2, rs1, vm # vector-scalar
+:vor.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57
+# vpopc.m rd, vs2, vm # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )
+:vpopc.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57 unimpl
+
+# vqmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vqmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vqmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+:vqmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vqmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]
+:vqmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vqmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]
+:vqmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vqmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vqmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vqmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+:vqmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vqmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
+:vqmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] )
+:vredand.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] )
+:vredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] )
+:vredmaxu.vs vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] )
+:vredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] )
+:vredminu.vs vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] )
+:vredor.vs vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] )
+:vredsum.vs vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] )
+:vredxor.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vrem.vv vd, vs2, vs1, vm # Vector-vector
+:vrem.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vrem.vx vd, vs2, rs1, vm # vector-scalar
+:vrem.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vremu.vv vd, vs2, vs1, vm # Vector-vector
+:vremu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vremu.vx vd, vs2, rs1, vm # vector-scalar
+:vremu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vrgather.vi vd, vs2, simm5, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm]
+:vrgather.vi vd, vs2, simm5, vm is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
+:vrgather.vv vd, vs2, vs1, vm is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]]
+:vrgather.vx vd, vs2, rs1, vm is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
+:vrgatherei16.vv vd, vs2, vs1, vm is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vrsub.vi vd, vs2, simm5, vm # vd[i] = imm - vs2[i]
+:vrsub.vi vd, vs2, simm5, vm is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i]
+:vrsub.vx vd, vs2, rs1, vm is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
+# vs1r.v vs3, (rs1)
+:vs1r.v vs3, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
+# vs2r.v vs3, (rs1)
+:vs2r.v vs3, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
+# vs4r.v vs3, (rs1)
+:vs4r.v vs3, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27
+# vs8r.v vs3, (rs1)
+:vs8r.v vs3, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vsadd.vi vd, vs2, simm5, vm # vector-immediate
+:vsadd.vi vd, vs2, simm5, vm is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsadd.vv vd, vs2, vs1, vm # Vector-vector
+:vsadd.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsadd.vx vd, vs2, rs1, vm # vector-scalar
+:vsadd.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vsaddu.vi vd, vs2, simm5, vm # vector-immediate
+:vsaddu.vi vd, vs2, simm5, vm is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsaddu.vv vd, vs2, vs1, vm # Vector-vector
+:vsaddu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsaddu.vx vd, vs2, rs1, vm # vector-scalar
+:vsaddu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsbc.vvm vd, vs2, vs1, v0 # Vector-vector
+:vsbc.vvm vd, vs2, vs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl
+
+# vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar
+:vsbc.vxm vd, vs2, rs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl
+
+# vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
+# vse1024.v vs3, (rs1), vm # 1024-bit unit-stride store
+:vse1024.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
+# vse128.v vs3, (rs1), vm # 128-bit unit-stride store
+:vse128.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
+# vse16.v vs3, (rs1), vm # 16-bit unit-stride store
+:vse16.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27
+# vse256.v vs3, (rs1), vm # 256-bit unit-stride store
+:vse256.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
+# vse32.v vs3, (rs1), vm # 32-bit unit-stride store
+:vse32.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27
+# vse512.v vs3, (rs1), vm # 512-bit unit-stride store
+:vse512.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27
+# vse64.v vs3, (rs1), vm # 64-bit unit-stride store
+:vse64.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27
+# vse8.v vs3, (rs1), vm # 8-bit unit-stride store
+:vse8.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57
+# vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value
+:vsetvl rd, rs1, rs2 is op3131=0x1 & op2530=0x0 & rs2 & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl
+
+#TODO huh
+# vsetvli 31=0 vtypei rs1 14..12=0x7 rd 6..0=0x57
+# vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting
+:vsetvli rd, rs1, vtypei is op3131=0x0 & vtypei & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl
+
+# vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57
+# vsext.vf2 vd, vs2, vm # Sign-extend SEW/2 source to SEW destination
+:vsext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57
+# vsext.vf4 vd, vs2, vm # Sign-extend SEW/4 source to SEW destination
+:vsext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57
+# vsext.vf8 vd, vs2, vm # Sign-extend SEW/8 source to SEW destination
+:vsext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
+:vslide1down.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i]
+:vslide1up.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vslidedown.vi vd, vs2, simm5[4:0], vm # vd[i] = vs2[i+uimm]
+:vslidedown.vi vd, vs2, simm5[4:0], vm is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1]
+:vslidedown.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vslideup.vi vd, vs2, simm5[4:0], vm # vd[i+uimm] = vs2[i]
+:vslideup.vi vd, vs2, simm5[4:0], vm is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i]
+:vslideup.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vsll.vi vd, vs2, simm5, vm # vector-immediate
+:vsll.vi vd, vs2, simm5, vm is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsll.vv vd, vs2, vs1, vm # Vector-vector
+:vsll.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsll.vx vd, vs2, rs1, vm # vector-scalar
+:vsll.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1))
+:vsmul.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))
+:vsmul.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#OTOD this is broken
+# vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vsra.vi vd, vs2, simm5, vm # vector-immediate
+:vsra.vi vd, vs2, simm5, vm is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsra.vv vd, vs2, vs1, vm # Vector-vector
+:vsra.vv vd, vs2, vs1, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsra.vx vd, vs2, rs1, vm # vector-scalar
+:vsra.vx vd, vs2, rs1, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vsrl.vi vd, vs2, simm5, vm # vector-immediate
+:vsrl.vi vd, vs2, simm5, vm is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsrl.vv vd, vs2, vs1, vm # Vector-vector
+:vsrl.vv vd, vs2, vs1, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsrl.vx vd, vs2, rs1, vm # vector-scalar
+:vsrl.vx vd, vs2, rs1, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsse1024.v vs3, (rs1), rs2, vm # 1024-bit strided store
+:vsse1024.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsse128.v vs3, (rs1), rs2, vm # 128-bit strided store
+:vsse128.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store
+:vsse16.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsse256.v vs3, (rs1), rs2, vm # 256-bit strided store
+:vsse256.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store
+:vsse32.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsse512.v vs3, (rs1), rs2, vm # 512-bit strided store
+:vsse512.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store
+:vsse64.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store
+:vsse8.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+#TODO this is broken
+# vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vssra.vi vd, vs2, simm5, vm # vd[i] = roundoff_signed(vs2[i], uimm)
+:vssra.vi vd, vs2, simm5, vm is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i])
+:vssra.vv vd, vs2, vs1, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1])
+:vssra.vx vd, vs2, rs1, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+#TODO this is broken
+# vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vssrl.vi vd, vs2, simm5, vm # vd[i] = roundoff_unsigned(vs2[i], uimm)
+:vssrl.vi vd, vs2, simm5, vm is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i])
+:vssrl.vv vd, vs2, vs1, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1])
+:vssrl.vx vd, vs2, rs1, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vssub.vv vd, vs2, vs1, vm # Vector-vector
+:vssub.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vssub.vx vd, vs2, rs1, vm # vector-scalar
+:vssub.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vssubu.vv vd, vs2, vs1, vm # Vector-vector
+:vssubu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vssubu.vx vd, vs2, rs1, vm # vector-scalar
+:vssubu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vsub.vv vd, vs2, vs1, vm # Vector-vector
+:vsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vsub.vx vd, vs2, rs1, vm # vector-scalar
+:vsub.vx vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsuxei1024.v vs3, (rs1), vs2, vm # unordered 1024-bit indexed store of SEW data
+:vsuxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsuxei128.v vs3, (rs1), vs2, vm # unordered 128-bit indexed store of SEW data
+:vsuxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data
+:vsuxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsuxei256.v vs3, (rs1), vs2, vm # unordered 256-bit indexed store of SEW data
+:vsuxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data
+:vsuxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsuxei512.v vs3, (rs1), vs2, vm # unordered 512-bit indexed store of SEW data
+:vsuxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data
+:vsuxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data
+:vsuxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsxei1024.v vs3, (rs1), vs2, vm # ordered 1024-bit indexed store of SEW data
+:vsxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsxei128.v vs3, (rs1), vs2, vm # ordered 128-bit indexed store of SEW data
+:vsxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vsxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data
+:vsxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
+# vsxei256.v vs3, (rs1), vs2, vm # ordered 256-bit indexed store of SEW data
+:vsxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl
+
+# vsxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data
+:vsxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
+# vsxei512.v vs3, (rs1), vs2, vm # ordered 512-bit indexed store of SEW data
+:vsxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl
+
+# vsxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27
+# vsxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data
+:vsxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl
+
+# vsxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27
+# vsxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data
+:vsxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl
+
+# vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwadd.vv vd, vs2, vs1, vm # vector-vector
+:vwadd.vv vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwadd.vx vd, vs2, rs1, vm # vector-scalar
+:vwadd.vx vd, vs2, rs1, vm is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwadd.wv vd, vs2, vs1, vm # vector-vector
+:vwadd.wv vd, vs2, vs1, vm is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwadd.wx vd, vs2, rs1, vm # vector-scalar
+:vwadd.wx vd, vs2, rs1, vm is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwaddu.vv vd, vs2, vs1, vm # vector-vector
+:vwaddu.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwaddu.vx vd, vs2, rs1, vm # vector-scalar
+:vwaddu.vx vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwaddu.wv vd, vs2, vs1, vm # vector-vector
+:vwaddu.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwaddu.wx vd, vs2, rs1, vm # vector-scalar
+:vwaddu.wx vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vwmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+:vwmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i]
+:vwmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i]
+:vwmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+:vwmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+:vwmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]
+:vwmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmul.vv vd, vs2, vs1, vm# vector-vector
+:vwmul.vv vd, vs2, vs1, vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmul.vx vd, vs2, rs1, vm # vector-scalar
+:vwmul.vx vd, vs2, rs1, vm is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmulsu.vv vd, vs2, vs1, vm # vector-vector
+:vwmulsu.vv vd, vs2, vs1, vm is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmulsu.vx vd, vs2, rs1, vm # vector-scalar
+:vwmulsu.vx vd, vs2, rs1, vm is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwmulu.vv vd, vs2, vs1, vm # vector-vector
+:vwmulu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwmulu.vx vd, vs2, rs1, vm # vector-scalar
+:vwmulu.vx vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW))
+:vwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW))
+:vwredsumu.vs vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwsub.vv vd, vs2, vs1, vm # vector-vector
+:vwsub.vv vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwsub.vx vd, vs2, rs1, vm # vector-scalar
+:vwsub.vx vd, vs2, rs1, vm is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwsub.wv vd, vs2, vs1, vm # vector-vector
+:vwsub.wv vd, vs2, vs1, vm is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwsub.wx vd, vs2, rs1, vm # vector-scalar
+:vwsub.wx vd, vs2, rs1, vm is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwsubu.vv vd, vs2, vs1, vm # vector-vector
+:vwsubu.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwsubu.vx vd, vs2, rs1, vm # vector-scalar
+:vwsubu.vx vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57
+# vwsubu.wv vd, vs2, vs1, vm # vector-vector
+:vwsubu.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57
+# vwsubu.wx vd, vs2, rs1, vm # vector-scalar
+:vwsubu.wx vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl
+
+# vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57
+# vxor.vi vd, vs2, simm5, vm # vector-immediate
+:vxor.vi vd, vs2, simm5, vm is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl
+
+# vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57
+# vxor.vv vd, vs2, vs1, vm # Vector-vector
+:vxor.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl
+
+# vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57
+# vxor.vx vd, vs2, rs1, vm # vector-scalar
+:vxor.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl
+
+# vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57
+# vzext.vf2 vd, vs2, vm # Zero-extend SEW/2 source to SEW destination
+:vzext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57
+# vzext.vf4 vd, vs2, vm # Zero-extend SEW/4 source to SEW destination
+:vzext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57 unimpl
+
+# vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57
+# vzext.vf8 vd, vs2, vm # Zero-extend SEW/8 source to SEW destination
+:vzext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
index e512b793ea..089a1b2ace 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
@@ -12,48 +12,43 @@
@define QXLEN 16
+define pcodeop unimp;
define pcodeop trap;
+define pcodeop ebreak;
+define pcodeop ecall;
+define pcodeop fence;
+define pcodeop fence.i;
# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711
-rs1: r1519 is r1519 { export r1519; }
-rs1: zero is r1519 & zero & op1519=0 { export 0:$(XLEN); }
+rs1: r1519 is r1519 { export r1519; }
+rs1: zero is zero & op1519=0 { export 0:$(XLEN); }
rs2: r2024 is r2024 { export r2024; }
-rs2: zero is r2024 & zero & op2024=0 { export 0:$(XLEN); }
+rs2: zero is zero & op2024=0 { export 0:$(XLEN); }
+
+rs3: r2731 is r2731 { export r2731; }
+rs3: zero is zero & op2731=0 { export 0:$(XLEN); }
rd: r0711 is r0711 { export r0711; }
rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); }
-@if ADDRSIZE == "32"
-rs1W: r1519 is RV32 & r1519 { export r1519; }
-rs1W: zero is RV32 & r1519 & zero & op1519=0 { export 0:$(XLEN); }
+rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; }
+rs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); }
-rs2W: r2024 is RV32 & r2024 { export r2024; }
-rs2W: zero is RV32 & r2024 & zero & op2024=0 { export 0:$(XLEN); }
+rs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; }
+rs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); }
#TODO dest may be bad, might need an assign macro
-rdW: r0711 is RV32 & r0711 { export r0711; }
-rdW: zero is RV32 & r0711 & zero & op0711=0 { export 0:$(XLEN); }
+rdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; }
+rdW: zero is r0711 & zero & op0711=0 { export 0:$(WXLEN); }
-@else
-rs1W: r1519 is r1519 { local tmp:4 = r1519:4; export tmp; }
-rs1W: zero is r1519 & zero & op1519=0 { export 0:4; }
-
-rs2W: r2024 is r2024 { local tmp:4 = r2024:4; export tmp; }
-rs2W: zero is r2024 & zero & op2024=0 { export 0:4; }
-
-#TODO dest may be bad, might need an assign macro
-rdW: r0711 is r0711 { export r0711; }
-rdW: zero is r0711 & zero & op0711=0 { export 0:8; }
-
-@endif
#TODO does this need to be in an if/endif
@if ADDRSIZE == "64"
-rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; }
+rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; }
rs1L: zero is r1519 & zero & op1519=0 { export 0:8; }
rs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; }
@@ -79,8 +74,8 @@ rdL: zero is r0711 & zero & op0711=0 { export 0:8; }
# # 128-bit quad-precision $(QFLEN)
# fmt: ".q" is op2526=3 { export $(QFLEN):1; }
-@if FPSIZE != ""
+@if FPSIZE != "0"
frd: fr0711 is fr0711 { export fr0711; }
frs1: fr1519 is fr1519 { export fr1519; }
frs2: fr2024 is fr2024 { export fr2024; }
@@ -92,13 +87,13 @@ frs1S: fr1519 is fr1519 { local tmp = fr1519:$(SFLEN); export tmp; }
frs2S: fr2024 is fr2024 { local tmp = fr2024:$(SFLEN); export tmp; }
frs3S: fr2731 is fr2731 { local tmp = fr2731:$(SFLEN); export tmp; }
-
+@if ((FPSIZE == "64") || (FPSIZE == "128"))
#TODO dest may be bad, might need an assign macro
#frdD: fr0711 is fr0711 { local tmp = fr0711:$(DFLEN); export tmp; }
frs1D: fr1519 is fr1519 { local tmp = fr1519:$(DFLEN); export tmp; }
frs2D: fr2024 is fr2024 { local tmp = fr2024:$(DFLEN); export tmp; }
frs3D: fr2731 is fr2731 { local tmp = fr2731:$(DFLEN); export tmp; }
-
+@endif
macro fassignS(dest, src) {
@if FPSIZE == "32"
@@ -107,9 +102,9 @@ macro fassignS(dest, src) {
dest = zext(src);
@endif
}
-
@endif
+
macro assignW(dest, src) {
@if ADDRSIZE == "32"
dest = src;
@@ -127,13 +122,20 @@ macro zassignW(dest, src) {
}
macro zassignD(dest, src) {
-@if ADDRSIZE == "64"
- dest = src;
-@else
+@if ADDRSIZE == "128"
dest = zext(src);
+@else
+ dest = src;
@endif
}
+macro assignD(dest, src) {
+@if ADDRSIZE == "128"
+ dest = sext(src);
+@else
+ dest = src;
+@endif
+}
immI: sop2031 is sop2031 { local tmp:$(XLEN) = sop2031; export tmp; }
@@ -144,18 +146,17 @@ immS: imm is op0711 & sop2531 [ imm = (sop2531 << 5) | op0711; ] { local tmp:$(X
immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export *[ram]:$(XLEN) reloc; }
#immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export reloc; }
-#NOTES this reads as '<< 12' but objdump does not
-# immU: imm is sop1231 [ imm = (sop1231 << 12); ] { local tmp:$(XLEN) = imm; export tmp; }
-immU: sop1231 is sop1231 { local tmp:$(XLEN) = sop1231; export tmp; }
+immU: op1231 is op1231 & sop1231 { local tmp:$(XLEN) = sop1231 << 12; export tmp; }
# used for goto
immUJ: reloc is op1219 & op2020 & op2130 & sop3131 [ reloc = inst_start + ((sop3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12)); ] { export *[ram]:$(XLEN) reloc; }
-@if ADDRSIZE == "64"
+@if ADDRSIZE == "32"
+shamt6: op2024 is op2024 & op2525=0 { local tmp:$(XLEN) = op2024; export tmp; }
+@else
shamt5: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; }
-@endif
-
shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:$(XLEN) = imm; export tmp; }
+@endif
FRM: "rne" is op1214=0 { local tmp:1 = 0; export tmp; }
FRM: "rtz" is op1214=1 { local tmp:1 = 1; export tmp; }
@@ -166,10 +167,11 @@ FRM: "rmm" is op1214=4 { local tmp:1 = 4; export tmp; }
# 6 Invalid. Reserved for future use
FRM: "dyn" is op1214=7 { local tmp:1 = 7; export tmp; }
-aqrl: "" is op2526=0 {}
-aqrl: ".rl" is op2526=1 {}
-aqrl: ".aq" is op2526=2 {}
-aqrl: ".aqrl" is op2526=3 {}
+# used to specify additional memory ordering constraints
+aqrl: "" is op2526=0 { export 0:$(XLEN); }
+aqrl: ".rl" is op2526=1 { export 1:$(XLEN); }
+aqrl: ".aq" is op2526=2 { export 2:$(XLEN); }
+aqrl: ".aqrl" is op2526=3 { export 3:$(XLEN); }
@@ -177,12 +179,12 @@ crs1: cr0711 is cr0711 { export cr0711; }
crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); }
crd: cd0711 is cd0711 { export cd0711; }
-crd: zero is cd0711 & zero & cop0711=0 { export 0:$(XLEN); }
+crd: zero is zero & cop0711=0 { export 0:$(XLEN); }
crs2: cr0206 is cr0206 { export cr0206; }
crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); }
-@if FPSIZE != ""
+@if FPSIZE != "0"
cfrs1: cfr0711 is cfr0711 { export cfr0711; }
cfrd: cfr0711 is cfr0711 { export cfr0711; }
@@ -214,146 +216,168 @@ c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local
c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm + (64 * (uimm == 0)); export tmp; }
@endif
-#NOTES not shifted
-# cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 17) | (cop0206 << 12); ] { local tmp:$(XLEN) = imm; export tmp; }
-cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; }
+cbigimm: uimm is cop1212 & scop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = (scop1212 << 17) | (cop0206 << 12); export tmp; }
caddi4spnimm: uimm is cop1112 & cop0710 & cop0606 & cop0505 [ uimm = (cop0710 << 6) | (cop1112 << 4) | (cop0505 << 3) | (cop0606 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }
caddi16spimm: imm is scop1212 & cop0606 & cop0505 & cop0304 & cop0202 [ imm = (scop1212 << 9) | (cop0304 << 7) | (cop0505 << 6) | (cop0202 << 5) | (cop0606 << 4); ] { local tmp:$(XLEN) = imm; export tmp; }
-cldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
-
clwimm: uimm is cop1012 & cop0606 & cop0505 [ uimm = (cop1012 << 3) | (cop0606 << 2) | (cop0505 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
-clqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
+clwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
+
+cswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }
+
+cldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
cldspimm: uimm is cop1212 & cop0506 & cop0204 [ uimm = (cop1212 << 5) | (cop0506 << 3) | (cop0204 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
-@if ADDRSIZE == "64"
-clqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
-@endif
-
-clwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
-
csdspimm: uimm is cop0709 & cop1012 [ uimm = (cop0709 << 6) | (cop1012 << 3); ] { local tmp:$(XLEN) = uimm; export tmp; }
@if ADDRSIZE == "128"
+clqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
+
+clqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; }
+
csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; }
@endif
-cswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; }
-#TODO this is broken
-#TODO maybe 2 tables are needed for address and size
-# instead of register name
-# CSR have different access level, use, and accessibility
-# just formatting this way for readability. Breaking up
-# csr into multiples to avoid having an 'attach variables'
-# with 0x1000 fields
+
# SEE riscv-privileged.pdf Section 'CSR Listing' for description
+# This implementation aligns with the table breakdown
+
+# csr[11:10] - read/write (00, 01, 10) or read-only (11)
+# csr[9:8] - lowest privilege that can access the CSR
# 0x000-0x0ff
with csr: op3031=0 & op2829=0 {
- : csr_0 is csr_0 {}
+ : csr_0 is csr_0 { export csr_0; } # user, standard read/write
}
# 0x100-0x1ff
with csr: op3031=0 & op2829=1 {
- : csr_1 is csr_1 {}
+ : csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write
}
# 0x200-0x2ff
with csr: op3031=0 & op2829=2 {
- : csr_2 is csr_2 {}
+ : csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write
}
# 0x300-0x3ff
with csr: op3031=0 & op2829=3 {
- : csr_3 is csr_3 {}
+ : csr_3 is csr_3 { export csr_3; } # machine, standard read/write
}
# 0x400-0x4ff
with csr: op3031=1 & op2829=0 {
- : csr_4 is csr_4 {}
+ : csr_4 is csr_4 { export csr_4; } # user, standard read/write
}
# 0x500-0x5ff
with csr: op3031=1 & op2829=1 {
- : csr_50 is csr_50 & op2727=0 {}
- : csr_58 is csr_58 & op2627=2 {}
- : csr_5C is csr_5C & op2627=3 {}
+ : csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write
+ : csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write
+ : csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write
}
# 0x600-0x6ff
with csr: op3031=1 & op2829=2 {
- : csr_60 is csr_60 & op2727=0 {}
- : csr_68 is csr_68 & op2627=2 {}
- : csr_6C is csr_6C & op2627=3 {}
+ : csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write
+ : csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write
+ : csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write
}
# 0x700-0x7ff
with csr: op3031=1 & op2829=3 {
- : csr_70 is csr_70 & op2727=0 {}
- : csr_78 is csr_78 & op2527=4 {}
- : csr_7A is csr_7A & op2427=0xa {}
- : csr_7B is csr_7B & op2427=0xb {}
- : csr_7C is csr_7C & op2627=3 {}
+ : csr_70 is csr_70 & op2727=0 { export csr_70; } # machine, standard read/write
+ : csr_78 is csr_78 & op2527=4 { export csr_78; } # machine, standard read/write
+ : csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug
+ : csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only
+ : csr_7C is csr_7C & op2627=3 { export csr_7C; } # machine, custom read/write
}
# 0x800-0x8ff
with csr: op3031=2 & op2829=0 {
- : csr_8 is csr_8 {}
+ : csr_8 is csr_8 { export csr_8; } # user, custom read/write
}
# 0x900-0x9ff
with csr: op3031=2 & op2829=1 {
- : csr_90 is csr_90 & op2727=0 {}
- : csr_98 is csr_98 & op2627=2 {}
- : csr_9C is csr_9C & op2627=3 {}
+ : csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write
+ : csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write
+ : csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write
}
# 0xa00-0xaff
with csr: op3031=2 & op2829=2 {
- : csr_A0 is csr_A0 & op2727=0 {}
- : csr_A8 is csr_A8 & op2627=2 {}
- : csr_AC is csr_AC & op2627=3 {}
+ : csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write
+ : csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write
+ : csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write
}
# 0xb00-0xbff
with csr: op3031=2 & op2829=3 {
- : csr_B0 is csr_B0 & op2727=0 {}
- : csr_B8 is csr_B8 & op2627=2 {}
- : csr_BC is csr_BC & op2627=3 {}
+ : csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write
+ : csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write
+ : csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write
}
# 0xc00-0xcff
with csr: op3031=3 & op2829=0 {
- : csr_C0 is csr_C0 & op2727=0 {}
- : csr_C8 is csr_C8 & op2627=2 {}
- : csr_CC is csr_CC & op2627=3 {}
+ : csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only
+ : csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only
+ : csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only
}
# 0xd00-0xdff
with csr: op3031=3 & op2829=1 {
- : csr_D0 is csr_D0 & op2727=0 {}
- : csr_D8 is csr_D8 & op2627=2 {}
- : csr_DC is csr_DC & op2627=3 {}
+ : csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only
+ : csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only
+ : csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only
}
# 0xe00-0xeff
with csr: op3031=3 & op2829=2 {
- : csr_E0 is csr_E0 & op2727=0 {}
- : csr_E8 is csr_E8 & op2627=2 {}
- : csr_EC is csr_EC & op2627=3 {}
+ : csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only
+ : csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only
+ : csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only
}
# 0xf00-0xfff
with csr: op3031=3 & op2829=3 {
- : csr_F0 is csr_F0 & op2727=0 {}
- : csr_F8 is csr_F8 & op2627=2 {}
- : csr_FC is csr_FC & op2627=3 {}
+ : csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only
+ : csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only
+ : csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only
}
+
+
+
+vm: op2525 is op2525 { local tmp:1 = op2525; export tmp; }
+
+vs1: v1519 is v1519 { export v1519; }
+vs2: v2024 is v2024 { export v2024; }
+vs3: v0711 is v0711 { export v0711; }
+vd: v0711 is v0711 { export v0711; }
+
+simm5: sop1519 is sop1519 { local tmp:$(XLEN) = sop1519; export tmp; }
+# zimm: op1519 is op1519 { local tmp:$(XLEN) = op1519; export tmp; }
+
+nf: op2931 is op2931 { local tmp:$(XLEN) = op2931; export tmp; }
+
+vtypei: op2030 is op2030 { local tmp:$(XLEN) = op2030; export tmp; }
+
+
+bs: op3031 is op3031 { local tmp:$(XLEN) = op3031; export tmp; }
+rcon: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; }
+
+# imm=0 for baseline operation, nonzero values are reserved
+shamtw: 0 is op2024=0 { local tmp:$(XLEN) = 0; export tmp; }
+
+imm3u: op2022 is op2022 { local tmp:$(XLEN) = op2022; export tmp; }
+imm4u: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; }
+imm5u: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; }
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc
index 92ea0d6765..54ff05b778 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc
@@ -3,4 +3,5 @@
# fence.i 0000100f ffffffff SIMPLE (0, 0)
:fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0
{
+ fence.i();
}
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf
deleted file mode 100644
index f136b11870..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf
index 31074ccdd8..f136b11870 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf
+++ b/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf
@@ -11,6 +11,12 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf
deleted file mode 100644
index ee3e8fa4bf..0000000000
--- a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf
index b147720559..ee3e8fa4bf 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf
+++ b/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf
@@ -11,6 +11,12 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Ghidra/Processors/RISCV/data/patterns/riscv_gc_patterns.xml b/Ghidra/Processors/RISCV/data/patterns/riscv_gc_patterns.xml
index 3f0fa6558a..14ecd69948 100644
--- a/Ghidra/Processors/RISCV/data/patterns/riscv_gc_patterns.xml
+++ b/Ghidra/Processors/RISCV/data/patterns/riscv_gc_patterns.xml
@@ -1,16 +1,49 @@
-
+
-
10000010 10000000
- 01101111 ....0000 ........ ........
......01 101.....
0.....01 01110001
0.....01 00010001
+
+
+
+
+
+
+ 10000010 10000000
+ ......01 101.....
+
+
+
+ 00010011 00000001 ....0001 1.......
+ .0010111 ........ ........ ........
+
+
+
+
+
+
+ 01101111 ....0000 ........ ........
+
+
+
+ 0.....01 01110001
+ 0.....01 00010001
+
+
+
+
+
+
+ 01101111 ....0000 ........ ........
+
+
+
00010011 00000001 ....0001 1.......
.0010111 ........ ........ ........