From ca9f57af477d87271e286e3b3602bcd7a5be7171 Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Mon, 24 Jan 2022 19:26:43 +0000 Subject: [PATCH] GP-1965_emteere Moving 6805 to MC6800 and refactoring to better allow extensions. Also adding H6309 processor --- .../{6805 => MC6800}/Module.manifest | 0 .../Processors/{6805 => MC6800}/build.gradle | 0 .../{6805 => MC6800}/certification.manifest | 2 + .../data/languages/6800.ldefs} | 36 ++-- .../data/languages/6805.cspec | 0 .../MC6800/data/languages/6805.ldefs | 15 ++ .../data/languages/6805.pspec | 0 .../data/languages/6805.slaspec | 0 .../data/languages/6809.cspec | 0 .../data/languages/6809.pspec | 0 .../data/languages/6809.slaspec | 0 .../{6805 => MC6800}/data/languages/6x09.sinc | 157 +++++++++++++++--- .../data/languages/6x09_exg_tfr.sinc | 0 .../data/languages/6x09_pull.sinc | 0 .../data/languages/6x09_push.sinc | 0 .../MC6800/data/languages/H6309.slaspec | 10 ++ .../{6805 => MC6800}/data/manuals/6809.idx | 0 17 files changed, 177 insertions(+), 43 deletions(-) rename Ghidra/Processors/{6805 => MC6800}/Module.manifest (100%) rename Ghidra/Processors/{6805 => MC6800}/build.gradle (100%) rename Ghidra/Processors/{6805 => MC6800}/certification.manifest (86%) rename Ghidra/Processors/{6805/data/languages/6805.ldefs => MC6800/data/languages/6800.ldefs} (64%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6805.cspec (100%) create mode 100644 Ghidra/Processors/MC6800/data/languages/6805.ldefs rename Ghidra/Processors/{6805 => MC6800}/data/languages/6805.pspec (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6805.slaspec (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6809.cspec (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6809.pspec (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6809.slaspec (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6x09.sinc (85%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6x09_exg_tfr.sinc (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6x09_pull.sinc (100%) rename Ghidra/Processors/{6805 => MC6800}/data/languages/6x09_push.sinc (100%) create mode 100644 Ghidra/Processors/MC6800/data/languages/H6309.slaspec rename Ghidra/Processors/{6805 => MC6800}/data/manuals/6809.idx (100%) diff --git a/Ghidra/Processors/6805/Module.manifest b/Ghidra/Processors/MC6800/Module.manifest similarity index 100% rename from Ghidra/Processors/6805/Module.manifest rename to Ghidra/Processors/MC6800/Module.manifest diff --git a/Ghidra/Processors/6805/build.gradle b/Ghidra/Processors/MC6800/build.gradle similarity index 100% rename from Ghidra/Processors/6805/build.gradle rename to Ghidra/Processors/MC6800/build.gradle diff --git a/Ghidra/Processors/6805/certification.manifest b/Ghidra/Processors/MC6800/certification.manifest similarity index 86% rename from Ghidra/Processors/6805/certification.manifest rename to Ghidra/Processors/MC6800/certification.manifest index c78ef5c3de..390dc50b2e 100644 --- a/Ghidra/Processors/6805/certification.manifest +++ b/Ghidra/Processors/MC6800/certification.manifest @@ -1,5 +1,6 @@ ##VERSION: 2.0 Module.manifest||GHIDRA||||END| +data/languages/6800.ldefs||GHIDRA||||END| data/languages/6805.cspec||GHIDRA||||END| data/languages/6805.ldefs||GHIDRA||||END| data/languages/6805.pspec||GHIDRA||reviewed||END| @@ -11,4 +12,5 @@ data/languages/6x09.sinc||GHIDRA||||END| data/languages/6x09_exg_tfr.sinc||GHIDRA||||END| data/languages/6x09_pull.sinc||GHIDRA||||END| data/languages/6x09_push.sinc||GHIDRA||||END| +data/languages/H6309.slaspec||GHIDRA||||END| data/manuals/6809.idx||GHIDRA||||END| diff --git a/Ghidra/Processors/6805/data/languages/6805.ldefs b/Ghidra/Processors/MC6800/data/languages/6800.ldefs similarity index 64% rename from Ghidra/Processors/6805/data/languages/6805.ldefs rename to Ghidra/Processors/MC6800/data/languages/6800.ldefs index 317588ca42..fe2fcf9d99 100644 --- a/Ghidra/Processors/6805/data/languages/6805.ldefs +++ b/Ghidra/Processors/MC6800/data/languages/6800.ldefs @@ -1,22 +1,5 @@ - - - 6805 Microcontroller Family - - - - - - - 6809 Microprocessor + + + + - + + Hitachi 6309 Microprocessor, extension of 6809, 6309 addressing modes, missing many instructions + + + + \ No newline at end of file diff --git a/Ghidra/Processors/6805/data/languages/6805.cspec b/Ghidra/Processors/MC6800/data/languages/6805.cspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6805.cspec rename to Ghidra/Processors/MC6800/data/languages/6805.cspec diff --git a/Ghidra/Processors/MC6800/data/languages/6805.ldefs b/Ghidra/Processors/MC6800/data/languages/6805.ldefs new file mode 100644 index 0000000000..d9ad9489b6 --- /dev/null +++ b/Ghidra/Processors/MC6800/data/languages/6805.ldefs @@ -0,0 +1,15 @@ + + + + 6805 Microcontroller Family + + + + \ No newline at end of file diff --git a/Ghidra/Processors/6805/data/languages/6805.pspec b/Ghidra/Processors/MC6800/data/languages/6805.pspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6805.pspec rename to Ghidra/Processors/MC6800/data/languages/6805.pspec diff --git a/Ghidra/Processors/6805/data/languages/6805.slaspec b/Ghidra/Processors/MC6800/data/languages/6805.slaspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6805.slaspec rename to Ghidra/Processors/MC6800/data/languages/6805.slaspec diff --git a/Ghidra/Processors/6805/data/languages/6809.cspec b/Ghidra/Processors/MC6800/data/languages/6809.cspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6809.cspec rename to Ghidra/Processors/MC6800/data/languages/6809.cspec diff --git a/Ghidra/Processors/6805/data/languages/6809.pspec b/Ghidra/Processors/MC6800/data/languages/6809.pspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6809.pspec rename to Ghidra/Processors/MC6800/data/languages/6809.pspec diff --git a/Ghidra/Processors/6805/data/languages/6809.slaspec b/Ghidra/Processors/MC6800/data/languages/6809.slaspec similarity index 100% rename from Ghidra/Processors/6805/data/languages/6809.slaspec rename to Ghidra/Processors/MC6800/data/languages/6809.slaspec diff --git a/Ghidra/Processors/6805/data/languages/6x09.sinc b/Ghidra/Processors/MC6800/data/languages/6x09.sinc similarity index 85% rename from Ghidra/Processors/6805/data/languages/6x09.sinc rename to Ghidra/Processors/MC6800/data/languages/6x09.sinc index 6e788ea1cd..3216225d3d 100644 --- a/Ghidra/Processors/6805/data/languages/6x09.sinc +++ b/Ghidra/Processors/MC6800/data/languages/6x09.sinc @@ -91,131 +91,238 @@ EA: simm5,idxReg is simm5 & idxReg & noOffset5=0 local addr:2 = idxReg + sext(offs); export addr; } -EA: ","idxReg is idxReg & noOffset5=1 & idxMode=4 # no offset +EA: ","^idxReg is idxReg & noOffset5=1 & idxMode=0b00100 # no offset { local addr:2 = idxReg; export addr; } -EA: simm8,idxReg is idxReg & noOffset5=1 & idxMode=8; simm8 # 8-bit offset +EA: simm8,idxReg is idxReg & noOffset5=1 & idxMode=0b01000; simm8 # 8-bit offset { local addr:2 = idxReg + simm8; export addr; } -EA: simm16,idxReg is idxReg & noOffset5=1 & idxMode=9; simm16 # 16-bit offset +EA: simm16,idxReg is idxReg & noOffset5=1 & idxMode=0b01001; simm16 # 16-bit offset { local addr:2 = idxReg + simm16; export addr; } -EA: "B,"idxReg is idxReg & noOffset5=1 & idxMode=5 # B,R + +@ifdef H6309 +EA: ","^W is idxReg=0b00 & noOffset5=1 & idxMode=0b01111 & W # no offset { - local addr:2 = idxReg + sext(B); + local addr:2 = W; export addr; } -EA: "A,"idxReg is idxReg & noOffset5=1 & idxMode=6 # A,R +EA: simm16,W is idxReg=0b01 & noOffset5=1 & idxMode=0b01111; simm16 & W # 16-bit offset +{ + local addr:2 = W + simm16; + export addr; +} +@endif # H6309 + +EA: A,idxReg is idxReg & noOffset5=1 & idxMode=0b00110 & A # A,R { local addr:2 = idxReg + sext(A); export addr; } -EA: D,idxReg is D & idxReg & noOffset5=1 & idxMode=11 # D,R +EA: B,idxReg is idxReg & noOffset5=1 & idxMode=0b00101 & B # B,R +{ + local addr:2 = idxReg + sext(B); + export addr; +} +EA: D,idxReg is idxReg & noOffset5=1 & idxMode=0b01011 & D # D,R { local addr:2 = idxReg + D; export addr; } -EA: ","idxReg"+" is idxReg & noOffset5=1 & idxMode=0 # ,R+ + +@ifdef H6309 +EA: E,idxReg is idxReg & noOffset5=1 & idxMode=0b00111 & E # E,R +{ + local addr:2 = idxReg + sext(E); + export addr; +} +EA: F,idxReg is idxReg & noOffset5=1 & idxMode=0b01010 & F # F,R +{ + local addr:2 = idxReg + sext(F); + export addr; +} +EA: W,idxReg is idxReg & noOffset5=1 & idxMode=0b01110 & W # W,R +{ + local addr:2 = idxReg + W; + export addr; +} +@endif # H6309 + + +EA: ","^idxReg^"+" is idxReg & noOffset5=1 & idxMode=0b00000 # ,R+ { addr:2 = idxReg; idxReg = idxReg + 1; export addr; } -EA: ","idxReg"++" is idxReg & noOffset5=1 & idxMode=1 # ,R++ +EA: ","^idxReg^"++" is idxReg & noOffset5=1 & idxMode=0b00001 # ,R++ { local addr:2 = idxReg; idxReg = idxReg + 2; export addr; } -EA: ",-"idxReg is idxReg & noOffset5=1 & idxMode=2 # ,-R +EA: ",-"^idxReg is idxReg & noOffset5=1 & idxMode=0b00010 # ,-R { idxReg = idxReg - 1; local addr:2 = idxReg; export addr; } -EA: ",--"idxReg is idxReg & noOffset5=1 & idxMode=3 # ,--R +EA: ",--"^idxReg is idxReg & noOffset5=1 & idxMode=0b00011 # ,--R { idxReg = idxReg - 2; local addr:2 = idxReg; export addr; } -EA: addr",PCR" is noOffset5=1 & idxMode=12; simm8 [ addr = inst_next + simm8; ] + +@ifdef H6309 +EA: ","^W^"++" is idxReg=0b10 & noOffset5=1 & idxMode=0b01111 & W # ,W++ +{ + local addr:2 = W; + W = W + 2; + export addr; +} +EA: ",--"^W is idxReg=0b11 & noOffset5=1 & idxMode=0b01111 & W # ,--W +{ + W = W - 2; + local addr:2 = W; + export addr; +} +@endif # H6309 + +EA: addr,"PCR" is noOffset5=1 & idxMode=0b01100; simm8 [ addr = inst_next + simm8; ] { export addr; } -EA: addr",PCR" is noOffset5=1 & idxMode=13; simm16 [ addr = inst_next + simm16; ] +EA: addr,"PCR" is noOffset5=1 & idxMode=0b01101; simm16 [ addr = inst_next + simm16; ] { export addr; } -EA: "[,"idxReg"]" is idxReg & noOffset5=1 & idxMode=20 +EA: "[,"idxReg"]" is idxReg & noOffset5=1 & idxMode=0b10100 { local addr:2 = *:2 idxReg; export addr; } -EA: "["simm8,idxReg"]" is idxReg & noOffset5=1 & idxMode=24; simm8 +EA: "["simm8,idxReg"]" is idxReg & noOffset5=1 & idxMode=0b11000; simm8 { local offs:1 = simm8; local addr:2 = idxReg + sext(offs); addr = *:2 addr; export addr; } -EA: "["simm16,idxReg"]" is idxReg & noOffset5=1 & idxMode=25; simm16 +EA: "["simm16,idxReg"]" is idxReg & noOffset5=1 & idxMode=0b11001; simm16 { local addr:2 = idxReg + simm16; addr = *:2 addr; export addr; } -EA: "[B,"idxReg"]" is idxReg & noOffset5=1 & idxMode=21 + +@ifdef H6309 +EA: "[,"W"]" is idxReg=0b00 & noOffset5=1 & idxMode=0b10000 & W { - local addr:2 = idxReg + sext(B); + local addr:2 = *:2 W; + export addr; +} +EA: "["simm16,W"]" is idxReg=0b01 & noOffset5=1 & idxMode=0b10000; simm16 & W +{ + local addr:2 = W + simm16; addr = *:2 addr; export addr; } -EA: "[A,"idxReg"]" is idxReg & noOffset5=1 & idxMode=22 +@endif # H6309 + +EA: "["^A,idxReg"]" is A & idxReg & noOffset5=1 & idxMode=0b10110 { local addr:2 = idxReg + sext(A); addr = *:2 addr; export addr; } -EA: "["D,idxReg"]" is D & idxReg & noOffset5=1 & idxMode=27 +EA: "["^B,idxReg"]" is B & idxReg & noOffset5=1 & idxMode=0b10101 +{ + local addr:2 = idxReg + sext(B); + addr = *:2 addr; + export addr; +} +EA: "["^D,idxReg"]" is D & idxReg & noOffset5=1 & idxMode=0b11011 { local addr:2 = idxReg + D; addr = *:2 addr; export addr; } -EA: "[,"idxReg"++]" is idxReg & noOffset5=1 & idxMode=17 + +@ifdef H6309 +EA: "["^E,idxReg"]" is E & idxReg & noOffset5=1 & idxMode=0b10111 +{ + local addr:2 = idxReg + sext(E); + addr = *:2 addr; + export addr; +} +EA: "["^F,idxReg"]" is F & idxReg & noOffset5=1 & idxMode=0b11010 +{ + local addr:2 = idxReg + sext(F); + addr = *:2 addr; + export addr; +} +EA: "["^W,idxReg"]" is W & idxReg & noOffset5=1 & idxMode=0b11110 +{ + local addr:2 = idxReg + W; + addr = *:2 addr; + export addr; +} +@endif # H6309 + + +EA: "[,"idxReg"++]" is idxReg & noOffset5=1 & idxMode=0b10001 { local addr:2 = idxReg; addr = *:2 addr; idxReg = idxReg + 2; export addr; } -EA: "[,--"idxReg"]" is idxReg & noOffset5=1 & idxMode=19 +EA: "[,--"idxReg"]" is idxReg & noOffset5=1 & idxMode=0b10011 { idxReg = idxReg - 2; local addr:2 = idxReg; addr = *:2 addr; export addr; } -EA: "["addr",PCR]" is noOffset5=1 & idxMode=28; simm8 [ addr = inst_next + simm8; ] + +@ifdef H6309 +EA: "[,"^W^"++]" is W & idxReg=0b10 & noOffset5=1 & idxMode=0b10000 +{ + local addr:2 = W; + addr = *:2 addr; + W = W + 2; + export addr; +} +EA: "[,--"^W^"]" is W & idxReg=0b11 & noOffset5=1 & idxMode=0b10000 +{ + W = W - 2; + local addr:2 = W; + addr = *:2 addr; + export addr; +} +@endif # H6309 + +EA: "["addr",PCR]" is noOffset5=1 & idxMode=0b11100; simm8 [ addr = inst_next + simm8; ] { local eaddr:2 = inst_next + simm8; eaddr = *:2 eaddr; export eaddr; } -EA: "["addr",PCR]" is noOffset5=1 & idxMode=29; simm16 [ addr = inst_next + simm16; ] +EA: "["addr",PCR]" is noOffset5=1 & idxMode=0b11101; simm16 [ addr = inst_next + simm16; ] { local eaddr:2 = inst_next + simm16; eaddr = *:2 eaddr; export eaddr; } -EA: "["addr"]" is imm8=0x9F; simm16 [ addr = inst_next; ] + +EA: "["addr"]" is noOffset5=1 & idxReg=0b00 & idxMode=0b11101; simm16 [ addr = inst_next; ] { local eaddr:2 = inst_next; eaddr = *:2 eaddr; diff --git a/Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc b/Ghidra/Processors/MC6800/data/languages/6x09_exg_tfr.sinc similarity index 100% rename from Ghidra/Processors/6805/data/languages/6x09_exg_tfr.sinc rename to Ghidra/Processors/MC6800/data/languages/6x09_exg_tfr.sinc diff --git a/Ghidra/Processors/6805/data/languages/6x09_pull.sinc b/Ghidra/Processors/MC6800/data/languages/6x09_pull.sinc similarity index 100% rename from Ghidra/Processors/6805/data/languages/6x09_pull.sinc rename to Ghidra/Processors/MC6800/data/languages/6x09_pull.sinc diff --git a/Ghidra/Processors/6805/data/languages/6x09_push.sinc b/Ghidra/Processors/MC6800/data/languages/6x09_push.sinc similarity index 100% rename from Ghidra/Processors/6805/data/languages/6x09_push.sinc rename to Ghidra/Processors/MC6800/data/languages/6x09_push.sinc diff --git a/Ghidra/Processors/MC6800/data/languages/H6309.slaspec b/Ghidra/Processors/MC6800/data/languages/H6309.slaspec new file mode 100644 index 0000000000..0f82d8b8fe --- /dev/null +++ b/Ghidra/Processors/MC6800/data/languages/H6309.slaspec @@ -0,0 +1,10 @@ +# sleigh specification file for Hitachi 6309 +# Compatible with MC6809 with some extended instructions +# and addressing modes + +@define H6309 "" + +@include "6x09.sinc" +@include "6x09_push.sinc" +@include "6x09_pull.sinc" +@include "6x09_exg_tfr.sinc" diff --git a/Ghidra/Processors/6805/data/manuals/6809.idx b/Ghidra/Processors/MC6800/data/manuals/6809.idx similarity index 100% rename from Ghidra/Processors/6805/data/manuals/6809.idx rename to Ghidra/Processors/MC6800/data/manuals/6809.idx