From cd0e9eb401c31edeefa11c0b64384f8c06821885 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rubens=20Brand=C3=A3o?= Date: Sat, 6 Aug 2022 11:08:59 -0300 Subject: [PATCH] Sleigh ARMNeon have an ambiguious pattern On the Arm Neon sleigh file, the table `vld4Align2` pattern is ambiguous. The Pattern `TMode=0 & (c1011=1 & c0404=1) | (c1011=2 & c0405=1)`. Can be interpreted by the parser as: `(TMode=0 & ((c1011=1 & c0404=1)) | (c1011=2 & c0405=1)` or `TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1))` Similar to the Thumb constructor on line [2432](https://github.com/NationalSecurityAgency/ghidra/blob/6fad151b5440de3dfdd619df7b5dc070b2b4dc6c/Ghidra/Processors/ARM/data/languages/ARMneon.sinc#L2432), the second interpretation, should be enforced. --- Ghidra/Processors/ARM/data/languages/ARMneon.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc index 9ada3fceda..67eab34c1c 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -2425,7 +2425,7 @@ vld4DdElement2: Dreg^"["^vld4Index^"]" is Dreg & vld4Index vld4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } vld4Align2: "@32" is TMode=0 & c1011=0 & c0404=1 { } -vld4Align2: "@64" is TMode=0 & (c1011=1 & c0404=1) | (c1011=2 & c0405=1) { } +vld4Align2: "@64" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { } vld4Align2: "@128" is TMode=0 & c1011=2 & c0405=2 { } vld4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { } vld4Align2: "@32" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }