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Sleigh ARMNeon have an ambiguious pattern

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On the Arm Neon sleigh file, the table `vld4Align2` pattern is ambiguous.

The Pattern `TMode=0 & (c1011=1 & c0404=1) | (c1011=2 & c0405=1)`.
Can be interpreted by the parser as: `(TMode=0 & ((c1011=1 & c0404=1)) | (c1011=2 & c0405=1)` or `TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1))`

Similar to the Thumb constructor on line [2432](6fad151b54/Ghidra/Processors/ARM/data/languages/ARMneon.sinc (L2432)), the second interpretation, should be enforced.
This commit is contained in:
Rubens Brandão
2022-08-06 11:08:59 -03:00
committed by GitHub
parent 6fad151b54
commit cd0e9eb401
1 changed files with 1 additions and 1 deletions
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2
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
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@@ -2425,7 +2425,7 @@ vld4DdElement2: Dreg^"["^vld4Index^"]" is Dreg & vld4Index
vld4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { }
vld4Align2: "@32" is TMode=0 & c1011=0 & c0404=1 { }
vld4Align2: "@64" is TMode=0 & (c1011=1 & c0404=1) | (c1011=2 & c0405=1) { }
vld4Align2: "@64" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { }
vld4Align2: "@128" is TMode=0 & c1011=2 & c0405=2 { }
vld4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { }
vld4Align2: "@32" is TMode=1 & thv_c1011=0 & thv_c0404=1 { }