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GP-2480 Console mode inst_next2 support and documentation update

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caheckman
2022-08-24 14:56:34 -04:00
committed by ghidra1
parent 8d4a6c213e
commit d33cd8a92e
23 changed files with 348 additions and 275 deletions
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6
GhidraDocs/languages/html/sleigh_context.html
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@@ -4,7 +4,7 @@
<title>8. Using Context</title>
<link rel="stylesheet" type="text/css" href="Frontpage.css">
<link rel="stylesheet" type="text/css" href="languages.css">
<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="sleigh.html" title="SLEIGH">
<link rel="up" href="sleigh.html" title="SLEIGH">
<link rel="prev" href="sleigh_constructors.html" title="7. Constructors">
@@ -85,7 +85,7 @@ whose encodings are otherwise the same.
</p>
<div class="sect2">
<div class="titlepage"><div><div><h3 class="title">
<a name="idm140526920261472"></a>8.1. Basic Use of Context Variables</h3></div></div></div>
<a name="sleigh_context_basic"></a>8.1. Basic Use of Context Variables</h3></div></div></div>
<p>
Suppose a processor supports the use of two different sets of
registers in its main addressing mode, based on the setting of a
@@ -100,7 +100,7 @@ define space ram type=ram_space size=4 default;
define space register type=register_space size=4;
define register offset=0 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 ];
define register offset=0x100 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 ];
define register offset=0x200 size=4 [ contextreg ]; # define context bits (if defined, size must be multiple of 4-bytes)
define register offset=0x200 size=4 [ statusreg ]; # define context bits (if defined, size must be multiple of 4-bytes)
define token instr(16)
op=(10,15) rreg1=(7,9) sreg1=(7,9) imm=(0,6)