From d69dbe5c97c2c26557af3244b4a15c2e1673d180 Mon Sep 17 00:00:00 2001 From: shrlnm Date: Tue, 19 Nov 2019 11:43:58 +0300 Subject: [PATCH] fix movi20 and movi20s --- Ghidra/Processors/SuperH/data/languages/superh.sinc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Ghidra/Processors/SuperH/data/languages/superh.sinc b/Ghidra/Processors/SuperH/data/languages/superh.sinc index 3b3f997065..ebe30d6ea9 100644 --- a/Ghidra/Processors/SuperH/data/languages/superh.sinc +++ b/Ghidra/Processors/SuperH/data/languages/superh.sinc @@ -91,7 +91,7 @@ define token instr32(32) l_rm_20_23 = (20, 23) l_rn_24_27 = (24, 27) l_opcode_28_31 = (28, 31) - l_imm20_00_16 = (0, 16) + l_imm20_00_15 = (0, 15) l_simm20_20_23 = (20, 23) signed l_imm3_20_22 = (20, 22) ; @@ -499,12 +499,12 @@ disppc2: @(disp,pc) is disp_00_07 & pc l_rm_20_23 = zext(*:2 (disp + l_rm_20_23)); } -simm20: "#"value is l_simm20_20_23 & l_imm20_00_16 - [ value = ((l_simm20_20_23 << 16) | l_imm20_00_16); ] +simm20: "#"value is l_simm20_20_23 & l_imm20_00_15 + [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15); ] { export *[const]:4 value; } -simm20s: "#"value is l_simm20_20_23 & l_imm20_00_16 - [ value = ((l_simm20_20_23 << 16) | l_imm20_00_16) << 8; ] +simm20s: "#"value is l_simm20_20_23 & l_imm20_00_15 + [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15) << 8; ] { export *[const]:4 value; }