From d7e51ee5154a218499e8d0aa0b467765caca4cb1 Mon Sep 17 00:00:00 2001 From: mumbel <22204578+mumbel@users.noreply.github.com> Date: Wed, 21 Aug 2019 18:36:45 -0500 Subject: [PATCH] RISC-V processor [riscv] Added context register for extensions [riscv] missed a define in refactor [riscv] got 100% on RV32IMC [riscv] Add throw away script to generate SLEIGH [riscv] Fixes from SleighDevTools - R4-type were using a bad bit pattern that broke the rs3 operand - mul had a copy/paste typo that ignored the rs2 operand - bad define guard for compressesed instruction --- Ghidra/Processors/RISCV/Module.manifest | 0 Ghidra/Processors/RISCV/build.gradle | 11 + .../Processors/RISCV/certification.manifest | 37 + .../RISCV/data/languages/RV32G.pspec | 11 + .../RISCV/data/languages/RV32GC.pspec | 12 + .../RISCV/data/languages/RV32I.pspec | 11 + .../RISCV/data/languages/RV32IC.pspec | 12 + .../RISCV/data/languages/RV32IMC.pspec | 13 + .../RISCV/data/languages/RV64G.pspec | 11 + .../RISCV/data/languages/RV64GC.pspec | 12 + .../RISCV/data/languages/RV64I.pspec | 11 + .../RISCV/data/languages/RV64IC.pspec | 12 + .../RISCV/data/languages/riscv.csr.sinc | 172 + .../RISCV/data/languages/riscv.ilp32.slaspec | 12 + .../RISCV/data/languages/riscv.ilp32d.slaspec | 12 + .../RISCV/data/languages/riscv.ilp32f.slaspec | 12 + .../RISCV/data/languages/riscv.instr.sinc | 1024 ++++++ .../RISCV/data/languages/riscv.ldefs | 138 + .../RISCV/data/languages/riscv.lp64.slaspec | 12 + .../RISCV/data/languages/riscv.lp64d.slaspec | 12 + .../RISCV/data/languages/riscv.lp64f.slaspec | 12 + .../RISCV/data/languages/riscv.opinion | 25 + .../RISCV/data/languages/riscv.priv.sinc | 63 + .../RISCV/data/languages/riscv.reg.sinc | 793 +++++ .../RISCV/data/languages/riscv.rv32a.sinc | 134 + .../RISCV/data/languages/riscv.rv32d.sinc | 335 ++ .../RISCV/data/languages/riscv.rv32f.sinc | 358 ++ .../RISCV/data/languages/riscv.rv32i.sinc | 359 +++ .../RISCV/data/languages/riscv.rv32m.sinc | 66 + .../RISCV/data/languages/riscv.rv32q.sinc | 322 ++ .../RISCV/data/languages/riscv.rv64a.sinc | 135 + .../RISCV/data/languages/riscv.rv64d.sinc | 82 + .../RISCV/data/languages/riscv.rv64f.sinc | 70 + .../RISCV/data/languages/riscv.rv64i.sinc | 122 + .../RISCV/data/languages/riscv.rv64m.sinc | 45 + .../RISCV/data/languages/riscv.rv64q.sinc | 62 + .../RISCV/data/languages/riscv.rvc.sinc | 371 +++ .../RISCV/data/languages/riscv.table.sinc | 359 +++ .../RISCV/data/languages/riscv.zi.sinc | 6 + .../RISCV/data/languages/riscv32-fp.cspec | 133 + .../RISCV/data/languages/riscv32-fp.dwarf | 22 + .../RISCV/data/languages/riscv32.cspec | 89 + .../RISCV/data/languages/riscv32.dwarf | 16 + .../RISCV/data/languages/riscv64-fp.cspec | 133 + .../RISCV/data/languages/riscv64-fp.dwarf | 22 + .../RISCV/data/languages/riscv64.cspec | 89 + .../RISCV/data/languages/riscv64.dwarf | 16 + Ghidra/Processors/RISCV/scripts/binutil.py | 2871 +++++++++++++++++ .../core/analysis/RISCVAddressAnalyzer.java | 146 + .../format/elf/extend/RISCV_ElfExtension.java | 49 + .../RISCV_ElfRelocationConstants.java | 84 + .../RISCV_ElfRelocationHandler.java | 459 +++ .../RISCVEmulateInstructionStateModifier.java | 61 + .../processors/RV32GC_O0_EmulatorTest.java | 40 + .../processors/RV32GC_O3_EmulatorTest.java | 40 + .../processors/RV32IMC_O0_EmulatorTest.java | 39 + .../processors/RV64GC_O0_EmulatorTest.java | 40 + .../processors/RV64GC_O3_EmulatorTest.java | 40 + .../processors/RV64G_O0_EmulatorTest.java | 40 + .../processors/RV64G_O3_EmulatorTest.java | 40 + 60 files changed, 9735 insertions(+) create mode 100644 Ghidra/Processors/RISCV/Module.manifest create mode 100644 Ghidra/Processors/RISCV/build.gradle create mode 100644 Ghidra/Processors/RISCV/certification.manifest create mode 100644 Ghidra/Processors/RISCV/data/languages/RV32G.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV32GC.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV32I.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV32IC.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV64G.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV64GC.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV64I.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/RV64IC.pspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.ldefs create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.opinion create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.table.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv32.cspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv32.dwarf create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv64.cspec create mode 100644 Ghidra/Processors/RISCV/data/languages/riscv64.dwarf create mode 100644 Ghidra/Processors/RISCV/scripts/binutil.py create mode 100644 Ghidra/Processors/RISCV/src/main/java/ghidra/app/plugin/core/analysis/RISCVAddressAnalyzer.java create mode 100644 Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/extend/RISCV_ElfExtension.java create mode 100644 Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationConstants.java create mode 100644 Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationHandler.java create mode 100644 Ghidra/Processors/RISCV/src/main/java/ghidra/program/emulation/RISCVEmulateInstructionStateModifier.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O3_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32IMC_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O3_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O3_EmulatorTest.java diff --git a/Ghidra/Processors/RISCV/Module.manifest b/Ghidra/Processors/RISCV/Module.manifest new file mode 100644 index 0000000000..e69de29bb2 diff --git a/Ghidra/Processors/RISCV/build.gradle b/Ghidra/Processors/RISCV/build.gradle new file mode 100644 index 0000000000..9f5dcab806 --- /dev/null +++ b/Ghidra/Processors/RISCV/build.gradle @@ -0,0 +1,11 @@ +apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" +apply from: "$rootProject.projectDir/gradle/javaProject.gradle" +apply from: "$rootProject.projectDir/gradle/processorProject.gradle" +apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle" +apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle" +apply plugin: 'eclipse' +eclipse.project.name = 'Processors RISCV' + +dependencies { + compile project(':Base') +} diff --git a/Ghidra/Processors/RISCV/certification.manifest b/Ghidra/Processors/RISCV/certification.manifest new file mode 100644 index 0000000000..2371dd2eba --- /dev/null +++ b/Ghidra/Processors/RISCV/certification.manifest @@ -0,0 +1,37 @@ +##VERSION: 2.0 +Module.manifest||GHIDRA||||END| +build.gradle||GHIDRA||||END| +data/languages/riscv.ldefs||GHIDRA||||END| +data/languages/riscv.opinion||GHIDRA||||END| +data/languages/riscv.pspec||GHIDRA||||END| +data/languages/riscv32.cspec||GHIDRA||||END| +data/languages/riscv64.cspec||GHIDRA||||END| +data/languages/riscv32.dwarf||GHIDRA||||END| +data/languages/riscv64.dwarf||GHIDRA||||END| +data/languages/RV32I.slaspec||GHIDRA||||END| +data/languages/RV32IC.slaspec||GHIDRA||||END| +data/languages/RV32G.slaspec||GHIDRA||||END| +data/languages/RV32GC.slaspec||GHIDRA||||END| +data/languages/RV64I.slaspec||GHIDRA||||END| +data/languages/RV64IC.slaspec||GHIDRA||||END| +data/languages/RV64G.slaspec||GHIDRA||||END| +data/languages/RV64GC.slaspec||GHIDRA||||END| +data/languages/riscv.instr.sinc||GHIDRA||||END| +data/languages/riscv.reg.sinc||GHIDRA||||END| +data/languages/riscv.table.sinc||GHIDRA||||END| +data/languages/riscv.csr.sinc||GHIDRA||||END| +data/languages/riscv.priv.sinc||GHIDRA||||END| +data/languages/riscv.rv32a.sinc||GHIDRA||||END| +data/languages/riscv.rv32d.sinc||GHIDRA||||END| +data/languages/riscv.rv32f.sinc||GHIDRA||||END| +data/languages/riscv.rv32i.sinc||GHIDRA||||END| +data/languages/riscv.rv32m.sinc||GHIDRA||||END| +data/languages/riscv.rv32q.sinc||GHIDRA||||END| +data/languages/riscv.rv64a.sinc||GHIDRA||||END| +data/languages/riscv.rv64d.sinc||GHIDRA||||END| +data/languages/riscv.rv64f.sinc||GHIDRA||||END| +data/languages/riscv.rv64i.sinc||GHIDRA||||END| +data/languages/riscv.rv64m.sinc||GHIDRA||||END| +data/languages/riscv.rv64q.sinc||GHIDRA||||END| +data/languages/riscv.rvc.sinc||GHIDRA||||END| +data/languages/riscv.zi.sinc||GHIDRA||||END| diff --git a/Ghidra/Processors/RISCV/data/languages/RV32G.pspec b/Ghidra/Processors/RISCV/data/languages/RV32G.pspec new file mode 100644 index 0000000000..4ae572b3e3 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV32G.pspec @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec new file mode 100644 index 0000000000..30a359fcfa --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV32I.pspec b/Ghidra/Processors/RISCV/data/languages/RV32I.pspec new file mode 100644 index 0000000000..c2f0d8f3f8 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV32I.pspec @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec new file mode 100644 index 0000000000..19e5af29d3 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec b/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec new file mode 100644 index 0000000000..7a67fe559c --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV64G.pspec b/Ghidra/Processors/RISCV/data/languages/RV64G.pspec new file mode 100644 index 0000000000..789744421c --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV64G.pspec @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec new file mode 100644 index 0000000000..b336b24854 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV64I.pspec b/Ghidra/Processors/RISCV/data/languages/RV64I.pspec new file mode 100644 index 0000000000..1af12e37bd --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV64I.pspec @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec b/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec new file mode 100644 index 0000000000..3aeb8c2115 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc new file mode 100644 index 0000000000..cc2c099490 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc @@ -0,0 +1,172 @@ +# RV32/RV64 Zicsr Standard Extension + + +# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) +:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519 +{ + #TODO Size restriction error + # local tmprs1:$(XLEN) = rs1; + # local oldcsr:$(XLEN) = csr:$(XLEN); + # rd = oldcsr; + # local tmp:$(XLEN) = op1519; + # if (tmp == 0) goto inst_next; + # local newcsr:$(XLEN) = oldcsr & ~tmprs1; + # csr = zext(newcsr); +} + + +# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) +:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +{ + #TODO Size restriction error + # local oldcsr:$(XLEN) = csr:$(XLEN); + # rd = oldcsr; + # local tmp:$(XLEN) = op1519; + # if (tmp == 0) goto inst_next; + # csr = csr & ~tmp; +} + + +# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) +:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 +{ + #TODO Size restriction error + # local tmprs1 = rs1; + # local oldcsr:$(XLEN) = csr:$(XLEN); + # rd = oldcsr; + # local tmp:$(XLEN) = op1519; + # if (tmp == 0) goto inst_next; + # csr = csr | tmprs1; +} + + +# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) +:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +{ + #TODO Size restriction error + # local oldcsr:$(XLEN) = csr:$(XLEN); + # rd = oldcsr; + # local tmp:$(XLEN) = op1519; + # if (tmp == 0) goto inst_next; + # csr = csr | tmp; +} + + +# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) +:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519 +{ + #TODO Size restriction error + # local tmprs1:$(XLEN) = rs1; + # local oldcsr:$(XLEN) = csr:$(XLEN); + # local tmp:$(XLEN) = op1519; + # csr = tmprs1; + # if (tmp == 0) goto inst_next; + # rd = oldcsr; +} + + +# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) +:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 +{ + #TODO Size restriction error + # local oldcsr:$(XLEN) = csr:$(XLEN); + # local tmp:$(XLEN) = op1519; + # csr = tmp; + # if (tmp == 0) goto inst_next; + # rd = oldcsr; +} + + +# frcsr d 00302073 fffff07f SIMPLE (0, 0) +:frcsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 +{ + rd = fcsr; +} + +# frflags d 00102073 fffff07f SIMPLE (0, 0) +:frflags rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20 +{ + rd = zext(fflags[0,5]); +} + +# frrm d 00202073 fffff07f SIMPLE (0, 0) +:frrm rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40 +{ + rd = frm; +} + +# fscsr s 00301073 fff07fff SIMPLE (0, 0) +:fscsr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3 +{ + zero = fcsr; + fcsr = rs1; +} + +# fscsr d,s 00301073 fff0707f SIMPLE (0, 0) +:fscsr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 +{ + rd = fcsr; + fcsr = rs1; +} + + +# fsflags s 00101073 fff07fff SIMPLE (0, 0) +:fsflags rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x1 +{ + zero = zext(fflags[0,5]); + fflags[0,5] = rs1[0,5]; +} + +# fsflags d,s 00101073 fff0707f SIMPLE (0, 0) +:fsflags rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1 +{ + rd = zext(fflags[0,5]); + fflags[0,5] = rs1[0,5]; +} + +# fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0) +:fsflagsi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1 +{ + rd = zext(fflags[0,5]); + local tmp:1 = op1519:1; + fflags[0,5] = tmp[0,5]; +} + +# fsflagsi Z 00105073 fff07fff SIMPLE (0, 0) +:fsflagsi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x1 +{ + zero = zext(fflags[0,5]); + local tmp:1 = op1519:1; + fflags[0,5] = tmp[0,5]; +} + +# fsrm s 00201073 fff07fff SIMPLE (0, 0) +:fsrm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x2 +{ + zero = zext(frm[0,3]); + frm[0,3] = rs1[0,3]; +} + +# fsrm d,s 00201073 fff0707f SIMPLE (0, 0) +:fsrm rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2 +{ + rd = zext(frm[0,3]); + frm[0,3] = rs1[0,3]; +} + +# fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0) +:fsrmi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2 +{ + rd = zext(frm[0,3]); + local tmp:1 = op1519:1; + frm[0,3] = tmp[0,3]; +} + +# fsrmi Z 00205073 fff07fff SIMPLE (0, 0) +:fsrmi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x2 +{ + zero = zext(frm[0,3]); + local tmp:1 = op1519:1; + frm[0,3] = tmp[0,3]; +} + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec new file mode 100644 index 0000000000..58d9312de3 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 4 +@define XLEN2 8 +@define FLEN 0 + +@define ADDRSIZE "32" +@define FPSIZE "" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec new file mode 100644 index 0000000000..c8157a3f5e --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 4 +@define XLEN2 8 +@define FLEN 8 + +@define ADDRSIZE "32" +@define FPSIZE "64" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec new file mode 100644 index 0000000000..6838e4d0d9 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.ilp32f.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 4 +@define XLEN2 8 +@define FLEN 4 + +@define ADDRSIZE "32" +@define FPSIZE "32" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc new file mode 100644 index 0000000000..77c6c9f1ab --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc @@ -0,0 +1,1024 @@ +# This is just a top level to include the standards + +@include "riscv.rv32i.sinc" +@include "riscv.rv32a.sinc" +@include "riscv.rv32d.sinc" +@include "riscv.rv32f.sinc" +@include "riscv.rv32m.sinc" +@include "riscv.rv32q.sinc" + +@if ADDRSIZE == "64" +@include "riscv.rv64i.sinc" +@include "riscv.rv64a.sinc" +@include "riscv.rv64d.sinc" +@include "riscv.rv64f.sinc" +@include "riscv.rv64m.sinc" +@include "riscv.rv64q.sinc" +@endif + +@include "riscv.csr.sinc" +@include "riscv.priv.sinc" +@include "riscv.rvc.sinc" +@include "riscv.zi.sinc" + + + +# todos that may be possible, mostly just artifacts from my +# script to generate the initial SELIGH + + +#TODO ALIAS +# add d,CU,CV 00009002 0000f003 ALIAS (0, 0) +#:add crd,crs1,crs2 is crd & crs2 & crs1 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# add d,CV,CU 00009002 0000f003 ALIAS (0, 0) +#:add crd,crs2,crs1 is crd & crs1 & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# add d,CU,Co 00000001 0000e003 ALIAS (0, 0) +#:add crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# add Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) +#:add cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# add Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) +#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#:add sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# add d,s,j 00000013 0000707f ALIAS (0, 0) +#:add rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 +#{ +#} + +#TODO ALIAS +# addi Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) +#:addi cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# addi d,CU,Cj 00000001 0000e003 ALIAS (0, 0) +#:addi crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# addi d,CU,z 00000001 0000f07f ALIAS (0, 0) +#:addi crd,crs1,zero is crd & zero & crs1 & cop0001=0x1 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# addi Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) +#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#:addi sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# addiw d,CU,Co 00002001 0000e003 ALIAS (64, 0) +#TODO 32 64 +#:addiw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw Cs,Cw,Ct 00009c21 0000fc63 ALIAS (64, 0) +#:addw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw Cs,Ct,Cw 00009c21 0000fc63 ALIAS (64, 0) +#:addw cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw d,CU,Co 00002001 0000e003 ALIAS (64, 0) +#TODO crd,crs1,cimmI crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#:addw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw d,s,j 0000001b 0000707f ALIAS (64, 0) +#:addw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# and Cs,Cw,Ct 00008c61 0000fc63 ALIAS (0, 0) +#:and cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# and Cs,Ct,Cw 00008c61 0000fc63 ALIAS (0, 0) +#:and cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# and Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) +#:and cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +#{ +#} + +#TODO ALIAS +# and d,s,j 00007013 0000707f ALIAS (0, 0) +#:and rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# andi Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) +#:andi cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +#{ +#} + +#TODO ALIAS +# beq Cs,Cz,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:beq cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x6 +#{ +#} + +#TODO ALIAS +# beqz Cs,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6 +#{ +#} + +#TODO ALIAS +# beqz s,p 00000063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:beqz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bgez s,p 00005063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bgez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bgt t,s,p 00004063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bgt rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 +#{ +#} + +#TODO ALIAS +# bgtu t,s,p 00006063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bgtu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# bgtz t,p 00004063 000ff07f CONDBRANCH|ALIAS (0, 0) +#:bgtz rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# ble t,s,p 00005063 0000707f CONDBRANCH|ALIAS (0, 0) +#:ble rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 +#{ +#} + +#TODO ALIAS +# bleu t,s,p 00007063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bleu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# blez t,p 00005063 000ff07f CONDBRANCH|ALIAS (0, 0) +#:blez rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# bltz s,p 00004063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bltz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bne Cs,Cz,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:bne cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x7 +#{ +#} + +#TODO ALIAS +# bnez Cs,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7 +#{ +#} + +#TODO ALIAS +# bnez s,p 00001063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bnez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1 & op2024=0x0 +#{ +#} + + +#@if defined(RISCV128I) +#TODO 128 +#:c.lq +#@endif + +#TODO ALIAS +# c.nop 00000001 0000ffff ALIAS (0, 0) +#:c.nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0 +#{ +#} + +#TODO ALIAS +# c.nop Cj 00000001 0000ef83 ALIAS (0, 0) +#:c.nop cimmI is cimmI & cop0001=0x1 & cop1315=0x0 & cop0711=0x0 +#{ +#} + +#TODO MACRO +# call d,c 00030000 00000015 MACRO (0, 64) + +#TODO MACRO +# call c 00008080 00000015 MACRO (0, 64) + +#TODO ALIAS +# csrc E,s 00003073 00007fff ALIAS (0, 0) +#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrc E,Z 00007073 00007fff ALIAS (0, 0) +#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrci E,Z 00007073 00007fff ALIAS (0, 0) +#:csrci csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrr d,E 00002073 000ff07f ALIAS (0, 0) +#:csrr rd,csr is csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# csrrc d,E,Z 00007073 0000707f ALIAS (0, 0) +#:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# csrrs d,E,Z 00006073 0000707f ALIAS (0, 0) +#:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# csrrw d,E,Z 00005073 0000707f ALIAS (0, 0) +#:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 +#{ +#} + +#TODO ALIAS +# csrs E,s 00002073 00007fff ALIAS (0, 0) +#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrs E,Z 00006073 00007fff ALIAS (0, 0) +#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrsi E,Z 00006073 00007fff ALIAS (0, 0) +#:csrsi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrw E,s 00001073 00007fff ALIAS (0, 0) +#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrw E,Z 00005073 00007fff ALIAS (0, 0) +#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrwi E,Z 00005073 00007fff ALIAS (0, 0) +#:csrwi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 +#{ +#} + + + +#TODO ALIAS +# ebreak 00009002 0000ffff ALIAS (0, 0) +#:ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400 +#{ +#} + +#TODO ALIAS +# fabs.q D,U 26002053 fe00707f ALIAS (0, 0) +#:fabs.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# fence 0ff0000f ffffffff ALIAS (0, 0) +#:fence is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1527=0x1fe0 +#{ +#} + +#TODO ALIAS +# fence.tso 8330000f ffffffff ALIAS (0, 0) +#:fence.tso is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x8 & op0711=0x0 & op1527=0x660 +#{ +#} + +#TODO SEE fle.d +# fge.d d,T,S a2000053 fe00707f SIMPLE (0, 0) +# :fge.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51 +# { +# } + +#TODO SEE fle.q +# fge.q d,T,S a6000053 fe00707f SIMPLE (0, 0) +# :fge.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53 +# { +# } + +#TODO SEE fle.s +# fge.s d,T,S a0000053 fe00707f SIMPLE (0, 0) +# :fge.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50 +# { +# } + +#TODO SEE flt.d +# fgt.d d,T,S a2001053 fe00707f SIMPLE (0, 0) +# :fgt.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51 +# { +# } + +#TODO SEE flt.q +# fgt.q d,T,S a6001053 fe00707f SIMPLE (0, 0) +# :fgt.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53 +# { +# } + +#TODO SEE flt.s +# fgt.s d,T,S a0001053 fe00707f SIMPLE (0, 0) +# :fgt.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50 +# { +# } + +#TODO ALIAS +# fld D,Cn(Cc) 00002002 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO cfr0711,cldspimm(sp) cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1 +#:fld cfr0711,cldspimm(sp) is cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1 +#{ +#} + +#TODO ALIAS +# fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO 32 64 +#:fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm +#{ +#} + +#TODO MACRO +# fld D,A,s 00000000 00000010 MACRO (0, 64) + +#TODO MACRO +# flq D,A,s 00000000 00000011 MACRO (0, 64) + + +#@if defined(RISCV32I) +#TODO ALIAS +# flw D,Cm(Cc) 00006002 0000e003 DWORD|DREF|ALIAD (32, 4) +#TODO cfr0711,clwspimm(sp) cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3 +#:flw cfr0711,clwspimm(sp) is cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3 +#{ +#} +#@endif + +#@if defined(RISCV32I) +#TODO ALIAS +# flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF|ALIAD (32, 4) +#:flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm +#{ +#} +#@endif + +#TODO MACRO +# flw D,A,s 00000000 0000000f MACRO (0, 64) + +#TODO ALIAS +# fmv.q D,U 26000053 fe00707f ALIAS (0, 0) +#:fmv.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13 & op2024=0x0 +#{ +#} + + +#TODO SEE fmv.w.x +# fmv.s.x D,s f0000053 fff0707f SIMPLE (0, 0) +# :fmv.s.x fr0711,rs1 is fr0711 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 +# { +# } + +#TODO SEE fmv.x.w +# fmv.x.s d,S e0000053 fff0707f SIMPLE (0, 0) +# :fmv.x.s rd,fr1519 is fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 +# { +# } + + +#TODO ALIAS +# fneg.q D,U 26001053 fe00707f ALIAS (0, 0) +#:fneg.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13 & op2024=0x0 +#{ +#} + +#TODO SEE frcsr +# frsr d 00302073 fffff07f SIMPLE (0, 0) +# :frsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 +# { +# } + +#TODO ALIAS +# fsd CT,CN(Cc) 0000a002 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO cfr0206,csdspimm(sp) csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 +#:fsd cfr0206,csdspimm(sp) is csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 +#{ +#} + +#TODO ALIAS +# fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO 32 64 +#:fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm +#{ +#} + +#TODO MACRO +# fsd T,A,s 00000000 00000013 MACRO (0, 64) + +#TODO MACRO +# fsq T,A,s 00000000 00000014 MACRO (0, 64) + +#TODO SEE fscsr +# fssr s 00301073 fff07fff SIMPLE (0, 0) +# :fssr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3 +# { +# } + +#TODO SEE fscsr +# fssr d,s 00301073 fff0707f SIMPLE (0, 0) +# :fssr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 +# { +# } + +#@if defined(RISCV32I) +#TODO ALIAS +# fsw CT,CM(Cc) 0000e002 0000e003 DWORD|DREF|ALIAD (32, 4) +#TODO cfr0206,cswspimm(sp) cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 +#:fsw cfr0206,cswspimm(sp) is cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 +#{ +#} +#@endif + +#@if defined(RISCV32I) +#TODO ALIAS +# fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF|ALIAD (32, 4) +#:fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm +#{ +#} +#@endif + +#TODO MACRO +# fsw T,A,s 00000000 00000012 MACRO (0, 64) + + +#TODO ALIAS +# j Ca 0000a001 0000e003 BRANCH|ALIAS (0, 0) +#:j cjimm is cjimm & cop0001=0x1 & cop1315=0x5 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# jal Ca 00002001 0000e003 JSR|ALIAS (32, 0) +#:jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#TODO ALIAS +# jal a 000000ef 00000fff JSR|ALIAS (0, 0) +#:jal immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr d 00009002 0000f07f JSR|ALIAS (0, 0) +#:jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# jalr s 000000e7 fff07fff JSR|ALIAS (0, 0) +#:jalr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 & op2031=0x0 +#{ +#} + +#TODO ALIAS +# jalr o(s) 000000e7 00007fff JSR|ALIAS (0, 0) +#:jalr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr s,j 000000e7 00007fff JSR|ALIAS (0, 0) +#:jalr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr d,s 00000067 fff0707f JSR|ALIAS (0, 0) +#:jalr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op2031=0x0 +#{ +#} + +#TODO SEE jalr +# jalr d,o(s) 00000067 0000707f JSR (0, 0) +# :jalr rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 +# { +# } + +#TODO ALIAS +# jr d 00008002 0000f07f BRANCH|ALIAS (0, 0) +#:jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# jr s,j 00000067 00007fff BRANCH|ALIAS (0, 0) +#:jr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 +#{ +#} + +#TODO MACRO +# jump c,s 00000000 00000015 MACRO (0, 64) + +#TODO MACRO +# la d,B 00000000 00000000 MACRO (0, 64) + +#TODO MACRO +# la.tls.gd d,A 00000000 00000002 MACRO (0, 64) + +#TODO MACRO +# la.tls.ie d,A 00000000 00000003 MACRO (0, 64) + +#TODO MACRO +# lb d,A 00000000 00000004 MACRO (0, 64) + +#TODO MACRO +# lbu d,A 00000000 00000005 MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO ALIAS +# ld d,Cn(Cc) 00006002 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO crd,cldspimm(sp) crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3 +#:ld crd,cldspimm(sp) is crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO 64 128 +#:ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO MACRO +# ld d,A 00000000 0000000a MACRO (64, 64) +#@endif + +#TODO MACRO +# lh d,A 00000000 00000006 MACRO (0, 64) + +#TODO MACRO +# lhu d,A 00000000 00000007 MACRO (0, 64) + +#TODO ALIAS +# li d,Cv 00006001 0000e003 ALIAS (0, 0) +#TODO crd,cbigimm crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#:li crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# li d,Co 00004001 0000e003 ALIAS (0, 0) +#:li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2 +#{ +#} + +#TODO MACRO +# li d,I 00000000 00000017 MACRO (0, 64) + +#TODO MACRO +# lla d,B 00000000 00000001 MACRO (0, 64) + +#TODO ALIAS +# lui d,Cu 00006001 0000e003 ALIAS (0, 0) +#:lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# lw d,Cm(Cc) 00004002 0000e003 DWORD|DREF|ALIAD (0, 4) +#:lw crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm +#{ +#} + +#TODO ALIAS +# lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF|ALIAD (0, 4) +#:lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm +#{ +#} + +#TODO MACRO +# lw d,A 00000000 00000008 MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO MACRO +# lwu d,A 00000000 00000009 MACRO (64, 64) +#@endif + +#TODO ALIAS +# move d,CV 00008002 0000f003 ALIAS (0, 0) +#TODO crd,crs2 crd & crs2 & cop0001=0x2 & cop1315=0x4 +#:move crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# move d,s 00000013 fff0707f ALIAS (0, 0) +#:move rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0 +#{ +#} + +#TODO ALIAS +# mv d,CV 00008002 0000f003 ALIAS (0, 0) +#:mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# nop 00000001 0000ffff ALIAS (0, 0) +#:nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0 +#{ +#} + +#TODO ALIAS +# or Cs,Cw,Ct 00008c41 0000fc63 ALIAS (0, 0) +#:or cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# or Cs,Ct,Cw 00008c41 0000fc63 ALIAS (0, 0) +#:or cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# or d,s,j 00006013 0000707f ALIAS (0, 0) +#:or rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# rdcycle d c0002073 fffff07f ALIAS (0, 0) +#:rdcycle rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18000 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdcycleh d c8002073 fffff07f ALIAS (32, 0) +#:rdcycleh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19000 +#{ +#} +#@endif + +#TODO ALIAS +# rdinstret d c0202073 fffff07f ALIAS (0, 0) +#:rdinstret rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18040 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdinstreth d c8202073 fffff07f ALIAS (32, 0) +#:rdinstreth rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19040 +#{ +#} +#@endif + +#TODO ALIAS +# rdtime d c0102073 fffff07f ALIAS (0, 0) +#:rdtime rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18020 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdtimeh d c8102073 fffff07f ALIAS (32, 0) +#:rdtimeh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19020 +#{ +#} +#@endif + +#TODO MACRO +# sb t,A,s 00000000 0000000b MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO ALIAS +# sd CV,CN(Cc) 0000e002 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO crs2,csdspimm(sp) csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7 +#:sd crs2,csdspimm(sp) is csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO 64 128 +#:sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO MACRO +# sd t,A,s 00000000 0000000e MACRO (64, 64) +#@endif + +#TODO ALIAS +# seqz d,s 00103013 fff0707f ALIAS (0, 0) +#:seqz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 & op2031=0x1 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sext.w d,CU 00002001 0000f07f ALIAS (64, 0) +#TODO crd,crs1 crd & crs1 & cop0001=0x1 & cop1315=0x1 +#:sext.w crd,crs1 is crd & crs1 & cop0001=0x1 & cop1315=0x1 & cop0206=0x0 & cop1212=0x0 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# sext.w d,s 0000001b fff0707f ALIAS (64, 0) +#:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# sfence.vma 12000073 ffffffff ALIAS (0, 0) +#:sfence.vma is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2400 +#{ +#} + +#TODO ALIAS +# sfence.vma s 12000073 fff07fff ALIAS (0, 0) +#:sfence.vma rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x120 +#{ +#} + +#TODO ALIAS +# sgt d,t,s 00002033 fe00707f ALIAS (0, 0) +#:sgt rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 +#{ +#} + +#TODO ALIAS +# sgtu d,t,s 00003033 fe00707f ALIAS (0, 0) +#:sgtu rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 +#{ +#} + +#TODO ALIAS +# sgtz d,t 00002033 fe0ff07f ALIAS (0, 0) +#:sgtz rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op1519=0x0 +#{ +#} + +#TODO MACRO +# sh t,A,s 00000000 0000000c MACRO (0, 64) + +#TODO ALIAS +# sll d,CU,C> 00000002 0000e003 ALIAS (0, 0) +#:sll crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# sll d,s,> 00001013 fc00707f ALIAS (0, 0) +#:sll rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0 +#{ +#} + +#TODO ALIAS +# slli d,CU,C> 00000002 0000e003 ALIAS (0, 0) +#:slli crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sllw d,s,< 0000101b fe00707f ALIAS (64, 0) +#:sllw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# slt d,s,j 00002013 0000707f ALIAS (0, 0) +#:slt rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2 +#{ +#} + +#TODO ALIAS +# sltu d,s,j 00003013 0000707f ALIAS (0, 0) +#:sltu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 +#{ +#} + +#TODO ALIAS +# sltz d,s 00002033 fff0707f ALIAS (0, 0) +#:sltz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# snez d,t 00003033 fe0ff07f ALIAS (0, 0) +#:snez rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# sra Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) +#:sra cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +#{ +#} + +#TODO ALIAS +# sra d,s,> 40005013 fc00707f ALIAS (0, 0) +#:sra rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10 +#{ +#} + +#TODO ALIAS +# srai Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) +#:srai cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sraw d,s,< 4000501b fe00707f ALIAS (64, 0) +#:sraw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20 +#{ +#} +#@endif + + +#TODO ALIAS +# srl Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) +#:srl cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +#{ +#} + +#TODO ALIAS +# srl d,s,> 00005013 fc00707f ALIAS (0, 0) +#:srl rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0 +#{ +#} + +#TODO ALIAS +# srli Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) +#:srli cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# srlw d,s,< 0000501b fe00707f ALIAS (64, 0) +#:srlw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# sub Cs,Cw,Ct 00008c01 0000fc63 ALIAS (0, 0) +#:sub cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# subw Cs,Cw,Ct 00009c01 0000fc63 ALIAS (64, 0) +#:subw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7 +#{ +#} +#@endif + +#TODO ALIAS +# sw CV,CM(Cc) 0000c002 0000e003 DWORD|DREF|ALIAD (0, 4) +#:sw crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm +#{ +#} + +#TODO ALIAS +# sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF|ALIAD (0, 4) +#:sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm +#{ +#} + +#TODO MACRO +# sw t,A,s 00000000 0000000d MACRO (0, 64) + +#TODO MACRO +# tail c 00030000 00000015 MACRO (0, 64) + +#TODO ALIAS +# unimp 00000000 0000ffff ALIAS (0, 0) +#:unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0 +#{ +#} + + +#TODO ALIAS +# xor Cs,Cw,Ct 00008c21 0000fc63 ALIAS (0, 0) +#:xor cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# xor Cs,Ct,Cw 00008c21 0000fc63 ALIAS (0, 0) +#:xor cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# xor d,s,j 00004013 0000707f ALIAS (0, 0) +#:xor rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 +#{ +#} + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs new file mode 100644 index 0000000000..25fca48648 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs @@ -0,0 +1,138 @@ + + + + + + RISC-V 64 little base + + + + + RISC-V 64 little base compressed + + + + + RISC-V 64 little general purpose + + + + + RISC-V 64 little general purpose compressed + + + + + RISC-V 32 little default + + + + + RISC-V 32 little base + + + + + RISC-V 32 little base compressed + + + + + RISC-V 32 little base compressed + + + + + RISC-V 32 little general purpose + + + + + RISC-V 32 little general purpose compressed + + + + + RISC-V 32 little default + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec new file mode 100644 index 0000000000..3b083a32a0 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.lp64.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 8 +@define XLEN2 16 +@define FLEN 0 + +@define ADDRSIZE "64" +@define FPSIZE "" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec new file mode 100644 index 0000000000..a67d8e65bd --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 8 +@define XLEN2 16 +@define FLEN 8 + +@define ADDRSIZE "64" +@define FPSIZE "64" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec b/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec new file mode 100644 index 0000000000..731d749fa4 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.lp64f.slaspec @@ -0,0 +1,12 @@ +define endian=little; + +@define XLEN 8 +@define XLEN2 16 +@define FLEN 4 + +@define ADDRSIZE "64" +@define FPSIZE "32" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.opinion b/Ghidra/Processors/RISCV/data/languages/riscv.opinion new file mode 100644 index 0000000000..08eefb35d3 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.opinion @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc new file mode 100644 index 0000000000..0e2f2974f5 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc @@ -0,0 +1,63 @@ +# RISC-V Privileged Instructions + +# Trap-Return + + +# dret 7b200073 ffffffff SIMPLE (0, 0) +:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640 +{ +} + +# hret 20200073 ffffffff SIMPLE (0, 0) +:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040 +{ +} + + +# mret 30200073 ffffffff SIMPLE (0, 0) +:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040 +{ +} + +# sret 10200073 ffffffff SIMPLE (0, 0) +:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040 +{ +} + + +# uret 00200073 ffffffff SIMPLE (0, 0) +:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40 +{ +} + + +# Interrupt-Management + +# wfi 10500073 ffffffff SIMPLE (0, 0) +:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0 +{ +} + + +# Supervisor Memory-Management + +# sfence.vm 10400073 ffffffff SIMPLE (0, 0) +:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080 +{ +} + +# sfence.vm s 10400073 fff07fff SIMPLE (0, 0) +:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104 +{ +} + +# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0) +:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9 +{ +} + + + + +# Hypervisor Memory-Management +#TODO \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc new file mode 100644 index 0000000000..a8ee148fae --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc @@ -0,0 +1,793 @@ + +define alignment=2; + +define space ram type=ram_space size=$(XLEN) default; +define space register type=register_space size=4; + + +# A - Atomic instructions +# B - Bit manipulation instructions +# C - Compressed instructions +# D - Double-precision floating-point instructions +# E - Embedded applications, resource-constrained subset +# F - Single-precision floating-point instructions +# G - General (I + M + A + F + D) +# I - Integer base instructions +# J - Dynamically translated languages +# L - Decimal floating point instructions +# M - Integer multiplication and division instructions +# N - User-level interrupt instructions +# P - Packed-SIMD instructions +# Q - Quad-precision floating-point instructions +# T - Transactional Memory instructions +# V - Vector operations instructions +# RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N +define register offset=0x1020 size=8 extensions; +define context extensions + RVI=(0,0) + RVM=(1,1) + RVA=(2,2) + RVF=(3,3) + RVD=(4,4) + RVG=(0,4) + RVQ=(5,5) + RVL=(6,6) + RVC=(7,7) + RVB=(8,8) + RVJ=(9,9) + RVT=(10,10) + RVP=(11,11) + RVV=(12,12) + RVN=(13,13) + RV128=(61,61) + RV64=(62,62) + RV32=(63,63) +; + +define register offset=0x1000 size=$(XLEN) [ pc ]; + + +# 08-31 reserved +# 05-07 frm +# 000 - RNE - round to nearest, ties to even +# 001 - RTZ - round towards zero +# 010 - RDN - round down (towards -inf) +# 011 - RUP - round up (towards +inf) +# 100 - RMM - round to nearest, ties to max magnitude +# 101 - invalid +# 110 - invalid +# 111 - DYN - in rm field, selects dynamic rounding mode +# in rounding mode register, invalid +# 04 NV - invalid operation +# 03 DZ - divide by zero +# 02 OF - overflow +# 01 UF - underflow +# 00 NX - inexact +#define register offset=0x1008 size=4 [ fcsr ]; + +#TODO FIXME +#TODO This is really broken +#NOTE This is stolen from ppc_common, so it has something similar +define register offset=0x1010 size=$(XLEN) [ RESERVE_ADDRESS ]; +define register offset=0x1018 size=1 [ RESERVE ]; +define register offset=0x101C size=1 [ RESERVE_LENGTH ]; +#TODO FIXME + + +# x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 +# z ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 +# x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 +# a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 +define register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2 + s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 + s8 s9 s10 s11 t3 t4 t5 t6 ]; +@if FPSIZE != "" +define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 + fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; +@endif + +define token instr (32) + op0001=(0,1) + op0204=(2,4) + op0506=(5,6) + op0707=(7,7) + op0711=(7,11) + r0711=(7,11) + fr0711=(7,11) + op0811=(8,11) + op1214=(12,14) + funct3=(12,14) + op1219=(12,19) + op1231=(12,31) + sop1231=(12,31) signed + op1519=(15,19) + r1519=(15,19) + fr1519=(15,19) + op1527=(15,27) + op1531=(15,31) + op2020=(20,20) + succ=(20,23) + op2024=(20,24) + r2024=(20,24) + fr2024=(20,24) + csr_0=(20,27) + csr_1=(20,27) + csr_2=(20,27) + csr_3=(20,27) + csr_4=(20,27) + csr_50=(20,26) + csr_58=(20,25) + csr_5C=(20,25) + csr_60=(20,26) + csr_68=(20,25) + csr_6C=(20,25) + csr_70=(20,26) + csr_78=(20,24) + csr_7A=(20,23) + csr_7B=(20,23) + csr_7C=(20,25) + csr_8=(20,27) + csr_90=(20,26) + csr_98=(20,25) + csr_9C=(20,25) + csr_A0=(20,26) + csr_A8=(20,25) + csr_AC=(20,25) + csr_B0=(20,26) + csr_B8=(20,25) + csr_BC=(20,25) + csr_C0=(20,26) + csr_C8=(20,25) + csr_CC=(20,25) + csr_D0=(20,26) + csr_D8=(20,25) + csr_DC=(20,25) + csr_E0=(20,26) + csr_E8=(20,25) + csr_EC=(20,25) + csr_F0=(20,26) + csr_F8=(20,25) + csr_FC=(20,25) + op2031=(20,31) + sop2031=(20,31) signed + op2130=(21,30) + op2427=(24,27) + pred=(24,27) + op2525=(25,25) + op2526=(25,26) + op2527=(25,27) + op2530=(25,30) + op2531=(25,31) + sop2531=(25,31) signed + funct7=(25,31) + op2627=(26,27) + op2631=(26,31) + op2731=(27,31) + funct5=(27,31) + op2727=(27,27) + r2731=(27,31) + fr2731=(27,31) + op2829=(28,29) + fm=(28,31) + op3031=(30,31) + sop3131=(31,31) signed +; + +define token cinstr (16) + cop0001=(0,1) + cop0202=(2,2) + cop0203=(2,3) + cop0204=(2,4) + cr0204s=(2,4) + cfr0204s=(2,4) + cop0205=(2,5) + cop0206=(2,6) + cr0206=(2,6) + cfr0206=(2,6) + cop0212=(2,12) + cop0304=(3,4) + cop0305=(3,5) + cop0406=(4,6) + cop0505=(5,5) + cop0506=(5,6) + cop0512=(5,12) + cop0606=(6,6) + cop0707=(7,7) + cop0708=(7,8) + cop0709=(7,9) + cr0709s=(7,9) + cd0709s=(7,9) + cfr0709s=(7,9) + cop0710=(7,10) + cop0711=(7,11) + cr0711=(7,11) + cd0711=(7,11) + cfr0711=(7,11) + cop0712=(7,12) + cop0808=(8,8) + cop0910=(9,10) + cop0912=(9,12) + cop1010=(10,10) + cop1011=(10,11) + cop1012=(10,12) + cop1111=(11,11) + cop1112=(11,12) + cop1212=(12,12) + scop1212=(12,12) signed + cop1315=(13,15) +; + + +attach variables [ r0711 r1519 r2024 r2731 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cr0206 cr0711 cd0711 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cr0204s cr0709s cd0709s ] + [ s0 s1 a0 a1 a2 a3 a4 a5 ]; + + +@if FPSIZE != "" +attach variables [ fr0711 fr1519 fr2024 fr2731 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0206 cfr0711 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0204s cfr0709s ] + [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ]; +@endif + + +#TODO this approach is probably incorrect +define register offset=0x90000000 size=$(XLEN) [ ustatus ]; +define register offset=0x90000010 size=$(XLEN) [ fflags ]; +define register offset=0x90000020 size=$(XLEN) [ frm ]; +define register offset=0x90000030 size=$(XLEN) [ fcsr ]; +define register offset=0x90000040 size=$(XLEN) [ uie ]; +define register offset=0x90000050 size=$(XLEN) [ utvec ]; +define register offset=0x90000400 size=$(XLEN) [ uscratch ]; +define register offset=0x90000410 size=$(XLEN) [ uepc ]; +define register offset=0x90000420 size=$(XLEN) [ ucause ]; +define register offset=0x90000430 size=$(XLEN) [ utval ]; +define register offset=0x90000440 size=$(XLEN) [ uip ]; +define register offset=0x90001000 size=$(XLEN) [ sstatus ]; +define register offset=0x90001020 size=$(XLEN) [ sedeleg ]; +define register offset=0x90001030 size=$(XLEN) [ sideleg ]; +define register offset=0x90001040 size=$(XLEN) [ sie ]; +define register offset=0x90001050 size=$(XLEN) [ stvec ]; +define register offset=0x90001060 size=$(XLEN) [ scounteren ]; +define register offset=0x90001400 size=$(XLEN) [ sscratch ]; +define register offset=0x90001410 size=$(XLEN) [ sepc ]; +define register offset=0x90001420 size=$(XLEN) [ scause ]; +define register offset=0x90001430 size=$(XLEN) [ stval ]; +define register offset=0x90001440 size=$(XLEN) [ sip ]; +define register offset=0x90001800 size=$(XLEN) [ satp ]; +define register offset=0x90002000 size=$(XLEN) [ vsstatus ]; +define register offset=0x90002040 size=$(XLEN) [ vsie ]; +define register offset=0x90002050 size=$(XLEN) [ vstvec ]; +define register offset=0x90002400 size=$(XLEN) [ vsscratch ]; +define register offset=0x90002410 size=$(XLEN) [ vsepc ]; +define register offset=0x90002420 size=$(XLEN) [ vscause ]; +define register offset=0x90002430 size=$(XLEN) [ vstval ]; +define register offset=0x90002440 size=$(XLEN) [ vsip ]; +define register offset=0x90002800 size=$(XLEN) [ vsatp ]; +define register offset=0x90003000 size=$(XLEN) [ mstatus ]; +define register offset=0x90003010 size=$(XLEN) [ misa ]; +define register offset=0x90003020 size=$(XLEN) [ medeleg ]; +define register offset=0x90003030 size=$(XLEN) [ mideleg ]; +define register offset=0x90003040 size=$(XLEN) [ mie ]; +define register offset=0x90003050 size=$(XLEN) [ mtvec ]; +define register offset=0x90003060 size=$(XLEN) [ mcounteren ]; +define register offset=0x90003100 size=$(XLEN) [ mstatush ]; +define register offset=0x90003200 size=$(XLEN) [ mucounteren ]; +define register offset=0x90003210 size=$(XLEN) [ mscounteren ]; +define register offset=0x90003220 size=$(XLEN) [ mhcounteren ]; +define register offset=0x90003400 size=$(XLEN) [ mscratch ]; +define register offset=0x90003410 size=$(XLEN) [ mepc ]; +define register offset=0x90003420 size=$(XLEN) [ mcause ]; +define register offset=0x90003430 size=$(XLEN) [ mtval ]; +define register offset=0x90003440 size=$(XLEN) [ mip ]; +define register offset=0x90003800 size=$(XLEN) [ mbase ]; +define register offset=0x90003810 size=$(XLEN) [ mbound ]; +define register offset=0x90003820 size=$(XLEN) [ mibase ]; +define register offset=0x90003830 size=$(XLEN) [ mibound ]; +define register offset=0x90003840 size=$(XLEN) [ mdbase ]; +define register offset=0x90003850 size=$(XLEN) [ mdbound ]; +define register offset=0x90003a00 size=$(XLEN) [ pmpcfg0 ]; +define register offset=0x90003a10 size=$(XLEN) [ pmpcfg1 ]; +define register offset=0x90003a20 size=$(XLEN) [ pmpcfg2 ]; +define register offset=0x90003a30 size=$(XLEN) [ pmpcfg3 ]; +define register offset=0x90003b00 size=$(XLEN) [ pmpaddr0 ]; +define register offset=0x90003b10 size=$(XLEN) [ pmpaddr1 ]; +define register offset=0x90003b20 size=$(XLEN) [ pmpaddr2 ]; +define register offset=0x90003b30 size=$(XLEN) [ pmpaddr3 ]; +define register offset=0x90003b40 size=$(XLEN) [ pmpaddr4 ]; +define register offset=0x90003b50 size=$(XLEN) [ pmpaddr5 ]; +define register offset=0x90003b60 size=$(XLEN) [ pmpaddr6 ]; +define register offset=0x90003b70 size=$(XLEN) [ pmpaddr7 ]; +define register offset=0x90003b80 size=$(XLEN) [ pmpaddr8 ]; +define register offset=0x90003b90 size=$(XLEN) [ pmpaddr9 ]; +define register offset=0x90003ba0 size=$(XLEN) [ pmpaddr10 ]; +define register offset=0x90003bb0 size=$(XLEN) [ pmpaddr11 ]; +define register offset=0x90003bc0 size=$(XLEN) [ pmpaddr12 ]; +define register offset=0x90003bd0 size=$(XLEN) [ pmpaddr13 ]; +define register offset=0x90003be0 size=$(XLEN) [ pmpaddr14 ]; +define register offset=0x90003bf0 size=$(XLEN) [ pmpaddr15 ]; +define register offset=0x90006000 size=$(XLEN) [ hstatus ]; +define register offset=0x90006020 size=$(XLEN) [ hedeleg ]; +define register offset=0x90006030 size=$(XLEN) [ hideleg ]; +define register offset=0x90006060 size=$(XLEN) [ hcounteren ]; +define register offset=0x90006800 size=$(XLEN) [ hgatp ]; +define register offset=0x90007a00 size=$(XLEN) [ tselect ]; +define register offset=0x90007a10 size=$(XLEN) [ tdata1 ]; +define register offset=0x90007a20 size=$(XLEN) [ tdata2 ]; +define register offset=0x90007a30 size=$(XLEN) [ tdata3 ]; +define register offset=0x90007b00 size=$(XLEN) [ dcsr ]; +define register offset=0x90007b10 size=$(XLEN) [ dpc ]; +define register offset=0x90007b20 size=$(XLEN) [ dscratch0 ]; +define register offset=0x90007b30 size=$(XLEN) [ dscratch1 ]; +define register offset=0x9000b000 size=$(XLEN) [ mcycle ]; +define register offset=0x9000b020 size=$(XLEN) [ minstret ]; +define register offset=0x9000b030 size=$(XLEN) [ mhpmcounter3 ]; +define register offset=0x9000b040 size=$(XLEN) [ mhpmcounter4 ]; +define register offset=0x9000b050 size=$(XLEN) [ mhpmcounter5 ]; +define register offset=0x9000b060 size=$(XLEN) [ mhpmcounter6 ]; +define register offset=0x9000b070 size=$(XLEN) [ mhpmcounter7 ]; +define register offset=0x9000b080 size=$(XLEN) [ mhpmcounter8 ]; +define register offset=0x9000b090 size=$(XLEN) [ mhpmcounter9 ]; +define register offset=0x9000b0a0 size=$(XLEN) [ mhpmcounter10 ]; +define register offset=0x9000b0b0 size=$(XLEN) [ mhpmcounter11 ]; +define register offset=0x9000b0c0 size=$(XLEN) [ mhpmcounter12 ]; +define register offset=0x9000b0d0 size=$(XLEN) [ mhpmcounter13 ]; +define register offset=0x9000b0e0 size=$(XLEN) [ mhpmcounter14 ]; +define register offset=0x9000b0f0 size=$(XLEN) [ mhpmcounter15 ]; +define register offset=0x9000b100 size=$(XLEN) [ mhpmcounter16 ]; +define register offset=0x9000b110 size=$(XLEN) [ mhpmcounter17 ]; +define register offset=0x9000b120 size=$(XLEN) [ mhpmcounter18 ]; +define register offset=0x9000b130 size=$(XLEN) [ mhpmcounter19 ]; +define register offset=0x9000b140 size=$(XLEN) [ mhpmcounter20 ]; +define register offset=0x9000b150 size=$(XLEN) [ mhpmcounter21 ]; +define register offset=0x9000b160 size=$(XLEN) [ mhpmcounter22 ]; +define register offset=0x9000b170 size=$(XLEN) [ mhpmcounter23 ]; +define register offset=0x9000b180 size=$(XLEN) [ mhpmcounter24 ]; +define register offset=0x9000b190 size=$(XLEN) [ mhpmcounter25 ]; +define register offset=0x9000b1a0 size=$(XLEN) [ mhpmcounter26 ]; +define register offset=0x9000b1b0 size=$(XLEN) [ mhpmcounter27 ]; +define register offset=0x9000b1c0 size=$(XLEN) [ mhpmcounter28 ]; +define register offset=0x9000b1d0 size=$(XLEN) [ mhpmcounter29 ]; +define register offset=0x9000b1e0 size=$(XLEN) [ mhpmcounter30 ]; +define register offset=0x9000b1f0 size=$(XLEN) [ mhpmcounter31 ]; +define register offset=0x9000b200 size=$(XLEN) [ mcountinhibit ]; +define register offset=0x9000b230 size=$(XLEN) [ mhpmevent3 ]; +define register offset=0x9000b240 size=$(XLEN) [ mhpmevent4 ]; +define register offset=0x9000b250 size=$(XLEN) [ mhpmevent5 ]; +define register offset=0x9000b260 size=$(XLEN) [ mhpmevent6 ]; +define register offset=0x9000b270 size=$(XLEN) [ mhpmevent7 ]; +define register offset=0x9000b280 size=$(XLEN) [ mhpmevent8 ]; +define register offset=0x9000b290 size=$(XLEN) [ mhpmevent9 ]; +define register offset=0x9000b2a0 size=$(XLEN) [ mhpmevent10 ]; +define register offset=0x9000b2b0 size=$(XLEN) [ mhpmevent11 ]; +define register offset=0x9000b2c0 size=$(XLEN) [ mhpmevent12 ]; +define register offset=0x9000b2d0 size=$(XLEN) [ mhpmevent13 ]; +define register offset=0x9000b2e0 size=$(XLEN) [ mhpmevent14 ]; +define register offset=0x9000b2f0 size=$(XLEN) [ mhpmevent15 ]; +define register offset=0x9000b300 size=$(XLEN) [ mhpmevent16 ]; +define register offset=0x9000b310 size=$(XLEN) [ mhpmevent17 ]; +define register offset=0x9000b320 size=$(XLEN) [ mhpmevent18 ]; +define register offset=0x9000b330 size=$(XLEN) [ mhpmevent19 ]; +define register offset=0x9000b340 size=$(XLEN) [ mhpmevent20 ]; +define register offset=0x9000b350 size=$(XLEN) [ mhpmevent21 ]; +define register offset=0x9000b360 size=$(XLEN) [ mhpmevent22 ]; +define register offset=0x9000b370 size=$(XLEN) [ mhpmevent23 ]; +define register offset=0x9000b380 size=$(XLEN) [ mhpmevent24 ]; +define register offset=0x9000b390 size=$(XLEN) [ mhpmevent25 ]; +define register offset=0x9000b3a0 size=$(XLEN) [ mhpmevent26 ]; +define register offset=0x9000b3b0 size=$(XLEN) [ mhpmevent27 ]; +define register offset=0x9000b3c0 size=$(XLEN) [ mhpmevent28 ]; +define register offset=0x9000b3d0 size=$(XLEN) [ mhpmevent29 ]; +define register offset=0x9000b3e0 size=$(XLEN) [ mhpmevent30 ]; +define register offset=0x9000b3f0 size=$(XLEN) [ mhpmevent31 ]; +define register offset=0x9000b800 size=$(XLEN) [ mcycleh ]; +define register offset=0x9000b820 size=$(XLEN) [ minstreth ]; +define register offset=0x9000b830 size=$(XLEN) [ mhpmcounter3h ]; +define register offset=0x9000b840 size=$(XLEN) [ mhpmcounter4h ]; +define register offset=0x9000b850 size=$(XLEN) [ mhpmcounter5h ]; +define register offset=0x9000b860 size=$(XLEN) [ mhpmcounter6h ]; +define register offset=0x9000b870 size=$(XLEN) [ mhpmcounter7h ]; +define register offset=0x9000b880 size=$(XLEN) [ mhpmcounter8h ]; +define register offset=0x9000b890 size=$(XLEN) [ mhpmcounter9h ]; +define register offset=0x9000b8a0 size=$(XLEN) [ mhpmcounter10h ]; +define register offset=0x9000b8b0 size=$(XLEN) [ mhpmcounter11h ]; +define register offset=0x9000b8c0 size=$(XLEN) [ mhpmcounter12h ]; +define register offset=0x9000b8d0 size=$(XLEN) [ mhpmcounter13h ]; +define register offset=0x9000b8e0 size=$(XLEN) [ mhpmcounter14h ]; +define register offset=0x9000b8f0 size=$(XLEN) [ mhpmcounter15h ]; +define register offset=0x9000b900 size=$(XLEN) [ mhpmcounter16h ]; +define register offset=0x9000b910 size=$(XLEN) [ mhpmcounter17h ]; +define register offset=0x9000b920 size=$(XLEN) [ mhpmcounter18h ]; +define register offset=0x9000b930 size=$(XLEN) [ mhpmcounter19h ]; +define register offset=0x9000b940 size=$(XLEN) [ mhpmcounter20h ]; +define register offset=0x9000b950 size=$(XLEN) [ mhpmcounter21h ]; +define register offset=0x9000b960 size=$(XLEN) [ mhpmcounter22h ]; +define register offset=0x9000b970 size=$(XLEN) [ mhpmcounter23h ]; +define register offset=0x9000b980 size=$(XLEN) [ mhpmcounter24h ]; +define register offset=0x9000b990 size=$(XLEN) [ mhpmcounter25h ]; +define register offset=0x9000b9a0 size=$(XLEN) [ mhpmcounter26h ]; +define register offset=0x9000b9b0 size=$(XLEN) [ mhpmcounter27h ]; +define register offset=0x9000b9c0 size=$(XLEN) [ mhpmcounter28h ]; +define register offset=0x9000b9d0 size=$(XLEN) [ mhpmcounter29h ]; +define register offset=0x9000b9e0 size=$(XLEN) [ mhpmcounter30h ]; +define register offset=0x9000b9f0 size=$(XLEN) [ mhpmcounter31h ]; +define register offset=0x9000c000 size=$(XLEN) [ cycle ]; +define register offset=0x9000c010 size=$(XLEN) [ time ]; +define register offset=0x9000c020 size=$(XLEN) [ instret ]; +define register offset=0x9000c030 size=$(XLEN) [ hpmcounter3 ]; +define register offset=0x9000c040 size=$(XLEN) [ hpmcounter4 ]; +define register offset=0x9000c050 size=$(XLEN) [ hpmcounter5 ]; +define register offset=0x9000c060 size=$(XLEN) [ hpmcounter6 ]; +define register offset=0x9000c070 size=$(XLEN) [ hpmcounter7 ]; +define register offset=0x9000c080 size=$(XLEN) [ hpmcounter8 ]; +define register offset=0x9000c090 size=$(XLEN) [ hpmcounter9 ]; +define register offset=0x9000c0a0 size=$(XLEN) [ hpmcounter10 ]; +define register offset=0x9000c0b0 size=$(XLEN) [ hpmcounter11 ]; +define register offset=0x9000c0c0 size=$(XLEN) [ hpmcounter12 ]; +define register offset=0x9000c0d0 size=$(XLEN) [ hpmcounter13 ]; +define register offset=0x9000c0e0 size=$(XLEN) [ hpmcounter14 ]; +define register offset=0x9000c0f0 size=$(XLEN) [ hpmcounter15 ]; +define register offset=0x9000c100 size=$(XLEN) [ hpmcounter16 ]; +define register offset=0x9000c110 size=$(XLEN) [ hpmcounter17 ]; +define register offset=0x9000c120 size=$(XLEN) [ hpmcounter18 ]; +define register offset=0x9000c130 size=$(XLEN) [ hpmcounter19 ]; +define register offset=0x9000c140 size=$(XLEN) [ hpmcounter20 ]; +define register offset=0x9000c150 size=$(XLEN) [ hpmcounter21 ]; +define register offset=0x9000c160 size=$(XLEN) [ hpmcounter22 ]; +define register offset=0x9000c170 size=$(XLEN) [ hpmcounter23 ]; +define register offset=0x9000c180 size=$(XLEN) [ hpmcounter24 ]; +define register offset=0x9000c190 size=$(XLEN) [ hpmcounter25 ]; +define register offset=0x9000c1a0 size=$(XLEN) [ hpmcounter26 ]; +define register offset=0x9000c1b0 size=$(XLEN) [ hpmcounter27 ]; +define register offset=0x9000c1c0 size=$(XLEN) [ hpmcounter28 ]; +define register offset=0x9000c1d0 size=$(XLEN) [ hpmcounter29 ]; +define register offset=0x9000c1e0 size=$(XLEN) [ hpmcounter30 ]; +define register offset=0x9000c1f0 size=$(XLEN) [ hpmcounter31 ]; +define register offset=0x9000c800 size=$(XLEN) [ cycleh ]; +define register offset=0x9000c810 size=$(XLEN) [ timeh ]; +define register offset=0x9000c820 size=$(XLEN) [ instreth ]; +define register offset=0x9000c830 size=$(XLEN) [ hpmcounter3h ]; +define register offset=0x9000c840 size=$(XLEN) [ hpmcounter4h ]; +define register offset=0x9000c850 size=$(XLEN) [ hpmcounter5h ]; +define register offset=0x9000c860 size=$(XLEN) [ hpmcounter6h ]; +define register offset=0x9000c870 size=$(XLEN) [ hpmcounter7h ]; +define register offset=0x9000c880 size=$(XLEN) [ hpmcounter8h ]; +define register offset=0x9000c890 size=$(XLEN) [ hpmcounter9h ]; +define register offset=0x9000c8a0 size=$(XLEN) [ hpmcounter10h ]; +define register offset=0x9000c8b0 size=$(XLEN) [ hpmcounter11h ]; +define register offset=0x9000c8c0 size=$(XLEN) [ hpmcounter12h ]; +define register offset=0x9000c8d0 size=$(XLEN) [ hpmcounter13h ]; +define register offset=0x9000c8e0 size=$(XLEN) [ hpmcounter14h ]; +define register offset=0x9000c8f0 size=$(XLEN) [ hpmcounter15h ]; +define register offset=0x9000c900 size=$(XLEN) [ hpmcounter16h ]; +define register offset=0x9000c910 size=$(XLEN) [ hpmcounter17h ]; +define register offset=0x9000c920 size=$(XLEN) [ hpmcounter18h ]; +define register offset=0x9000c930 size=$(XLEN) [ hpmcounter19h ]; +define register offset=0x9000c940 size=$(XLEN) [ hpmcounter20h ]; +define register offset=0x9000c950 size=$(XLEN) [ hpmcounter21h ]; +define register offset=0x9000c960 size=$(XLEN) [ hpmcounter22h ]; +define register offset=0x9000c970 size=$(XLEN) [ hpmcounter23h ]; +define register offset=0x9000c980 size=$(XLEN) [ hpmcounter24h ]; +define register offset=0x9000c990 size=$(XLEN) [ hpmcounter25h ]; +define register offset=0x9000c9a0 size=$(XLEN) [ hpmcounter26h ]; +define register offset=0x9000c9b0 size=$(XLEN) [ hpmcounter27h ]; +define register offset=0x9000c9c0 size=$(XLEN) [ hpmcounter28h ]; +define register offset=0x9000c9d0 size=$(XLEN) [ hpmcounter29h ]; +define register offset=0x9000c9e0 size=$(XLEN) [ hpmcounter30h ]; +define register offset=0x9000c9f0 size=$(XLEN) [ hpmcounter31h ]; +define register offset=0x9000f110 size=$(XLEN) [ mvendorid ]; +define register offset=0x9000f120 size=$(XLEN) [ marchid ]; +define register offset=0x9000f130 size=$(XLEN) [ mimpid ]; +define register offset=0x9000f140 size=$(XLEN) [ mhartid ]; + + +attach variables [ csr_0 ] + [ ustatus fflags frm fcsr uie utvec _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + uscratch uepc ucause utval uip _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_1 ] + [ sstatus _ sedeleg sideleg sie stvec scounteren _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + sscratch sepc scause stval sip _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + satp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_2 ] + [ vsstatus _ _ _ vsie vstvec _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + vsscratch vsepc vscause vstval vsip _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + vsatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_3 ] + [ mstatus misa medeleg mideleg mie mtvec mcounteren _ _ _ _ _ _ _ _ _ + mstatush _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + mscratch mepc mcause mtval mip _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 _ _ _ _ _ _ _ _ _ _ _ _ + pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_4 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_50 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_58 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_5C ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_60 ] + [ hstatus _ hedeleg hideleg _ _ hcounteren _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_68 ] + [ hgatp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_6C ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_70 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_78 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_7A ] + [ tselect tdata1 tdata2 tdata3 _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_7B ] + [ dcsr dpc dscratch0 dscratch1 _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_7C ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_90 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_98 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_9C ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_A0 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_A8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_AC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_B0 ] + [ mcycle _ minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15 + mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31 + mcountinhibit _ _ mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 + mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_B8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_BC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_C0 ] + [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15 + hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_C8 ] + [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h + hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_CC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_D0 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_D8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_DC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_E0 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_E8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_EC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_F0 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ mvendorid marchid mimpid mhartid _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_F8 ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ csr_FC ] + [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc new file mode 100644 index 0000000000..a75be012b9 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc @@ -0,0 +1,134 @@ +# RV32A Standard Extension + +# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4) +:amoadd.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp + tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4) +:amoand.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp & tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4) +:amomax.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 s<= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4) +:amomaxu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 <= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4) +:amomin.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 s>= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4) +:amominu.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 >= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4) +:amoor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp | tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4) +:amoswap.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + *[ram]:4 tmprs1 = tmprs2; +} + + +# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4) +:amoxor.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp ^ tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# lr.w d,0(s) 1000202f fff0707f DWORD|DREF (0, 4) +:lr.w^aqrl rd,(rs1) is RV32 & RVA & rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl +{ + RESERVE_ADDRESS = rs1; + RESERVE = 1; + RESERVE_LENGTH = 4; + assignW(rd, *[ram]:4 rs1); +} + + +# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4) +:sc.w^aqrl rd,rs2W,(rs1) is RV32 & RVA & rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl +{ + local tmprs2 = rs2W; + local tmprs1 = rs1; + rd = 1; + if (RESERVE == 0) goto inst_next; + if (RESERVE_ADDRESS != rs1) goto inst_next; + if (RESERVE_LENGTH != 8) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; + rd = 0; + RESERVE_ADDRESS = 0; + RESERVE = 0; + RESERVE_LENGTH = 0; +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc new file mode 100644 index 0000000000..39bd5febb2 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc @@ -0,0 +1,335 @@ +# RV32D Standard Extension + +@if FPSIZE == "64" + +# fadd.d D,S,T 02007053 fe00707f SIMPLE (0, 0) +:fadd.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x1 +{ + frd = frs1D f+ frs2D; +} + + +# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0) +:fadd.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1 +{ + frd = frs1D f+ frs2D; +} + + +# fclass.d d,S e2001053 fff0707f SIMPLE (0, 0) +:fclass.d rd,frs1D is RV32 & RVD & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + +# fcvt.d.s D,S 42000053 fff0707f SIMPLE (0, 0) +:fcvt.d.s frd,frs1S is RV32 & RVD & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0 +{ + local tmp:8 = float2float(frs1S); + frd = tmp; +} + + +# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0) +:fcvt.d.w frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0 +{ + local tmp:8 = int2float(rs1W); + frd = tmp; +} + + +# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0) +:fcvt.d.wu frd,rs1W is RV32 & RVD & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1 +{ + #ATTN unsigned can be an issue here + local u32:$(XLEN2) = zext(rs1W); + local tmp:8 = int2float(u32); + frd = tmp; +} + + +# fcvt.s.d D,S 40107053 fff0707f SIMPLE (0, 0) +:fcvt.s.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x1 +{ + local tmp:4 = float2float(frs1D); + frd = zext(tmp); +} + + +# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0) +:fcvt.s.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1 +{ + local tmp:4 = float2float(frs1D); + frd = zext(tmp); +} + + +# fcvt.w.d d,S c2007053 fff0707f SIMPLE (0, 0) +:fcvt.w.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x0 +{ + rdW = trunc(frs1D); +} + + +# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0) +:fcvt.w.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0 +{ + rdW = trunc(frs1D); +} + + +# fcvt.wu.d d,S c2107053 fff0707f SIMPLE (0, 0) +:fcvt.wu.d rdW,frs1D is RV32 & RVD & frs1D & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1D); +} + + +# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1D); +} + + +# fdiv.d D,S,T 1a007053 fe00707f SIMPLE (0, 0) +:fdiv.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xd +{ + frd = frs1D f/ frs2D; +} + + +# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0) +:fdiv.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd +{ + frd = frs1D f/ frs2D; +} + + +# feq.d d,S,T a2002053 fe00707f SIMPLE (0, 0) +:feq.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51 +{ + rd = zext(frs1D f== frs2D); +} + + +# fld D,o(s) 00003007 0000707f QWORD|DREF (0, 8) +:fld frd,immI(rs1) is RV32 & RVD & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3 +{ + local ea:$(XLEN) = immI + rs1; + frd = *[ram]:$(DFLEN) ea; +} + + +# fle.d d,S,T a2000053 fe00707f SIMPLE (0, 0) +:fle.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51 +{ + rd = zext(frs1D f<= frs2D); +} + + +# flt.d d,S,T a2001053 fe00707f SIMPLE (0, 0) +:flt.d rd,frs1D,frs2D is RV32 & RVD & frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51 +{ + rd = zext(frs1D f< frs2D); +} +#endif + + +# fmadd.d D,S,T,R 02007043 0600707f SIMPLE (0, 0) +:fmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f+ frs3D; +} + + +# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0) +:fmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f+ frs3D; +} + + +# fmax.d D,S,T 2a001053 fe00707f SIMPLE (0, 0) +:fmax.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15 +{ + #TODO redo this + local tmpfrs1 = frs1D; + local tmpfrs2 = frs2D; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f> tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + + +# fmin.d D,S,T 2a000053 fe00707f SIMPLE (0, 0) +:fmin.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15 +{ + #TODO redo this + local tmpfrs1 = frs1D; + local tmpfrs2 = frs2D; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + + +# fmsub.d D,S,T,R 02007047 0600707f SIMPLE (0, 0) +:fmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f- frs3D; +} + + +# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0) +:fmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f- frs3D; +} + + +# fmul.d D,S,T 12007053 fe00707f SIMPLE (0, 0) +:fmul.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x9 +{ + frd = frs1D f* frs2D; +} + + +# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0) +:fmul.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9 +{ + frd = frs1D f* frs2D; +} + + +# fnmadd.d D,S,T,R 0200704f 0600707f SIMPLE (0, 0) +:fnmadd.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f- frs3D; +} + + +# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0) +:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f- frs3D; +} + + +# fnmsub.d D,S,T,R 0200704b 0600707f SIMPLE (0, 0) +:fnmsub.d frd,frs1D,frs2D,frs3D is RV32 & RVD & frs1D & frd & frs2D & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f+ frs3D; +} + + +# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0) +:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f+ frs3D; +} + + +# fsd T,q(s) 00003027 0000707f QWORD|DREF (0, 8) +:fsd frs2D,immS(rs1) is RV32 & RVD & frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(DFLEN) ea = frs2D; +} + + +# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0) +:fsgnj.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519!=op2024 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = frs2D[63,1]; + frd = tmp; +} + +# fmv.d D,U 22000053 fe00707f ALIAS (0, 0) +:fmv.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024 +{ + frd = frs1D; +} + + +# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0) +:fsgnjn.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519!=op2024 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = !frs2D[63,1]; + frd = tmp; +} + +# fneg.d D,U 22001053 fe00707f ALIAS (0, 0) +:fneg.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024 +{ + frd = f- frs1D; +} + + +# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0) +:fsgnjx.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519!=op2024 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = tmp[63,1] ^ frs2D[63,1]; + frd = tmp; +} + +# fabs.d D,U 22002053 fe00707f ALIAS (0, 0) +:fabs.d frd,frs1D is RV32 & RVD & frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024 +{ + frd = abs(frs1D); +} + + +# fsqrt.d D,S 5a007053 fff0707f SIMPLE (0, 0) +:fsqrt.d frd,frs1D is RV32 & RVD & frs1D & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2d & op2024=0x0 +{ + frd = sqrt(frs1D); +} + + +# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0) +:fsqrt.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0 +{ + frd = sqrt(frs1D); +} + + +# fsub.d D,S,T 0a007053 fe00707f SIMPLE (0, 0) +:fsub.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x5 +{ + frd = frs1D f- frs2D; +} + + +# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0) +:fsub.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5 +{ + frd = frs1D f- frs2D; +} + +@endif diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc new file mode 100644 index 0000000000..d31aa8dc13 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc @@ -0,0 +1,358 @@ +# RV32F Standard Extension + +@if FPSIZE != "" + +# fadd.s D,S,T 00007053 fe00707f SIMPLE (0, 0) +:fadd.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x0 +{ + local tmp:4 = frs1S f+ frs2S; + fassignS(frd, tmp); +} + + +# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0) +:fadd.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0 +{ + local tmp:4 = frs1S f+ frs2S; + fassignS(frd, tmp); +} + + +# fclass.s d,S e0001053 fff0707f SIMPLE (0, 0) +:fclass.s rd,frs1S is RV32 & RVF & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + +# fcvt.s.w D,s d0007053 fff0707f SIMPLE (0, 0) +:fcvt.s.w frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x0 +{ + local tmp:4 = int2float(rs1W); + fassignS(frd, tmp); +} + + +# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0) +:fcvt.s.w frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0 +{ + local tmp:4 = int2float(rs1W); + fassignS(frd, tmp); +} + + +# fcvt.s.wu D,s d0107053 fff0707f SIMPLE (0, 0) +:fcvt.s.wu frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x1 +{ + #ATTN unsigned can be an issue here + local u32:$(XLEN2) = zext(rs1W); + local tmp:4 = int2float(u32); + fassignS(frd, tmp); +} + + +# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0) +:fcvt.s.wu frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1 +{ + #ATTN unsigned can be an issue here + local u32:$(XLEN2) = zext(rs1W); + local tmp:4 = int2float(u32); + fassignS(frd, tmp); +} + + +# fcvt.w.s d,S c0007053 fff0707f SIMPLE (0, 0) +:fcvt.w.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x0 +{ + rdW = trunc(frs1S); +} + +# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0) +:fcvt.w.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0 +{ + rdW = trunc(frs1S); +} + + +# fcvt.wu.s d,S c0107053 fff0707f SIMPLE (0, 0) +:fcvt.wu.s rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1S); +} + +# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1S); +} + + +# fdiv.s D,S,T 18007053 fe00707f SIMPLE (0, 0) +:fdiv.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xc +{ + local tmp:4 = frs1S f/ frs2S; + fassignS(frd, tmp); +} + + +# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0) +:fdiv.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc +{ + local tmp:4 = frs1S f/ frs2S; + fassignS(frd, tmp); +} + + +# feq.s d,S,T a0002053 fe00707f SIMPLE (0, 0) +:feq.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50 +{ + rd = zext(frs1S f== frs2S); +} + + +# fle.s d,S,T a0000053 fe00707f SIMPLE (0, 0) +:fle.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50 +{ + rd = zext(frs1S f<= frs2S); +} + + +# flt.s d,S,T a0001053 fe00707f SIMPLE (0, 0) +:flt.s rd,frs1S,frs2S is RV32 & RVF & frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50 +{ + rd = zext(frs1S f< frs2S); +} + + +# flw D,o(s) 00002007 0000707f DWORD|DREF (0, 4) +:flw frd,immI(rs1) is RV32 & RVF & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2 +{ + local ea:$(XLEN) = immI + rs1; + fassignS(frd, *[ram]:4 ea); +} + + +# fmadd.s D,S,T,R 00007043 0600707f SIMPLE (0, 0) +:fmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f+ frs3S; + fassignS(frd, tmp); +} + + +# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0) +:fmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f+ frs3S; + fassignS(frd, tmp); +} + + +# fmax.s D,S,T 28001053 fe00707f SIMPLE (0, 0) +:fmax.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14 +{ + #TODO redo this + local tmpfrs1 = frs1S; + local tmpfrs2 = frs2S; + fassignS(frd, tmpfrs1); + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + fassignS(frd, tmpfrs2); + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f>= tmpfrs1) goto inst_next; + fassignS(frd, tmpfrs1); +} + + +# fmin.s D,S,T 28000053 fe00707f SIMPLE (0, 0) +:fmin.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14 +{ + #TODO redo this + local tmpfrs1 = frs1S; + local tmpfrs2 = frs2S; + fassignS(frd, tmpfrs1); + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + fassignS(frd, tmpfrs2); + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + fassignS(frd, tmpfrs1); +} + + +# fmsub.s D,S,T,R 00007047 0600707f SIMPLE (0, 0) +:fmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f- frs3S; + fassignS(frd, tmp); +} + + +# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0) +:fmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f- frs3S; + fassignS(frd, tmp); +} + + +# fmul.s D,S,T 10007053 fe00707f SIMPLE (0, 0) +:fmul.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x8 +{ + local tmp:4 = frs1S f* frs2S; + fassignS(frd, tmp); +} + +# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0) +:fmul.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8 +{ + local tmp:4 = frs1S f* frs2S; + fassignS(frd, tmp); +} + + +# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0) +:fmv.w.x frd,rs1W is RV32 & RVF & frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 +{ + fassignS(frd, rs1W); +} + +# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0) +:fmv.x.w rdW,frs1S is RV32 & RVF & frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 +{ + zassignW(rdW, frs1S); +} + + +# fnmadd.s D,S,T,R 0000704f 0600707f SIMPLE (0, 0) +:fnmadd.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S; + fassignS(frd, tmp); +} + + +# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0) +:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S; + fassignS(frd, tmp); +} + + +# fnmsub.s D,S,T,R 0000704b 0600707f SIMPLE (0, 0) +:fnmsub.s frd,frs1S,frs2S,frs3S is RV32 & RVF & frs1S & frd & frs2S & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S; + fassignS(frd, tmp); +} + + +# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0) +:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S; + fassignS(frd, tmp); +} + + +# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0) +:fsgnj.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519!=op2024 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = frs2S[31,1]; + fassignS(frd, tmp); +} + +# fmv.s D,U 20000053 fe00707f ALIAS (0, 0) +:fmv.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024 +{ + fassignS(frd, frs1S); +} + + +# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0) +:fsgnjn.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519!=op2024 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = !frs2S[31,1]; + fassignS(frd, tmp); +} + +# fneg.s D,U 20001053 fe00707f ALIAS (0, 0) +:fneg.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024 +{ + local tmp:4 = f- frs1S; + fassignS(frd, tmp); +} + + +# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0) +:fsgnjx.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519!=op2024 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = tmp[31,1] ^ frs2S[31,1]; + fassignS(frd, tmp); +} + +# fabs.s D,U 20002053 fe00707f ALIAS (0, 0) +:fabs.s frd,frs1S is RV32 & RVF & frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024 +{ + local tmp:4 = abs(frs1S); + fassignS(frd, tmp); +} + + +# fsqrt.s D,S 58007053 fff0707f SIMPLE (0, 0) +:fsqrt.s frd,frs1S is RV32 & RVF & frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2c & op2024=0x0 +{ + local tmp:4 = sqrt(frs1S); + fassignS(frd, tmp); +} + + +# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0) +:fsqrt.s frd,frs1S,FRM is RV32 & RVF & frs1S & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0 +{ + local tmp:4 = sqrt(frs1S); + fassignS(frd, tmp); +} + + +# fsub.s D,S,T 08007053 fe00707f SIMPLE (0, 0) +:fsub.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x4 +{ + local tmp:4 = frs1S f- frs2S; + fassignS(frd, tmp); +} + + +# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0) +:fsub.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4 +{ + local tmp:4 = frs1S f- frs2S; + fassignS(frd, tmp); +} + + +# fsw T,q(s) 00002027 0000707f DWORD|DREF (0, 4) +:fsw frs2S,immS(rs1) is RV32 & RVF & frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(SFLEN) ea = frs2S; +} + +@endif \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc new file mode 100644 index 0000000000..6391935990 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc @@ -0,0 +1,359 @@ +# RV32I Base Instruction Set + + +# add d,s,t 00000033 fe00707f SIMPLE (0, 0) +:add rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0 +{ + rd = rs1 + rs2; +} + + +# addi d,s,j 00000013 0000707f SIMPLE (0, 0) +:addi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031!=0 & op1519!=0 +{ + rd = rs1 + immI; +} + +# nop 00000013 ffffffff ALIAS (0, 0) +:nop is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0 +{ + local NOP:1 = 0; + NOP = NOP; +} + +# mv d,s 00000013 fff0707f ALIAS (0, 0) +:mv rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0 +{ + rd = rs1; +} + +# li d,j 00000013 000ff07f ALIAS (0, 0) +:li rd,immI is RV32 & RVI & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0 & op2031!=0 +{ + #TODO alias of addi rd,zero,0x0 is an issue + # choosing between: mv rd,zero and li rd,0x0 + #ATTN this implementation uses mv rd,zero + rd = immI; +} + + + +# and d,s,t 00007033 fe00707f SIMPLE (0, 0) +:and rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0 +{ + rd = rs1 & rs2; +} + + +# andi d,s,j 00007013 0000707f SIMPLE (0, 0) +:andi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7 +{ + rd = rs1 & immI; +} + + +# auipc d,u 00000017 0000007f SIMPLE (0, 0) +:auipc rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0 +{ + rd = (immU << 12) + inst_start; +} + + +# beq s,t,p 00000063 0000707f CONDBRANCH (0, 0) +:beq rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0 +{ + if (rs1 == rs2) goto immSB; +} + + +# bge s,t,p 00005063 0000707f CONDBRANCH (0, 0) +:bge rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 +{ + if (rs1 s>= rs2) goto immSB; +} + + +# bgeu s,t,p 00007063 0000707f CONDBRANCH (0, 0) +:bgeu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7 +{ + if (rs1 >= rs2) goto immSB; +} + + +# blt s,t,p 00004063 0000707f CONDBRANCH (0, 0) +:blt rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 +{ + if (rs1 s< rs2) goto immSB; +} + + +# bltu s,t,p 00006063 0000707f CONDBRANCH (0, 0) +:bltu rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6 +{ + if (rs1 < rs2) goto immSB; +} + + +# bne s,t,p 00001063 0000707f CONDBRANCH (0, 0) +:bne rs1,rs2,immSB is RV32 & RVI & immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1 +{ + if (rs1 != rs2) goto immSB; +} + + +# ebreak 00100073 ffffffff SIMPLE (0, 0) +:ebreak is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20 +{ +} + + +# ecall 00000073 ffffffff SIMPLE (0, 0) +:ecall is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0 +{ +} + + +# fence P,Q 0000000f f00fffff SIMPLE (0, 0) +:fence pred,succ is RV32 & RVI & pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0 +{ +} + +# jal d,a 0000006f 0000007f JSR (0, 0) +:jal rd,immUJ is RV32 & RVI & immUJ & rd & op0711!=0 & op0001=0x3 & op0204=0x3 & op0506=0x3 +{ + rd = inst_next; + call immUJ; +} + +# j a 0000006f 00000fff BRANCH|ALIAS (0, 0) +:j immUJ is RV32 & RVI & immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0 +{ + call immUJ; +} + + +# jalr d,s,j 00000067 0000707f JSR (0, 0) +:jalr rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711!=0 +{ + local ea:$(XLEN) = (rs1 + immI) & ~1; + rd = inst_next; + call [ea]; +} + +# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0) +:jr immI(rs1) is RV32 & RVI & immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031!=0 +{ + local ea:$(XLEN) = (rs1 + immI) & ~1; + call [ea]; +} + +# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0) +:jr rs1 is RV32 & RVI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519>1 +{ + local ea:$(XLEN) = rs1 & ~1; + call [ea]; +} + +# ret 00008067 ffffffff BRANCH|ALIAS (0, 0) +:ret is RV32 & RVI & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1 +{ + local ea:$(XLEN) = ra & ~1; + return [ea]; +} + + +# lb d,o(s) 00000003 0000707f BYTE|DREF (0, 1) +:lb rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0 +{ + local ea:$(XLEN) = rs1 + immI; + rd = sext(*[ram]:1 ea); +} + + +# lbu d,o(s) 00004003 0000707f BYTE|DREF (0, 1) +:lbu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:1 ea); +} + + +# lh d,o(s) 00001003 0000707f WORD|DREF (0, 2) +:lh rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1 +{ + local ea:$(XLEN) = rs1 + immI; + rd = sext(*[ram]:2 ea); +} + + +# lhu d,o(s) 00005003 0000707f WORD|DREF (0, 2) +:lhu rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:2 ea); +} + + +# lui d,u 00000037 0000007f SIMPLE (0, 0) +:lui rd,immU is RV32 & RVI & immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1 +{ + rd = immU << 12; +} + + +# lw d,o(s) 00002003 0000707f DWORD|DREF (0, 4) +:lw rd,immI(rs1) is RV32 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2 +{ + local ea:$(XLEN) = rs1 + immI; + assignW(rd, *[ram]:4 ea); +} + + +# or d,s,t 00006033 fe00707f SIMPLE (0, 0) +:or rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0 +{ + rd = rs1 | rs2; +} + + +# ori d,s,j 00006013 0000707f SIMPLE (0, 0) +:ori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6 +{ + rd = rs1 | immI; +} + + +# sb t,q(s) 00000023 0000707f BYTE|DREF (0, 1) +:sb rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:1 ea = rs2:1; +} + + +# sh t,q(s) 00001023 0000707f WORD|DREF (0, 2) +:sh rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:2 ea = rs2:2; +} + + +# sll d,s,t 00001033 fe00707f SIMPLE (0, 0) +:sll rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x3f; + rd = rs1 << shift; +} + + +# slli d,s,> 00001013 fc00707f SIMPLE (0, 0) +:slli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0 +{ + rd = rs1 << shamt6; +} + + +# slt d,s,t 00002033 fe00707f SIMPLE (0, 0) +:slt rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 +{ + rd = zext(rs1 s< rs2); +} + + +# slti d,s,j 00002013 0000707f SIMPLE (0, 0) +:slti rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2 +{ + rd = zext(rs1 s< immI); +} + + +# sltiu d,s,j 00003013 0000707f SIMPLE (0, 0) +:sltiu rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 +{ + rd = zext(rs1 < immI); +} + + +# sltu d,s,t 00003033 fe00707f SIMPLE (0, 0) +:sltu rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 +{ + rd = zext(rs1 < rs2); +} + + +# sra d,s,t 40005033 fe00707f SIMPLE (0, 0) +:sra rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20 +{ + local shift:$(XLEN) = rs2 & 0x3f; + rd = rs1 s>> shift; +} + + +# srai d,s,> 40005013 fc00707f SIMPLE (0, 0) +:srai rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10 +{ + rd = rs1 s>> shamt6; +} + + +# srl d,s,t 00005033 fe00707f SIMPLE (0, 0) +:srl rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x3f; + rd = rs1 >> shift; +} + + +# srli d,s,> 00005013 fc00707f SIMPLE (0, 0) +:srli rd,rs1,shamt6 is RV32 & RVI & rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0 +{ + rd = rs1 >> shamt6; +} + + +# sub d,s,t 40000033 fe00707f SIMPLE (0, 0) +:sub rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0 +{ + rd = rs1 - rs2; +} + +# neg d,t 40000033 fe0ff07f ALIAS (0, 0) +:neg rd,rs2 is RV32 & RVI & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 +{ + rd = -rs2; +} + + +# sw t,q(s) 00002023 0000707f DWORD|DREF (0, 4) +:sw rs2,immS(rs1) is RV32 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:4 ea = rs2:4; +} + + +# unimp c0001073 ffffffff SIMPLE (0, 0) +:unimp is RV32 & RVI & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000 +{ +} + + +# xor d,s,t 00004033 fe00707f SIMPLE (0, 0) +:xor rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0 +{ + rd = rs1 ^ rs2; +} + + +# xori d,s,j 00004013 0000707f SIMPLE (0, 0) +:xori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031!=0xfff +{ + rd = rs1 ^ immI; +} + +# not d,s fff04013 fff0707f ALIAS (0, 0) +:not rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff +{ + rd = ~rs1; +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc new file mode 100644 index 0000000000..b1e05c75d7 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc @@ -0,0 +1,66 @@ +# RV32M Standard Extension + + +# div d,s,t 02004033 fe00707f SIMPLE (0, 0) +:div rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1 +{ + rd = rs1 s/ rs2; +} + + +# divu d,s,t 02005033 fe00707f SIMPLE (0, 0) +:divu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1 +{ + rd = rs1 / rs2; +} + + +# mul d,s,t 02000033 fe00707f SIMPLE (0, 0) +:mul rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1 +{ + rd = rs1 * rs2; +} + + +# mulh d,s,t 02001033 fe00707f SIMPLE (0, 0) +:mulh rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1 +{ + local trs1:$(XLEN2) = sext(rs1); + local trs2:$(XLEN2) = sext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# mulhsu d,s,t 02002033 fe00707f SIMPLE (0, 0) +:mulhsu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1 +{ + local trs1:$(XLEN2) = sext(rs1); + local trs2:$(XLEN2) = zext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# mulhu d,s,t 02003033 fe00707f SIMPLE (0, 0) +:mulhu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1 +{ + local trs1:$(XLEN2) = zext(rs1); + local trs2:$(XLEN2) = zext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# rem d,s,t 02006033 fe00707f SIMPLE (0, 0) +:rem rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1 +{ + rd = rs1 s% rs2; +} + + +# remu d,s,t 02007033 fe00707f SIMPLE (0, 0) +:remu rd,rs1,rs2 is RV32 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1 +{ + rd = rs1 % rs2; +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc new file mode 100644 index 0000000000..9c697ee0bc --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc @@ -0,0 +1,322 @@ +# RV32Q Standard Extension + +#TODO fix q +#FIXME fix q +@if FPSIZE == "128" + +# fadd.q D,S,T 06007053 fe00707f SIMPLE (0, 0) +:fadd.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x3 +{ + frd = frs1 f+ frs2; +} + +# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0) +:fadd.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3 +{ + frd = frs1 f+ frs2; +} + +# fclass.q d,S e6001053 fff0707f SIMPLE (0, 0) +:fclass.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + + +# fcvt.d.q D,S 42307053 fff0707f SIMPLE (0, 0) +:fcvt.d.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x21 & op2024=0x3 +{ + #TODO quad to double +} + +# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0) +:fcvt.d.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3 +{ + #TODO double to quad +} + +# fcvt.q.d D,S 46100053 fff0707f SIMPLE (0, 0) +:fcvt.q.d frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1 +{ + frd = float2float(frs1); +} + +# fcvt.q.s D,S 46000053 fff0707f SIMPLE (0, 0) +:fcvt.q.s frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0 +{ + frd = float2float(frs1); +} + +# fcvt.q.w D,s d6000053 fff0707f SIMPLE (0, 0) +:fcvt.q.w frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0 +{ + frd = int2float(rs1); +} + +# fcvt.q.wu D,s d6100053 fff0707f SIMPLE (0, 0) +:fcvt.q.wu frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1 +{ + frd = int2float(rs1); +} + +# fcvt.s.q D,S 40307053 fff0707f SIMPLE (0, 0) +:fcvt.s.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x20 & op2024=0x3 +{ + frd = float2float(frs1); +} + +# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0) +:fcvt.s.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3 +{ + frd = float2float(frs1); +} + +# fcvt.w.q d,S c6007053 fff0707f SIMPLE (0, 0) +:fcvt.w.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x0 +{ + rd = trunc(frs1); +} + +# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0) +:fcvt.w.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0 +{ + rd = trunc(frs1); +} + +# fcvt.wu.q d,S c6107053 fff0707f SIMPLE (0, 0) +:fcvt.wu.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x1 +{ + rd = trunc(frs1); +} + +# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1 +{ + rd = trunc(frs1); +} + + +# fdiv.q D,S,T 1e007053 fe00707f SIMPLE (0, 0) +:fdiv.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xf +{ + local tfrs1:$(QFLEN) = frs1; + local tfrs2:$(QFLEN) = frs2; + local result:$(QFLEN) = tfrs1 f/ tfrs2; + frd = result; +} + + +# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0) +:fdiv.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf +{ + local tfrs1:$(QFLEN) = frs1; + local tfrs2:$(QFLEN) = frs2; + local result:$(QFLEN) = tfrs1 f/ tfrs2; + frd = result; +} + + +# feq.q d,S,T a6002053 fe00707f SIMPLE (0, 0) +:feq.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53 +{ + rd = zext(frs1 f== frs2); +} + + +# fle.q d,S,T a6000053 fe00707f SIMPLE (0, 0) +:fle.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53 +{ + rd = zext(frs1 f<= frs2); +} + +# flq D,o(s) 00004007 0000707f OWORD|DREF (0, 16) +:flq frd,immI(rs1) is RV32 & RVQ & immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4 +{ + local ea:$(XLEN) = immI + rs1; + frd = *[ram]:16 ea; +} + + +# flt.q d,S,T a6001053 fe00707f SIMPLE (0, 0) +:flt.q rd,frs1,frs2 is RV32 & RVQ & frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53 +{ + rd = zext(frs1 f< frs2); +} + + + +# fmadd.q D,S,T,R 06007043 0600707f SIMPLE (0, 0) +:fmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & funct3=0x7 & op2526=0x3 +{ + frd = (frs1 f* frs2) f+ frs3; +} + +# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0) +:fmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3 +{ + frd = (frs1 f* frs2) f+ frs3; +} + +# fmax.q D,S,T 2e001053 fe00707f SIMPLE (0, 0) +:fmax.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17 +{ + local tmpfrs1 = frs1; + local tmpfrs2 = frs2; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f> tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + +# fmin.q D,S,T 2e000053 fe00707f SIMPLE (0, 0) +:fmin.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17 +{ + local tmpfrs1 = frs1; + local tmpfrs2 = frs2; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + +# fmsub.q D,S,T,R 06007047 0600707f SIMPLE (0, 0) +:fmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & funct3=0x7 & op2526=0x3 +{ + frd = (frs1 f* frs2) f- frs3; +} + +# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0) +:fmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3 +{ + frd = (frs1 f* frs2) f- frs3; +} + +# fmul.q D,S,T 16007053 fe00707f SIMPLE (0, 0) +:fmul.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0xb +{ + frd = frs1 f* frs2; +} + +# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0) +:fmul.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb +{ + frd = frs1 f* frs2; +} + + +# fmv.q.x D,s f6000053 fff0707f SIMPLE (64, 0) +:fmv.q.x frd,rs1 is RV32 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0 +{ + frd = int2float(rs1); +} + + +# fmv.x.q d,S e6000053 fff0707f SIMPLE (64, 0) +:fmv.x.q rd,frs1 is RV32 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0 +{ + rd = trunc(frs1); +} + + +# fnmadd.q D,S,T,R 0600704f 0600707f SIMPLE (0, 0) +:fnmadd.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & funct3=0x7 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f- frs3; +} + +# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0) +:fnmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f- frs3; +} + +# fnmsub.q D,S,T,R 0600704b 0600707f SIMPLE (0, 0) +:fnmsub.q frd,frs1,frs2,frs3 is RV32 & RVQ & frs1 & frd & frs2 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & funct3=0x7 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f+ frs3; +} + +# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0) +:fnmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f+ frs3; +} + + +# fsgnj.q D,S,T 26000053 fe00707f SIMPLE (0, 0) +:fsgnj.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13 +{ local tmp = frs1; + tmp[127,1] = frs2[127,1]; + frd = tmp; +} + + +# fsgnjn.q D,S,T 26001053 fe00707f SIMPLE (0, 0) +:fsgnjn.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13 +{ + local tmp = frs1; + tmp[127,1] = !frs2[127,1]; + frd = tmp; +} + + +# fsgnjx.q D,S,T 26002053 fe00707f SIMPLE (0, 0) +:fsgnjx.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13 +{ + local tmp = frs1; + tmp[127,1] = tmp[127,1] ^ frs2[127,1]; + frd = tmp; +} + + +:fsq frs2,immS(rs1) is RV32 & RVQ & frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(QFLEN) ea = frs2; +} + + +# fsqrt.q D,S 5e007053 fff0707f SIMPLE (0, 0) +:fsqrt.q frd,frs1 is RV32 & RVQ & frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x2f & op2024=0x0 +{ + frd = sqrt(frs1); +} + +# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0) +:fsqrt.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0 +{ + frd = sqrt(frs1); +} + + +# fsub.q D,S,T 0e007053 fe00707f SIMPLE (0, 0) +:fsub.q frd,frs1,frs2 is RV32 & RVQ & frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x7 +{ + frd = frs1 f- frs2; +} + +# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0) +:fsub.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7 +{ + frd = frs1 f- frs2; +} + +@endif \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc new file mode 100644 index 0000000000..7b7d500206 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc @@ -0,0 +1,135 @@ +# RV64A Standard Extension (in addition to RV32A) + + +# amoadd.d d,t,0(s) 0000302f fe00707f QWORD|DREF (64, 8) +:amoadd.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp + tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amoand.d d,t,0(s) 6000302f fe00707f QWORD|DREF (64, 8) +:amoand.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp & tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amomax.d d,t,0(s) a000302f fe00707f QWORD|DREF (64, 8) +:amomax.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 s<= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amomaxu.d d,t,0(s) e000302f fe00707f QWORD|DREF (64, 8) +:amomaxu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 <= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amomin.d d,t,0(s) 8000302f fe00707f QWORD|DREF (64, 8) +:amomin.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 s>= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amominu.d d,t,0(s) c000302f fe00707f QWORD|DREF (64, 8) +:amominu.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 >= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amoor.d d,t,0(s) 4000302f fe00707f QWORD|DREF (64, 8) +:amoor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp | tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amoswap.d d,t,0(s) 0800302f fe00707f QWORD|DREF (64, 8) +:amoswap.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amoxor.d d,t,0(s) 2000302f fe00707f QWORD|DREF (64, 8) +:amoxor.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp ^ tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# lr.d d,0(s) 1000302f fff0707f QWORD|DREF (64, 8) +:lr.d^aqrl rdL,(rs1) is RV64 & RVA & rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl +{ + RESERVE_ADDRESS = rs1; + RESERVE = 1; + RESERVE_LENGTH = 8; + rdL = *[ram]:8 rs1; +} + + +# sc.d d,t,0(s) 1800302f fe00707f QWORD|DREF (64, 8) +:sc.d^aqrl rdL,rs2L,(rs1) is RV64 & RVA & rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl +{ + local tmprs2 = rs2L; + local tmprs1 = rs1; + rdL = 1; + if (RESERVE == 0) goto inst_next; + if (RESERVE_ADDRESS != rs1) goto inst_next; + if (RESERVE_LENGTH != 8) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; + rdL = 0; + RESERVE_ADDRESS = 0; + RESERVE = 0; + RESERVE_LENGTH = 0; +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc new file mode 100644 index 0000000000..3bb2d3c4ad --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc @@ -0,0 +1,82 @@ +# RV64D Standard Extension (in addition to RV32D) + +@if FPSIZE == "64" + +# fcvt.d.l D,s d2207053 fff0707f SIMPLE (64, 0) +:fcvt.d.l frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x2 +{ + local tmp:8 = int2float(rs1L); + frd = tmp; +} + + +# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0) +:fcvt.d.l frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2 +{ + local tmp:8 = int2float(rs1L); + frd = tmp; +} + + +# fcvt.d.lu D,s d2307053 fff0707f SIMPLE (64, 0) +:fcvt.d.lu frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x69 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:8 = int2float(u64); + frd = tmp; +} + + +# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0) +:fcvt.d.lu frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:8 = int2float(u64); + frd = tmp; +} + + +# fcvt.l.d d,S c2207053 fff0707f SIMPLE (64, 0) +:fcvt.l.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x2 +{ + rdL = trunc(frs1D); +} + + +# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0) +:fcvt.l.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2 +{ + rdL = trunc(frs1D); +} + + +# fcvt.lu.d d,S c2307053 fff0707f SIMPLE (64, 0) +:fcvt.lu.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x61 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1D); +} + + +# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1D); +} + + +# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0) +:fmv.d.x frd,rs1L is RV64 & RVD & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0 +{ + frd = rs1L; +} + +:fmv.x.d rdL,frs1D is RV64 & RVD & frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0 +{ + rdL = frs1D; +} + +@endif \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc new file mode 100644 index 0000000000..449390f652 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc @@ -0,0 +1,70 @@ +# RV64F Standard Extension (in addition to RV32F) + +@if FPSIZE != "" + +# fcvt.l.s d,S c0207053 fff0707f SIMPLE (64, 0) +:fcvt.l.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x2 +{ + rdL = trunc(frs1S); +} + + +# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0) +:fcvt.l.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2 +{ + rdL = trunc(frs1S); +} + + +# fcvt.lu.s d,S c0307053 fff0707f SIMPLE (64, 0) +:fcvt.lu.s rdL,frs1S is RV64 & RVF & frs1S & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x60 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1S); +} + + +# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1S); +} + + +# fcvt.s.l D,s d0207053 fff0707f SIMPLE (64, 0) +:fcvt.s.l frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x2 +{ + local tmp:4 = int2float(rs1L); + fassignS(frd, tmp); +} + + +# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0) +:fcvt.s.l frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2 +{ + local tmp:4 = int2float(rs1L); + fassignS(frd, tmp); +} + + +# fcvt.s.lu D,s d0307053 fff0707f SIMPLE (64, 0) +:fcvt.s.lu frd,rs1L is RV64 & RVF & frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x68 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:4 = int2float(u64); + fassignS(frd, tmp); +} + + +# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0) +:fcvt.s.lu frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:4 = int2float(u64); + fassignS(frd, tmp); +} + +@endif \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc new file mode 100644 index 0000000000..85d277fb38 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc @@ -0,0 +1,122 @@ +# RV64I Base Instruction Set (in addition to RV32I) + + +# addiw d,s,j 0000001b 0000707f SIMPLE (64, 0) +:addiw rd,rs1,immI is RV64 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031>0 +{ + local result = rs1 + immI; + rd = sext(result:4); +} + +:sext.w rd,rs1 is RV64 & RVI & rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0 +{ + local result = rs1; + rd = sext(result:4); +} + + + +# addw d,s,t 0000003b fe00707f SIMPLE (64, 0) +:addw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + local result:4 = tmpr1 + tmpr2; + rd = sext(result); +} + + +# ld d,o(s) 00003003 0000707f QWORD|DREF (64, 8) +:ld rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3 +{ + local ea:$(XLEN) = rs1 + immI; + rd = *[ram]:8 ea; +} + + +# lwu d,o(s) 00006003 0000707f DWORD|DREF (64, 4) +:lwu rd,immI(rs1) is RV64 & RVI & immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:4 ea); +} + + +# sd t,q(s) 00003023 0000707f QWORD|DREF (64, 8) +:sd rs2,immS(rs1) is RV64 & RVI & immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:8 ea = rs2; +} + + +# slliw d,s,< 0000101b fe00707f SIMPLE (64, 0) +:slliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0 +{ + local tmp:4 = rs1:4; + tmp = tmp << shamt5; + rd = sext(tmp); +} + + +# sllw d,s,t 0000103b fe00707f SIMPLE (64, 0) +:sllw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp << shift; + rd = sext(tmp); +} + + +# sraiw d,s,< 4000501b fe00707f SIMPLE (64, 0) +:sraiw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20 +{ + local tmp:4 = rs1:4; + tmp = tmp s>> shamt5; + rd = sext(tmp); +} + + +# sraw d,s,t 4000503b fe00707f SIMPLE (64, 0) +:sraw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp s>> shift; + rd = sext(tmp); +} + + +# srliw d,s,< 0000501b fe00707f SIMPLE (64, 0) +:srliw rd,rs1,shamt5 is RV64 & RVI & rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0 +{ + local tmp:4 = rs1:4; + tmp = tmp >> shamt5; + rd = sext(tmp); +} + + +# srlw d,s,t 0000503b fe00707f SIMPLE (64, 0) +:srlw rd,rs1,rs2 is RV64 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp >> shift; + rd = sext(tmp); +} + + +# subw d,s,t 4000003b fe00707f SIMPLE (64, 0) +:subw rd,rs1W,rs2W is RV64 & RVI & rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0 +{ + local result = rs1W - rs2W; + rd = sext(result); +} + +# negw d,t 4000003b fe0ff07f ALIAS (64, 0) +:negw rd,rs2W is RV64 & RVI & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 +{ + local tmp = -rs2W; + rd = sext(tmp); +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc new file mode 100644 index 0000000000..53dc93a7dd --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc @@ -0,0 +1,45 @@ +# RV64M Standard Exention (in addition to RV32M) + + +# divuw d,s,t 0200503b fe00707f SIMPLE (64, 0) +:divuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 / tmpr2); +} + + +# divw d,s,t 0200403b fe00707f SIMPLE (64, 0) +:divw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 s/ tmpr2); +} + + +# mulw d,s,t 0200003b fe00707f SIMPLE (64, 0) +:mulw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1 +{ + local tmp:4 = rs1:4 * rs2:4; + rd = sext(tmp); +} + + +# remuw d,s,t 0200703b fe00707f SIMPLE (64, 0) +:remuw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 % tmpr2); +} + + +# remw d,s,t 0200603b fe00707f SIMPLE (64, 0) +:remw rd,rs1,rs2 is RV64 & RVM & rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 s% tmpr2); +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc new file mode 100644 index 0000000000..ff41812bea --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc @@ -0,0 +1,62 @@ +# RV64Q Standard Extension (in addition to RV32Q) + +#TODO fix q +#FIXME fix q +@if FPSIZE == "128" + +# fcvt.l.q d,S c6207053 fff0707f SIMPLE (64, 0) +:fcvt.l.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x2 +{ + rd = trunc(frs1); +} + + +# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0) +:fcvt.l.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2 +{ + rd = trunc(frs1); +} + + +# fcvt.lu.q d,S c6307053 fff0707f SIMPLE (64, 0) +:fcvt.lu.q rd,frs1 is RV64 & RVQ & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x63 & op2024=0x3 +{ + rd = trunc(frs1); +} + + +# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3 +{ + rd = trunc(frs1); +} + + +# fcvt.q.l D,s d6207053 fff0707f SIMPLE (64, 0) +:fcvt.q.l frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x2 +{ + frd = int2float(rs1); +} + + +# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0) +:fcvt.q.l frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2 +{ + frd = int2float(rs1); +} + + +# fcvt.q.lu D,s d6307053 fff0707f SIMPLE (64, 0) +:fcvt.q.lu frd,rs1 is RV64 & RVQ & frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x7 & funct7=0x6b & op2024=0x3 +{ + frd = int2float(rs1); +} + + +# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0) +:fcvt.q.lu frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3 +{ + frd = int2float(rs1); +} + +@endif \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc new file mode 100644 index 0000000000..38cb9854ad --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc @@ -0,0 +1,371 @@ +# RVC Standard Extension for Compressed Instructions + + +# c.add d,CV 00009002 0000f003 SIMPLE (0, 0) +:c.add crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 & cop0711!=0 & cop0206!=0 +{ + crd = crd + crs2; +} + +# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0) +:c.addi crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x0 & cop0711!=0 & (cop1212!=0 | cop0206!=0) +{ + crd = crd + cimmI; +} + +:c.nop is RVC & cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0 +{ + local NOP:1 = 0; + NOP = NOP; +} + +# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0) +:c.addi16sp sp,caddi16spimm is RVC & cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 & cop0512!=0 +{ + sp = sp + caddi16spimm; +} + +# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0) +:c.addi4spn cr0204s,sp,caddi4spnimm is RVC & caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 & cop0512!=0 +{ + cr0204s = sp + caddi4spnimm; +} + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0) +:c.addiw crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x1 & cop0711!=0 +{ + local tmp:8 = crd + cimmI; + crd = sext(tmp:4); +} +@endif + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.addw Cs,Ct 00009c21 0000fc63 SIMPLE (64, 0) +:c.addw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +{ + local tmp:4 = cr0709s:4 + cr0204s:4; + cr0709s = sext(tmp); +} +@endif + +# c.and Cs,Ct 00008c61 0000fc63 SIMPLE (0, 0) +:c.and cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +{ + cr0709s = cr0709s & cr0204s; +} + +# c.andi Cs,Co 00008801 0000ec03 SIMPLE (0, 0) +:c.andi cr0709s,cimmI is RVC & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +{ + cr0709s = cr0709s & cimmI; +} + +# c.beqz Cs,Cp 0000c001 0000e003 CONDBRANCH (0, 0) +:c.beqz cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x6 +{ + if (cr0709s == 0) goto cbimm; +} + +# c.bnez Cs,Cp 0000e001 0000e003 CONDBRANCH (0, 0) +:c.bnez cr0709s,cbimm is RVC & cbimm & cr0709s & cop0001=0x1 & cop1315=0x7 +{ + if (cr0709s != 0) goto cbimm; +} + +# c.ebreak 00009002 0000ffff SIMPLE (0, 0) +:c.ebreak is RVC & cop0001=0x2 & cop1315=0x4 & cop0212=0x400 +{ +} + +@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64" +# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8) +:c.fld cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm +{ + local ea:$(XLEN) = cldimm + cr0709s; + cfr0204s = *[ram]:8 ea; +} +@endif + +@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64" +# c.fldsp D,Cn(Cc) 00002002 0000e003 QWORD|DREF (0, 8) +:c.fldsp cfrd,cldspimm(sp) is RVC & RVD & cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm +{ + local ea:$(XLEN) = cldspimm + sp; + cfrd = *[ram]:8 ea; +} +@endif + +@if ADDRSIZE == "32" && FPSIZE != "" +# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4) +:c.flw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + cfr0204s = *[ram]:4 ea; +} +@endif + +@if ADDRSIZE == "32" && FPSIZE != "" +# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4) +:c.flwsp cfrd,clwspimm(sp) is RVC & RVF & cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm +{ + local ea:$(XLEN) = clwspimm + sp; + cfrd = *[ram]:4 ea; +} +@endif + +@if ADDRSIZE == "32" || ADDRSIZE == "64" +# c.fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF (0, 8) +:c.fsd cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm +{ + local ea:$(XLEN) = cldimm + cr0709s; + *[ram]:8 ea = cfr0204s; +} +@endif + +@if ADDRSIZE == "32" || ADDRSIZE == "64" +# c.fsdsp CT,CN(Cc) 0000a002 0000e003 QWORD|DREF (0, 8) +:c.fsdsp cfr0206,csdspimm(sp) is RVC & RVD & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm +{ + local ea:$(XLEN) = csdspimm + sp; + *[ram]:8 ea = cfr0206; +} +@endif + +@if ADDRSIZE == "32" +# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4) +:c.fsw cfr0204s,clwimm(cr0709s) is RVC & RVF & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + *[ram]:4 ea = cfr0204s; +} +@endif + +@if ADDRSIZE == "32" +# c.fswsp CT,CM(Cc) 0000e002 0000e003 DWORD|DREF (32, 4) +:c.fswsp cfr0206,cswspimm(sp) is RVC & RVF & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm +{ + local ea:$(XLEN) = cswspimm + sp; + *[ram]:4 ea = cfr0206:4; +} +@endif + +# c.j Ca 0000a001 0000e003 BRANCH (0, 0) +:c.j cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x5 +{ + goto cjimm; +} + +@if ADDRSIZE == "32" +# c.jal Ca 00002001 0000e003 JSR (32, 0) +:c.jal cjimm is RVC & cjimm & cop0001=0x1 & cop1315=0x1 +{ + ra = inst_next; + call cjimm; +} +@endif + +# c.jalr d 00009002 0000f07f JSR (0, 0) +:c.jalr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 & cop0711!=0 +{ + ra = inst_next; + call [crd]; +} + +# c.jr d 00008002 0000f07f BRANCH (0, 0) +:c.jr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711>1 +{ + goto [crd]; +} + +# ret 00008082 0000ffff BRANCH|ALIAS (0, 0) +:ret is RVC & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1 +{ + return [ra]; +} + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF (64, 8) +:c.ld cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm +{ + local ea:$(XLEN) = cldimm + cr0709s; + zassignD(cr0204s, *[ram]:8 ea); +} +@endif + +@if ADDRSIZE == "128" +:c.lq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm +{ + local ea:$(XLEN) = clqimm + cr0709s; + cr0204s = *[ram]:16 ea; +} +@endif + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8) +:c.ldsp crd,cldspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm & cop0711!=0 +{ + local ea:$(XLEN) = cldspimm + sp; + zassignD(crd, *[ram]:8 ea); +} +@endif + +@if ADDRSIZE == "128" +:c.lqsp crd,clqspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & clqspimm & cop0711!=0 +{ + local ea:$(XLEN) = clqspimm + sp; + crd = *[ram]:16 ea; +} +@endif + +# c.li d,Co 00004001 0000e003 SIMPLE (0, 0) +:c.li crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x2 & cop0711!=0 +{ + crd = cimmI; +} + +# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0) +:c.lui crd,cbigimm is RVC & cop0711!=0 & cop0711!=2 & crd & cbigimm & cop0001=0x1 & cop1315=0x3 & cop0711!=0 & cop0711!=2 & (cop1212!=0 | cop0206!=0) +{ + crd = cbigimm << 12; +} + +# c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4) +:c.lw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + zassignW(cr0204s, *[ram]:4 ea); +} + +# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0) +:c.lwsp crd,clwspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm & cop0711!=0 +{ + local ea:$(XLEN) = clwspimm + sp; + zassignW(crd, *[ram]:4 ea); +} + +# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0) +:c.mv crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 & cop0711!=0 & cop0206!=0 +{ + crd = crs2; +} + +# c.or Cs,Ct 00008c41 0000fc63 SIMPLE (0, 0) +:c.or cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +{ + cr0709s = cr0709s | cr0204s; +} + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF (64, 8) +:c.sd cr0204s,cldimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm +{ + local ea:$(XLEN) = cldimm + cr0709s; + *[ram]:8 ea = cr0204s:8; +} +@endif + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.sdsp CV,CN(Cc) 0000e002 0000e003 QWORD|DREF (64, 8) +:c.sdsp crs2,csdspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm +{ + local ea:$(XLEN) = csdspimm + sp; + *[ram]:8 ea = crs2:8; +} +@endif + +# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0) +:c.slli crd,c6imm is RVC & crd & c6imm & cop0001=0x2 & cop1315=0x0 & cop0711!=0 +{ + crd = crd << c6imm; +} + +#TODO hint? +# c.slli64 d 00000002 0000f07f SIMPLE (0, 0) +:c.slli64 crd is RVC & crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 & cop0711!=0 +{ + crd = crd << 0; +} + +# c.srai Cs,C> 00008401 0000ec03 SIMPLE (0, 0) +:c.srai cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +{ + cr0709s = cr0709s s>> c6imm; +} + +#TODO hint? +# c.srai64 Cs 00008401 0000fc7f SIMPLE (0, 0) +:c.srai64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1 +{ + cr0709s = cr0709s s>> 0; +} + +# c.srli Cs,C> 00008001 0000ec03 SIMPLE (0, 0) +:c.srli cr0709s,c6imm is RVC & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +{ + cr0709s = cr0709s >> c6imm; +} + +#TODO hint? +# c.srli64 Cs 00008001 0000fc7f SIMPLE (0, 0) +:c.srli64 cr0709s is RVC & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0 +{ + cr0709s = cr0709s >> 0; +} + +# c.sub Cs,Ct 00008c01 0000fc63 SIMPLE (0, 0) +:c.sub cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3 +{ + cr0709s = cr0709s - cr0204s; +} + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +# c.subw Cs,Ct 00009c01 0000fc63 SIMPLE (64, 0) +:c.subw cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7 +{ + local tmp:4 = cr0709s:4 - cr0204s:4; + cr0709s = sext(tmp); +} +@endif + +# c.sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF (0, 4) +:c.sw cr0204s,clwimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + *[ram]:4 ea = cr0204s:4; +} + +@if ADDRSIZE == "128" +:c.sq cr0204s,clqimm(cr0709s) is RVC & cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm +{ + local ea:$(XLEN) = clqimm + cr0709s; + *[ram]:16 ea = cr0204s; +} +@endif + +@if ADDRSIZE == "128" +:c.sqsp crs2,csqspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm +{ + local ea:$(XLEN) = csqspimm + sp; + *[ram]:16 ea = crs2; +} +@endif + +# c.swsp CV,CM(Cc) 0000c002 0000e003 DWORD|DREF (0, 4) +:c.swsp crs2,cswspimm(sp) is RVC & crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm +{ + local ea:$(XLEN) = cswspimm + sp; + *[ram]:4 ea = crs2:4; +} + +# c.unimp 00000000 0000ffff SIMPLE (0, 0) +:c.unimp is RVC & cop0001=0x0 & cop1315=0x0 & cop0212=0x0 +{ + trap(); +} + +# c.xor Cs,Ct 00008c21 0000fc63 SIMPLE (0, 0) +:c.xor cr0709s,cr0204s is RVC & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +{ + cr0709s = cr0709s ^ cr0204s; +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc new file mode 100644 index 0000000000..f21da0672f --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc @@ -0,0 +1,359 @@ + +#TODO these names are madeup. do real ones exist? +#TODO go through and use these instead of numbers +@define HFLEN 2 +@define SFLEN 4 +@define DFLEN 8 +@define QFLEN 16 + +@define HXLEN 2 +@define WXLEN 4 +@define DXLEN 8 +@define QXLEN 16 + + +define pcodeop trap; + + +# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711 +rs1: r1519 is r1519 & op1519!=0 { export r1519; } +rs1: zero is r1519 & zero & op1519=0 { export 0:$(XLEN); } + +rs2: r2024 is r2024 & op2024!=0 { export r2024; } +rs2: zero is r2024 & zero & op2024=0 { export 0:$(XLEN); } + +rd: r0711 is r0711 & op0711!=0 { export r0711; } +rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); } + +@if ADDRSIZE == "32" + +rs1W: r1519 is RV32 & r1519 & op1519!=0 { export r1519; } +rs1W: zero is RV32 & r1519 & zero & op1519=0 { export 0:$(XLEN); } + +rs2W: r2024 is RV32 & r2024 & op2024!=0 { export r2024; } +rs2W: zero is RV32 & r2024 & zero & op2024=0 { export 0:$(XLEN); } + +#TODO dest may be bad, might need an assign macro +rdW: r0711 is RV32 & r0711 & op0711!=0 { export r0711; } +rdW: zero is RV32 & r0711 & zero & op0711=0 { export 0:$(XLEN); } + +@else + +rs1W: r1519 is r1519 & op1519!=0 { local tmp:4 = r1519:4; export tmp; } +rs1W: zero is r1519 & zero & op1519=0 { export 0:4; } + +rs2W: r2024 is r2024 & op2024!=0 { local tmp:4 = r2024:4; export tmp; } +rs2W: zero is r2024 & zero & op2024=0 { export 0:4; } + +#TODO dest may be bad, might need an assign macro +rdW: r0711 is r0711 & op0711!=0 { export r0711; } +rdW: zero is r0711 & zero & op0711=0 { export 0:8; } + +@endif + +#TODO does this need to be in an if/endif +@if ADDRSIZE == "64" +rs1L: r1519 is r1519 & op1519!=0 { local tmp:8 = r1519:8; export tmp; } +rs1L: zero is r1519 & zero & op1519=0 { export 0:8; } + +rs2L: r2024 is r2024 & op2024!=0 { local tmp:8 = r2024:8; export tmp; } +rs2L: zero is r2024 & zero & op2024=0 { export 0:8; } + +#TODO dest may be bad, might need an assign macro +rdL: r0711 is r0711 & op0711!=0 { export r0711; } +rdL: zero is r0711 & zero & op0711=0 { export 0:8; } +@endif + + +#TODO eh not sure if this is usable +# would only make sense to use this if the float operation +# tables for frd,frs1,frs2 could be different sizes or +# if the cast could use this export, but they have to export +# the same size and you cant 'local tmp:fmt' +# # 32-bit single-precision $(SFLEN) +# fmt: ".s" is op2526=0 { export $(SFLEN):1; } +# # 64-bit double-precision $(DFLEN) +# fmt: ".d" is op2526=1 { export $(DFLEN):1; } +# # 16-bit half-precision $(HFLEN) +# fmt: ".h" is op2526=2 { export $(HFLEN):1; } +# # 128-bit quad-precision $(QFLEN) +# fmt: ".q" is op2526=3 { export $(QFLEN):1; } + +@if FPSIZE != "" + +frd: fr0711 is fr0711 { export fr0711; } +frs1: fr1519 is fr1519 { export fr1519; } +frs2: fr2024 is fr2024 { export fr2024; } +frs3: fr2731 is fr2731 { export fr2731; } + +#TODO dest may be bad, might need an assign macro +#frdS: fr0711 is fr0711 { local tmp = fr0711:$(SFLEN); export tmp; } +frs1S: fr1519 is fr1519 { local tmp = fr1519:$(SFLEN); export tmp; } +frs2S: fr2024 is fr2024 { local tmp = fr2024:$(SFLEN); export tmp; } +frs3S: fr2731 is fr2731 { local tmp = fr2731:$(SFLEN); export tmp; } + + +#TODO dest may be bad, might need an assign macro +#frdD: fr0711 is fr0711 { local tmp = fr0711:$(DFLEN); export tmp; } +frs1D: fr1519 is fr1519 { local tmp = fr1519:$(DFLEN); export tmp; } +frs2D: fr2024 is fr2024 { local tmp = fr2024:$(DFLEN); export tmp; } +frs3D: fr2731 is fr2731 { local tmp = fr2731:$(DFLEN); export tmp; } + + +macro fassignS(dest, src) { +@if FPSIZE == "32" + dest = src; +@else + dest = zext(src); +@endif +} + +@endif + +macro assignW(dest, src) { +@if ADDRSIZE == "32" + dest = src; +@else + dest = sext(src); +@endif +} + +macro zassignW(dest, src) { +@if ADDRSIZE == "32" + dest = src; +@else + dest = zext(src); +@endif +} + +macro zassignD(dest, src) { +@if ADDRSIZE == "64" + dest = src; +@else + dest = zext(src); +@endif +} + + + +immI: sop2031 is sop2031 { local tmp:$(XLEN) = sop2031; export tmp; } + +immS: imm is op0711 & sop2531 [ imm = (sop2531 << 5) | op0711; ] { local tmp:$(XLEN) = imm; export tmp; } + +# used for goto +immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export *[ram]:$(XLEN) reloc; } +#immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export reloc; } + +#NOTES this reads as '<< 12' but objdump does not +# immU: imm is sop1231 [ imm = (sop1231 << 12); ] { local tmp:$(XLEN) = imm; export tmp; } +immU: sop1231 is sop1231 { local tmp:$(XLEN) = sop1231; export tmp; } + +# used for goto +immUJ: reloc is op1219 & op2020 & op2130 & sop3131 [ reloc = inst_start + ((sop3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12)); ] { export *[ram]:$(XLEN) reloc; } + +@if ADDRSIZE == "64" +shamt5: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; } +@endif + +shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:$(XLEN) = imm; export tmp; } + +FRM: "rne" is op1214=0 { local tmp:1 = 0; export tmp; } +FRM: "rtz" is op1214=1 { local tmp:1 = 1; export tmp; } +FRM: "rdn" is op1214=2 { local tmp:1 = 2; export tmp; } +FRM: "rup" is op1214=3 { local tmp:1 = 3; export tmp; } +FRM: "rmm" is op1214=4 { local tmp:1 = 4; export tmp; } +# 5 Invalid. Reserved for future use +# 6 Invalid. Reserved for future use +FRM: "dyn" is op1214=7 { local tmp:1 = 7; export tmp; } + +aqrl: "" is op2526=0 {} +aqrl: ".rl" is op2526=1 {} +aqrl: ".aq" is op2526=2 {} +aqrl: ".aqrl" is op2526=3 {} + + + +crs1: cr0711 is cr0711 & cop0711!=0 { export cr0711; } +crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); } + +crd: cd0711 is cd0711 & cop0711!=0 { export cd0711; } +crd: zero is cd0711 & zero & cop0711=0 { export 0:$(XLEN); } + +crs2: cr0206 is cr0206 & cop0206!=0 { export cr0206; } +crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); } + +@if FPSIZE != "" +cfrs1: cfr0711 is cfr0711 { export cfr0711; } + +cfrd: cfr0711 is cfr0711 { export cfr0711; } + +cfrs2: cfr0206 is cfr0206 { export cfr0206; } +@endif + +#ATTN Not doing tables for the RVC registers since there is no +# zero register to worry about + + + +cimmI: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; } + +# used for goto +cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export *[ram]:$(XLEN) reloc; } +#cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export reloc; } + +# used for goto +cjimm: reloc is scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202 [ reloc = inst_start + ((scop1212 << 11) | (cop1111 << 4) | (cop0910 << 8) | (cop0808 << 10) | (cop0707 << 6) | (cop0606 << 7) | (cop0305 << 1) | (cop0202 << 5)); ] { export *[ram]:$(XLEN) reloc; } + +@if ADDRSIZE == "32" +#TODO nonzero, would like to have cop0205>0 +c6imm: uimm is cop1212=0 & cop0206 [ uimm = (cop0206 + 0); ] { local tmp:$(XLEN) = uimm; export tmp; } +@elif ADDRSIZE == "64" +#TODO nonzero, would like to have cop0205>0 | cop0206>0 +c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm; export tmp; } +@elif ADDRSIZE == "128" +c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm + (64 * (uimm == 0)); export tmp; } +@endif + +#NOTES not shifted +# cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 17) | (cop0206 << 12); ] { local tmp:$(XLEN) = imm; export tmp; } +cbigimm: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; } + +caddi4spnimm: uimm is cop1112 & cop0710 & cop0606 & cop0505 [ uimm = (cop0710 << 6) | (cop1112 << 4) | (cop0505 << 3) | (cop0606 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; } + +caddi16spimm: imm is scop1212 & cop0606 & cop0505 & cop0304 & cop0202 [ imm = (scop1212 << 9) | (cop0304 << 7) | (cop0505 << 6) | (cop0202 << 5) | (cop0606 << 4); ] { local tmp:$(XLEN) = imm; export tmp; } + + +cldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +clwimm: uimm is cop1012 & cop0606 & cop0505 [ uimm = (cop1012 << 3) | (cop0606 << 2) | (cop0505 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +clqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +cldspimm: uimm is cop1212 & cop0506 & cop0204 [ uimm = (cop1212 << 5) | (cop0506 << 3) | (cop0204 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +@if ADDRSIZE == "64" +clqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } +@endif + +clwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +csdspimm: uimm is cop0709 & cop1012 [ uimm = (cop0709 << 6) | (cop1012 << 3); ] { local tmp:$(XLEN) = uimm; export tmp; } + +@if ADDRSIZE == "128" +csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; } +@endif + +cswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; } + + + +#TODO this is broken +#TODO maybe 2 tables are needed for address and size +# instead of register name +# CSR have different access level, use, and accessibility +# just formatting this way for readability. Breaking up +# csr into multiples to avoid having an 'attach variables' +# with 0x1000 fields +# SEE riscv-privileged.pdf Section 'CSR Listing' for description + +# 0x000-0x0ff +with csr: op3031=0 & op2829=0 { + : csr_0 is csr_0 {} +} + +# 0x100-0x1ff +with csr: op3031=0 & op2829=1 { + : csr_1 is csr_1 {} +} + +# 0x200-0x2ff +with csr: op3031=0 & op2829=2 { + : csr_2 is csr_2 {} +} + +# 0x300-0x3ff +with csr: op3031=0 & op2829=3 { + : csr_3 is csr_3 {} +} + +# 0x400-0x4ff +with csr: op3031=1 & op2829=0 { + : csr_4 is csr_4 {} +} + +# 0x500-0x5ff +with csr: op3031=1 & op2829=1 { + : csr_50 is csr_50 & op2727=0 {} + : csr_58 is csr_58 & op2627=2 {} + : csr_5C is csr_5C & op2627=3 {} +} + +# 0x600-0x6ff +with csr: op3031=1 & op2829=2 { + : csr_60 is csr_60 & op2727=0 {} + : csr_68 is csr_68 & op2627=2 {} + : csr_6C is csr_6C & op2627=3 {} +} + +# 0x700-0x7ff +with csr: op3031=1 & op2829=3 { + : csr_70 is csr_70 & op2727=0 {} + : csr_78 is csr_78 & op2527=4 {} + : csr_7A is csr_7A & op2427=0xa {} + : csr_7B is csr_7B & op2427=0xb {} + : csr_7C is csr_7C & op2627=3 {} +} + +# 0x800-0x8ff +with csr: op3031=2 & op2829=0 { + : csr_8 is csr_8 {} +} + +# 0x900-0x9ff +with csr: op3031=2 & op2829=1 { + : csr_90 is csr_90 & op2727=0 {} + : csr_98 is csr_98 & op2627=2 {} + : csr_9C is csr_9C & op2627=3 {} +} + +# 0xa00-0xaff +with csr: op3031=2 & op2829=2 { + : csr_A0 is csr_A0 & op2727=0 {} + : csr_A8 is csr_A8 & op2627=2 {} + : csr_AC is csr_AC & op2627=3 {} +} + +# 0xb00-0xbff +with csr: op3031=2 & op2829=3 { + : csr_B0 is csr_B0 & op2727=0 {} + : csr_B8 is csr_B8 & op2627=2 {} + : csr_BC is csr_BC & op2627=3 {} +} + +# 0xc00-0xcff +with csr: op3031=3 & op2829=0 { + : csr_C0 is csr_C0 & op2727=0 {} + : csr_C8 is csr_C8 & op2627=2 {} + : csr_CC is csr_CC & op2627=3 {} +} + +# 0xd00-0xdff +with csr: op3031=3 & op2829=1 { + : csr_D0 is csr_D0 & op2727=0 {} + : csr_D8 is csr_D8 & op2627=2 {} + : csr_DC is csr_DC & op2627=3 {} +} + +# 0xe00-0xeff +with csr: op3031=3 & op2829=2 { + : csr_E0 is csr_E0 & op2727=0 {} + : csr_E8 is csr_E8 & op2627=2 {} + : csr_EC is csr_EC & op2627=3 {} +} + +# 0xf00-0xfff +with csr: op3031=3 & op2829=3 { + : csr_F0 is csr_F0 & op2727=0 {} + : csr_F8 is csr_F8 & op2627=2 {} + : csr_FC is csr_FC & op2627=3 {} +} diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc new file mode 100644 index 0000000000..c0963b74a7 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc @@ -0,0 +1,6 @@ +# RV32/RV64 Zifencei Standard Extension + +# fence.i 0000100f ffffffff SIMPLE (0, 0) +:fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0 +{ +} \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec new file mode 100644 index 0000000000..19f0f17fe1 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf new file mode 100644 index 0000000000..f136b11870 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv32-fp.dwarf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32.cspec b/Ghidra/Processors/RISCV/data/languages/riscv32.cspec new file mode 100644 index 0000000000..86b26740cf --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv32.cspec @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf new file mode 100644 index 0000000000..31074ccdd8 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec new file mode 100644 index 0000000000..e0a5117fe7 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf new file mode 100644 index 0000000000..ee3e8fa4bf --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv64-fp.dwarf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64.cspec b/Ghidra/Processors/RISCV/data/languages/riscv64.cspec new file mode 100644 index 0000000000..b2f88d4cae --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv64.cspec @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf b/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf new file mode 100644 index 0000000000..b147720559 --- /dev/null +++ b/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/RISCV/scripts/binutil.py b/Ghidra/Processors/RISCV/scripts/binutil.py new file mode 100644 index 0000000000..7ebffaf5a3 --- /dev/null +++ b/Ghidra/Processors/RISCV/scripts/binutil.py @@ -0,0 +1,2871 @@ +#!/usr/bin/env python3 +"""Script to generate base RISC-V SLEIGH for Ghidra module + +Just an artifact to keep around for the development at this point as a lot of +cleanup and reorganization was done after generating the intial SLEIGH. + +Data was copied from various files in binutils, a lot of it unused. +""" + +import sys +import re + +MATCH_SLLI_RV32=0x1013 +MASK_SLLI_RV32=0xfe00707f +MATCH_SRLI_RV32=0x5013 +MASK_SRLI_RV32=0xfe00707f +MATCH_SRAI_RV32=0x40005013 +MASK_SRAI_RV32=0xfe00707f +MATCH_FRFLAGS=0x102073 +MASK_FRFLAGS=0xfffff07f +MATCH_FSFLAGS=0x101073 +MASK_FSFLAGS=0xfff0707f +MATCH_FSFLAGSI=0x105073 +MASK_FSFLAGSI=0xfff0707f +MATCH_FRRM=0x202073 +MASK_FRRM=0xfffff07f +MATCH_FSRM=0x201073 +MASK_FSRM=0xfff0707f +MATCH_FSRMI=0x205073 +MASK_FSRMI=0xfff0707f +MATCH_FSCSR=0x301073 +MASK_FSCSR=0xfff0707f +MATCH_FRCSR=0x302073 +MASK_FRCSR=0xfffff07f +MATCH_RDCYCLE=0xc0002073 +MASK_RDCYCLE=0xfffff07f +MATCH_RDTIME=0xc0102073 +MASK_RDTIME=0xfffff07f +MATCH_RDINSTRET=0xc0202073 +MASK_RDINSTRET=0xfffff07f +MATCH_RDCYCLEH=0xc8002073 +MASK_RDCYCLEH=0xfffff07f +MATCH_RDTIMEH=0xc8102073 +MASK_RDTIMEH=0xfffff07f +MATCH_RDINSTRETH=0xc8202073 +MASK_RDINSTRETH=0xfffff07f +MATCH_SCALL=0x73 +MASK_SCALL=0xffffffff +MATCH_SBREAK=0x100073 +MASK_SBREAK=0xffffffff +MATCH_BEQ=0x63 +MASK_BEQ=0x707f +MATCH_BNE=0x1063 +MASK_BNE=0x707f +MATCH_BLT=0x4063 +MASK_BLT=0x707f +MATCH_BGE=0x5063 +MASK_BGE=0x707f +MATCH_BLTU=0x6063 +MASK_BLTU=0x707f +MATCH_BGEU=0x7063 +MASK_BGEU=0x707f +MATCH_JALR=0x67 +MASK_JALR=0x707f +MATCH_JAL=0x6f +MASK_JAL=0x7f +MATCH_LUI=0x37 +MASK_LUI=0x7f +MATCH_AUIPC=0x17 +MASK_AUIPC=0x7f +MATCH_ADDI=0x13 +MASK_ADDI=0x707f +MATCH_SLLI=0x1013 +MASK_SLLI=0xfc00707f +MATCH_SLTI=0x2013 +MASK_SLTI=0x707f +MATCH_SLTIU=0x3013 +MASK_SLTIU=0x707f +MATCH_XORI=0x4013 +MASK_XORI=0x707f +MATCH_SRLI=0x5013 +MASK_SRLI=0xfc00707f +MATCH_SRAI=0x40005013 +MASK_SRAI=0xfc00707f +MATCH_ORI=0x6013 +MASK_ORI=0x707f +MATCH_ANDI=0x7013 +MASK_ANDI=0x707f +MATCH_ADD=0x33 +MASK_ADD=0xfe00707f +MATCH_SUB=0x40000033 +MASK_SUB=0xfe00707f +MATCH_SLL=0x1033 +MASK_SLL=0xfe00707f +MATCH_SLT=0x2033 +MASK_SLT=0xfe00707f +MATCH_SLTU=0x3033 +MASK_SLTU=0xfe00707f +MATCH_XOR=0x4033 +MASK_XOR=0xfe00707f +MATCH_SRL=0x5033 +MASK_SRL=0xfe00707f +MATCH_SRA=0x40005033 +MASK_SRA=0xfe00707f +MATCH_OR=0x6033 +MASK_OR=0xfe00707f +MATCH_AND=0x7033 +MASK_AND=0xfe00707f +MATCH_ADDIW=0x1b +MASK_ADDIW=0x707f +MATCH_SLLIW=0x101b +MASK_SLLIW=0xfe00707f +MATCH_SRLIW=0x501b +MASK_SRLIW=0xfe00707f +MATCH_SRAIW=0x4000501b +MASK_SRAIW=0xfe00707f +MATCH_ADDW=0x3b +MASK_ADDW=0xfe00707f +MATCH_SUBW=0x4000003b +MASK_SUBW=0xfe00707f +MATCH_SLLW=0x103b +MASK_SLLW=0xfe00707f +MATCH_SRLW=0x503b +MASK_SRLW=0xfe00707f +MATCH_SRAW=0x4000503b +MASK_SRAW=0xfe00707f +MATCH_LB=0x3 +MASK_LB=0x707f +MATCH_LH=0x1003 +MASK_LH=0x707f +MATCH_LW=0x2003 +MASK_LW=0x707f +MATCH_LD=0x3003 +MASK_LD=0x707f +MATCH_LBU=0x4003 +MASK_LBU=0x707f +MATCH_LHU=0x5003 +MASK_LHU=0x707f +MATCH_LWU=0x6003 +MASK_LWU=0x707f +MATCH_SB=0x23 +MASK_SB=0x707f +MATCH_SH=0x1023 +MASK_SH=0x707f +MATCH_SW=0x2023 +MASK_SW=0x707f +MATCH_SD=0x3023 +MASK_SD=0x707f +MATCH_FENCE=0xf +MASK_FENCE=0x707f +MATCH_FENCE_I=0x100f +MASK_FENCE_I=0x707f +MATCH_FENCE_TSO=0x8330000f +MASK_FENCE_TSO=0xfff0707f +MATCH_MUL=0x2000033 +MASK_MUL=0xfe00707f +MATCH_MULH=0x2001033 +MASK_MULH=0xfe00707f +MATCH_MULHSU=0x2002033 +MASK_MULHSU=0xfe00707f +MATCH_MULHU=0x2003033 +MASK_MULHU=0xfe00707f +MATCH_DIV=0x2004033 +MASK_DIV=0xfe00707f +MATCH_DIVU=0x2005033 +MASK_DIVU=0xfe00707f +MATCH_REM=0x2006033 +MASK_REM=0xfe00707f +MATCH_REMU=0x2007033 +MASK_REMU=0xfe00707f +MATCH_MULW=0x200003b +MASK_MULW=0xfe00707f +MATCH_DIVW=0x200403b +MASK_DIVW=0xfe00707f +MATCH_DIVUW=0x200503b +MASK_DIVUW=0xfe00707f +MATCH_REMW=0x200603b +MASK_REMW=0xfe00707f +MATCH_REMUW=0x200703b +MASK_REMUW=0xfe00707f +MATCH_AMOADD_W=0x202f +MASK_AMOADD_W=0xf800707f +MATCH_AMOXOR_W=0x2000202f +MASK_AMOXOR_W=0xf800707f +MATCH_AMOOR_W=0x4000202f +MASK_AMOOR_W=0xf800707f +MATCH_AMOAND_W=0x6000202f +MASK_AMOAND_W=0xf800707f +MATCH_AMOMIN_W=0x8000202f +MASK_AMOMIN_W=0xf800707f +MATCH_AMOMAX_W=0xa000202f +MASK_AMOMAX_W=0xf800707f +MATCH_AMOMINU_W=0xc000202f +MASK_AMOMINU_W=0xf800707f +MATCH_AMOMAXU_W=0xe000202f +MASK_AMOMAXU_W=0xf800707f +MATCH_AMOSWAP_W=0x800202f +MASK_AMOSWAP_W=0xf800707f +MATCH_LR_W=0x1000202f +MASK_LR_W=0xf9f0707f +MATCH_SC_W=0x1800202f +MASK_SC_W=0xf800707f +MATCH_AMOADD_D=0x302f +MASK_AMOADD_D=0xf800707f +MATCH_AMOXOR_D=0x2000302f +MASK_AMOXOR_D=0xf800707f +MATCH_AMOOR_D=0x4000302f +MASK_AMOOR_D=0xf800707f +MATCH_AMOAND_D=0x6000302f +MASK_AMOAND_D=0xf800707f +MATCH_AMOMIN_D=0x8000302f +MASK_AMOMIN_D=0xf800707f +MATCH_AMOMAX_D=0xa000302f +MASK_AMOMAX_D=0xf800707f +MATCH_AMOMINU_D=0xc000302f +MASK_AMOMINU_D=0xf800707f +MATCH_AMOMAXU_D=0xe000302f +MASK_AMOMAXU_D=0xf800707f +MATCH_AMOSWAP_D=0x800302f +MASK_AMOSWAP_D=0xf800707f +MATCH_LR_D=0x1000302f +MASK_LR_D=0xf9f0707f +MATCH_SC_D=0x1800302f +MASK_SC_D=0xf800707f +MATCH_ECALL=0x73 +MASK_ECALL=0xffffffff +MATCH_EBREAK=0x100073 +MASK_EBREAK=0xffffffff +MATCH_URET=0x200073 +MASK_URET=0xffffffff +MATCH_SRET=0x10200073 +MASK_SRET=0xffffffff +MATCH_HRET=0x20200073 +MASK_HRET=0xffffffff +MATCH_MRET=0x30200073 +MASK_MRET=0xffffffff +MATCH_DRET=0x7b200073 +MASK_DRET=0xffffffff +MATCH_SFENCE_VM=0x10400073 +MASK_SFENCE_VM=0xfff07fff +MATCH_SFENCE_VMA=0x12000073 +MASK_SFENCE_VMA=0xfe007fff +MATCH_WFI=0x10500073 +MASK_WFI=0xffffffff +MATCH_CSRRW=0x1073 +MASK_CSRRW=0x707f +MATCH_CSRRS=0x2073 +MASK_CSRRS=0x707f +MATCH_CSRRC=0x3073 +MASK_CSRRC=0x707f +MATCH_CSRRWI=0x5073 +MASK_CSRRWI=0x707f +MATCH_CSRRSI=0x6073 +MASK_CSRRSI=0x707f +MATCH_CSRRCI=0x7073 +MASK_CSRRCI=0x707f +MATCH_FADD_S=0x53 +MASK_FADD_S=0xfe00007f +MATCH_FSUB_S=0x8000053 +MASK_FSUB_S=0xfe00007f +MATCH_FMUL_S=0x10000053 +MASK_FMUL_S=0xfe00007f +MATCH_FDIV_S=0x18000053 +MASK_FDIV_S=0xfe00007f +MATCH_FSGNJ_S=0x20000053 +MASK_FSGNJ_S=0xfe00707f +MATCH_FSGNJN_S=0x20001053 +MASK_FSGNJN_S=0xfe00707f +MATCH_FSGNJX_S=0x20002053 +MASK_FSGNJX_S=0xfe00707f +MATCH_FMIN_S=0x28000053 +MASK_FMIN_S=0xfe00707f +MATCH_FMAX_S=0x28001053 +MASK_FMAX_S=0xfe00707f +MATCH_FSQRT_S=0x58000053 +MASK_FSQRT_S=0xfff0007f +MATCH_FADD_D=0x2000053 +MASK_FADD_D=0xfe00007f +MATCH_FSUB_D=0xa000053 +MASK_FSUB_D=0xfe00007f +MATCH_FMUL_D=0x12000053 +MASK_FMUL_D=0xfe00007f +MATCH_FDIV_D=0x1a000053 +MASK_FDIV_D=0xfe00007f +MATCH_FSGNJ_D=0x22000053 +MASK_FSGNJ_D=0xfe00707f +MATCH_FSGNJN_D=0x22001053 +MASK_FSGNJN_D=0xfe00707f +MATCH_FSGNJX_D=0x22002053 +MASK_FSGNJX_D=0xfe00707f +MATCH_FMIN_D=0x2a000053 +MASK_FMIN_D=0xfe00707f +MATCH_FMAX_D=0x2a001053 +MASK_FMAX_D=0xfe00707f +MATCH_FCVT_S_D=0x40100053 +MASK_FCVT_S_D=0xfff0007f +MATCH_FCVT_D_S=0x42000053 +MASK_FCVT_D_S=0xfff0007f +MATCH_FSQRT_D=0x5a000053 +MASK_FSQRT_D=0xfff0007f +MATCH_FADD_Q=0x6000053 +MASK_FADD_Q=0xfe00007f +MATCH_FSUB_Q=0xe000053 +MASK_FSUB_Q=0xfe00007f +MATCH_FMUL_Q=0x16000053 +MASK_FMUL_Q=0xfe00007f +MATCH_FDIV_Q=0x1e000053 +MASK_FDIV_Q=0xfe00007f +MATCH_FSGNJ_Q=0x26000053 +MASK_FSGNJ_Q=0xfe00707f +MATCH_FSGNJN_Q=0x26001053 +MASK_FSGNJN_Q=0xfe00707f +MATCH_FSGNJX_Q=0x26002053 +MASK_FSGNJX_Q=0xfe00707f +MATCH_FMIN_Q=0x2e000053 +MASK_FMIN_Q=0xfe00707f +MATCH_FMAX_Q=0x2e001053 +MASK_FMAX_Q=0xfe00707f +MATCH_FCVT_S_Q=0x40300053 +MASK_FCVT_S_Q=0xfff0007f +MATCH_FCVT_Q_S=0x46000053 +MASK_FCVT_Q_S=0xfff0007f +MATCH_FCVT_D_Q=0x42300053 +MASK_FCVT_D_Q=0xfff0007f +MATCH_FCVT_Q_D=0x46100053 +MASK_FCVT_Q_D=0xfff0007f +MATCH_FSQRT_Q=0x5e000053 +MASK_FSQRT_Q=0xfff0007f +MATCH_FLE_S=0xa0000053 +MASK_FLE_S=0xfe00707f +MATCH_FLT_S=0xa0001053 +MASK_FLT_S=0xfe00707f +MATCH_FEQ_S=0xa0002053 +MASK_FEQ_S=0xfe00707f +MATCH_FLE_D=0xa2000053 +MASK_FLE_D=0xfe00707f +MATCH_FLT_D=0xa2001053 +MASK_FLT_D=0xfe00707f +MATCH_FEQ_D=0xa2002053 +MASK_FEQ_D=0xfe00707f +MATCH_FLE_Q=0xa6000053 +MASK_FLE_Q=0xfe00707f +MATCH_FLT_Q=0xa6001053 +MASK_FLT_Q=0xfe00707f +MATCH_FEQ_Q=0xa6002053 +MASK_FEQ_Q=0xfe00707f +MATCH_FCVT_W_S=0xc0000053 +MASK_FCVT_W_S=0xfff0007f +MATCH_FCVT_WU_S=0xc0100053 +MASK_FCVT_WU_S=0xfff0007f +MATCH_FCVT_L_S=0xc0200053 +MASK_FCVT_L_S=0xfff0007f +MATCH_FCVT_LU_S=0xc0300053 +MASK_FCVT_LU_S=0xfff0007f +MATCH_FMV_X_S=0xe0000053 +MASK_FMV_X_S=0xfff0707f +MATCH_FCLASS_S=0xe0001053 +MASK_FCLASS_S=0xfff0707f +MATCH_FCVT_W_D=0xc2000053 +MASK_FCVT_W_D=0xfff0007f +MATCH_FCVT_WU_D=0xc2100053 +MASK_FCVT_WU_D=0xfff0007f +MATCH_FCVT_L_D=0xc2200053 +MASK_FCVT_L_D=0xfff0007f +MATCH_FCVT_LU_D=0xc2300053 +MASK_FCVT_LU_D=0xfff0007f +MATCH_FMV_X_D=0xe2000053 +MASK_FMV_X_D=0xfff0707f +MATCH_FCLASS_D=0xe2001053 +MASK_FCLASS_D=0xfff0707f +MATCH_FCVT_W_Q=0xc6000053 +MASK_FCVT_W_Q=0xfff0007f +MATCH_FCVT_WU_Q=0xc6100053 +MASK_FCVT_WU_Q=0xfff0007f +MATCH_FCVT_L_Q=0xc6200053 +MASK_FCVT_L_Q=0xfff0007f +MATCH_FCVT_LU_Q=0xc6300053 +MASK_FCVT_LU_Q=0xfff0007f +MATCH_FMV_X_Q=0xe6000053 +MASK_FMV_X_Q=0xfff0707f +MATCH_FCLASS_Q=0xe6001053 +MASK_FCLASS_Q=0xfff0707f +MATCH_FCVT_S_W=0xd0000053 +MASK_FCVT_S_W=0xfff0007f +MATCH_FCVT_S_WU=0xd0100053 +MASK_FCVT_S_WU=0xfff0007f +MATCH_FCVT_S_L=0xd0200053 +MASK_FCVT_S_L=0xfff0007f +MATCH_FCVT_S_LU=0xd0300053 +MASK_FCVT_S_LU=0xfff0007f +MATCH_FMV_S_X=0xf0000053 +MASK_FMV_S_X=0xfff0707f +MATCH_FCVT_D_W=0xd2000053 +MASK_FCVT_D_W=0xfff0007f +MATCH_FCVT_D_WU=0xd2100053 +MASK_FCVT_D_WU=0xfff0007f +MATCH_FCVT_D_L=0xd2200053 +MASK_FCVT_D_L=0xfff0007f +MATCH_FCVT_D_LU=0xd2300053 +MASK_FCVT_D_LU=0xfff0007f +MATCH_FMV_D_X=0xf2000053 +MASK_FMV_D_X=0xfff0707f +MATCH_FCVT_Q_W=0xd6000053 +MASK_FCVT_Q_W=0xfff0007f +MATCH_FCVT_Q_WU=0xd6100053 +MASK_FCVT_Q_WU=0xfff0007f +MATCH_FCVT_Q_L=0xd6200053 +MASK_FCVT_Q_L=0xfff0007f +MATCH_FCVT_Q_LU=0xd6300053 +MASK_FCVT_Q_LU=0xfff0007f +MATCH_FMV_Q_X=0xf6000053 +MASK_FMV_Q_X=0xfff0707f +MATCH_FLW=0x2007 +MASK_FLW=0x707f +MATCH_FLD=0x3007 +MASK_FLD=0x707f +MATCH_FLQ=0x4007 +MASK_FLQ=0x707f +MATCH_FSW=0x2027 +MASK_FSW=0x707f +MATCH_FSD=0x3027 +MASK_FSD=0x707f +MATCH_FSQ=0x4027 +MASK_FSQ=0x707f +MATCH_FMADD_S=0x43 +MASK_FMADD_S=0x600007f +MATCH_FMSUB_S=0x47 +MASK_FMSUB_S=0x600007f +MATCH_FNMSUB_S=0x4b +MASK_FNMSUB_S=0x600007f +MATCH_FNMADD_S=0x4f +MASK_FNMADD_S=0x600007f +MATCH_FMADD_D=0x2000043 +MASK_FMADD_D=0x600007f +MATCH_FMSUB_D=0x2000047 +MASK_FMSUB_D=0x600007f +MATCH_FNMSUB_D=0x200004b +MASK_FNMSUB_D=0x600007f +MATCH_FNMADD_D=0x200004f +MASK_FNMADD_D=0x600007f +MATCH_FMADD_Q=0x6000043 +MASK_FMADD_Q=0x600007f +MATCH_FMSUB_Q=0x6000047 +MASK_FMSUB_Q=0x600007f +MATCH_FNMSUB_Q=0x600004b +MASK_FNMSUB_Q=0x600007f +MATCH_FNMADD_Q=0x600004f +MASK_FNMADD_Q=0x600007f +MATCH_C_ADDI4SPN=0x0 +MASK_C_ADDI4SPN=0xe003 +MATCH_C_FLD=0x2000 +MASK_C_FLD=0xe003 +MATCH_C_LW=0x4000 +MASK_C_LW=0xe003 +MATCH_C_FLW=0x6000 +MASK_C_FLW=0xe003 +MATCH_C_FSD=0xa000 +MASK_C_FSD=0xe003 +MATCH_C_SW=0xc000 +MASK_C_SW=0xe003 +MATCH_C_FSW=0xe000 +MASK_C_FSW=0xe003 +MATCH_C_ADDI=0x1 +MASK_C_ADDI=0xe003 +MATCH_C_JAL=0x2001 +MASK_C_JAL=0xe003 +MATCH_C_LI=0x4001 +MASK_C_LI=0xe003 +MATCH_C_LUI=0x6001 +MASK_C_LUI=0xe003 +MATCH_C_SRLI=0x8001 +MASK_C_SRLI=0xec03 +MATCH_C_SRLI64=0x8001 +MASK_C_SRLI64=0xfc7f +MATCH_C_SRAI=0x8401 +MASK_C_SRAI=0xec03 +MATCH_C_SRAI64=0x8401 +MASK_C_SRAI64=0xfc7f +MATCH_C_ANDI=0x8801 +MASK_C_ANDI=0xec03 +MATCH_C_SUB=0x8c01 +MASK_C_SUB=0xfc63 +MATCH_C_XOR=0x8c21 +MASK_C_XOR=0xfc63 +MATCH_C_OR=0x8c41 +MASK_C_OR=0xfc63 +MATCH_C_AND=0x8c61 +MASK_C_AND=0xfc63 +MATCH_C_SUBW=0x9c01 +MASK_C_SUBW=0xfc63 +MATCH_C_ADDW=0x9c21 +MASK_C_ADDW=0xfc63 +MATCH_C_J=0xa001 +MASK_C_J=0xe003 +MATCH_C_BEQZ=0xc001 +MASK_C_BEQZ=0xe003 +MATCH_C_BNEZ=0xe001 +MASK_C_BNEZ=0xe003 +MATCH_C_SLLI=0x2 +MASK_C_SLLI=0xe003 +MATCH_C_SLLI64=0x2 +MASK_C_SLLI64=0xf07f +MATCH_C_FLDSP=0x2002 +MASK_C_FLDSP=0xe003 +MATCH_C_LWSP=0x4002 +MASK_C_LWSP=0xe003 +MATCH_C_FLWSP=0x6002 +MASK_C_FLWSP=0xe003 +MATCH_C_MV=0x8002 +MASK_C_MV=0xf003 +MATCH_C_ADD=0x9002 +MASK_C_ADD=0xf003 +MATCH_C_FSDSP=0xa002 +MASK_C_FSDSP=0xe003 +MATCH_C_SWSP=0xc002 +MASK_C_SWSP=0xe003 +MATCH_C_FSWSP=0xe002 +MASK_C_FSWSP=0xe003 +MATCH_C_NOP=0x1 +MASK_C_NOP=0xffff +MATCH_C_ADDI16SP=0x6101 +MASK_C_ADDI16SP=0xef83 +MATCH_C_JR=0x8002 +MASK_C_JR=0xf07f +MATCH_C_JALR=0x9002 +MASK_C_JALR=0xf07f +MATCH_C_EBREAK=0x9002 +MASK_C_EBREAK=0xffff +MATCH_C_LD=0x6000 +MASK_C_LD=0xe003 +MATCH_C_SD=0xe000 +MASK_C_SD=0xe003 +MATCH_C_ADDIW=0x2001 +MASK_C_ADDIW=0xe003 +MATCH_C_LDSP=0x6002 +MASK_C_LDSP=0xe003 +MATCH_C_SDSP=0xe002 +MASK_C_SDSP=0xe003 +MATCH_CUSTOM0=0xb +MASK_CUSTOM0=0x707f +MATCH_CUSTOM0_RS1=0x200b +MASK_CUSTOM0_RS1=0x707f +MATCH_CUSTOM0_RS1_RS2=0x300b +MASK_CUSTOM0_RS1_RS2=0x707f +MATCH_CUSTOM0_RD=0x400b +MASK_CUSTOM0_RD=0x707f +MATCH_CUSTOM0_RD_RS1=0x600b +MASK_CUSTOM0_RD_RS1=0x707f +MATCH_CUSTOM0_RD_RS1_RS2=0x700b +MASK_CUSTOM0_RD_RS1_RS2=0x707f +MATCH_CUSTOM1=0x2b +MASK_CUSTOM1=0x707f +MATCH_CUSTOM1_RS1=0x202b +MASK_CUSTOM1_RS1=0x707f +MATCH_CUSTOM1_RS1_RS2=0x302b +MASK_CUSTOM1_RS1_RS2=0x707f +MATCH_CUSTOM1_RD=0x402b +MASK_CUSTOM1_RD=0x707f +MATCH_CUSTOM1_RD_RS1=0x602b +MASK_CUSTOM1_RD_RS1=0x707f +MATCH_CUSTOM1_RD_RS1_RS2=0x702b +MASK_CUSTOM1_RD_RS1_RS2=0x707f +MATCH_CUSTOM2=0x5b +MASK_CUSTOM2=0x707f +MATCH_CUSTOM2_RS1=0x205b +MASK_CUSTOM2_RS1=0x707f +MATCH_CUSTOM2_RS1_RS2=0x305b +MASK_CUSTOM2_RS1_RS2=0x707f +MATCH_CUSTOM2_RD=0x405b +MASK_CUSTOM2_RD=0x707f +MATCH_CUSTOM2_RD_RS1=0x605b +MASK_CUSTOM2_RD_RS1=0x707f +MATCH_CUSTOM2_RD_RS1_RS2=0x705b +MASK_CUSTOM2_RD_RS1_RS2=0x707f +MATCH_CUSTOM3=0x7b +MASK_CUSTOM3=0x707f +MATCH_CUSTOM3_RS1=0x207b +MASK_CUSTOM3_RS1=0x707f +MATCH_CUSTOM3_RS1_RS2=0x307b +MASK_CUSTOM3_RS1_RS2=0x707f +MATCH_CUSTOM3_RD=0x407b +MASK_CUSTOM3_RD=0x707f +MATCH_CUSTOM3_RD_RS1=0x607b +MASK_CUSTOM3_RD_RS1=0x707f +MATCH_CUSTOM3_RD_RS1_RS2=0x707b +MASK_CUSTOM3_RD_RS1_RS2=0x707f +CSR_USTATUS=0x0 +CSR_UIE=0x4 +CSR_UTVEC=0x5 +CSR_USCRATCH=0x40 +CSR_UEPC=0x41 +CSR_UCAUSE=0x42 +CSR_UTVAL=0x43 +CSR_UIP=0x44 +CSR_FFLAGS=0x1 +CSR_FRM=0x2 +CSR_FCSR=0x3 +CSR_CYCLE=0xc00 +CSR_TIME=0xc01 +CSR_INSTRET=0xc02 +CSR_HPMCOUNTER3=0xc03 +CSR_HPMCOUNTER4=0xc04 +CSR_HPMCOUNTER5=0xc05 +CSR_HPMCOUNTER6=0xc06 +CSR_HPMCOUNTER7=0xc07 +CSR_HPMCOUNTER8=0xc08 +CSR_HPMCOUNTER9=0xc09 +CSR_HPMCOUNTER10=0xc0a +CSR_HPMCOUNTER11=0xc0b +CSR_HPMCOUNTER12=0xc0c +CSR_HPMCOUNTER13=0xc0d +CSR_HPMCOUNTER14=0xc0e +CSR_HPMCOUNTER15=0xc0f +CSR_HPMCOUNTER16=0xc10 +CSR_HPMCOUNTER17=0xc11 +CSR_HPMCOUNTER18=0xc12 +CSR_HPMCOUNTER19=0xc13 +CSR_HPMCOUNTER20=0xc14 +CSR_HPMCOUNTER21=0xc15 +CSR_HPMCOUNTER22=0xc16 +CSR_HPMCOUNTER23=0xc17 +CSR_HPMCOUNTER24=0xc18 +CSR_HPMCOUNTER25=0xc19 +CSR_HPMCOUNTER26=0xc1a +CSR_HPMCOUNTER27=0xc1b +CSR_HPMCOUNTER28=0xc1c +CSR_HPMCOUNTER29=0xc1d +CSR_HPMCOUNTER30=0xc1e +CSR_HPMCOUNTER31=0xc1f +CSR_CYCLEH=0xc80 +CSR_TIMEH=0xc81 +CSR_INSTRETH=0xc82 +CSR_HPMCOUNTER3H=0xc83 +CSR_HPMCOUNTER4H=0xc84 +CSR_HPMCOUNTER5H=0xc85 +CSR_HPMCOUNTER6H=0xc86 +CSR_HPMCOUNTER7H=0xc87 +CSR_HPMCOUNTER8H=0xc88 +CSR_HPMCOUNTER9H=0xc89 +CSR_HPMCOUNTER10H=0xc8a +CSR_HPMCOUNTER11H=0xc8b +CSR_HPMCOUNTER12H=0xc8c +CSR_HPMCOUNTER13H=0xc8d +CSR_HPMCOUNTER14H=0xc8e +CSR_HPMCOUNTER15H=0xc8f +CSR_HPMCOUNTER16H=0xc90 +CSR_HPMCOUNTER17H=0xc91 +CSR_HPMCOUNTER18H=0xc92 +CSR_HPMCOUNTER19H=0xc93 +CSR_HPMCOUNTER20H=0xc94 +CSR_HPMCOUNTER21H=0xc95 +CSR_HPMCOUNTER22H=0xc96 +CSR_HPMCOUNTER23H=0xc97 +CSR_HPMCOUNTER24H=0xc98 +CSR_HPMCOUNTER25H=0xc99 +CSR_HPMCOUNTER26H=0xc9a +CSR_HPMCOUNTER27H=0xc9b +CSR_HPMCOUNTER28H=0xc9c +CSR_HPMCOUNTER29H=0xc9d +CSR_HPMCOUNTER30H=0xc9e +CSR_HPMCOUNTER31H=0xc9f +CSR_SSTATUS=0x100 +CSR_SEDELEG=0x102 +CSR_SIDELEG=0x103 +CSR_SIE=0x104 +CSR_STVEC=0x105 +CSR_SCOUNTEREN=0x106 +CSR_SSCRATCH=0x140 +CSR_SEPC=0x141 +CSR_SCAUSE=0x142 +CSR_STVAL=0x143 +CSR_SIP=0x144 +CSR_SATP=0x180 +CSR_MVENDORID=0xf11 +CSR_MARCHID=0xf12 +CSR_MIMPID=0xf13 +CSR_MHARTID=0xf14 +CSR_MSTATUS=0x300 +CSR_MISA=0x301 +CSR_MEDELEG=0x302 +CSR_MIDELEG=0x303 +CSR_MIE=0x304 +CSR_MTVEC=0x305 +CSR_MCOUNTEREN=0x306 +CSR_MSCRATCH=0x340 +CSR_MEPC=0x341 +CSR_MCAUSE=0x342 +CSR_MTVAL=0x343 +CSR_MIP=0x344 +CSR_PMPCFG0=0x3a0 +CSR_PMPCFG1=0x3a1 +CSR_PMPCFG2=0x3a2 +CSR_PMPCFG3=0x3a3 +CSR_PMPADDR0=0x3b0 +CSR_PMPADDR1=0x3b1 +CSR_PMPADDR2=0x3b2 +CSR_PMPADDR3=0x3b3 +CSR_PMPADDR4=0x3b4 +CSR_PMPADDR5=0x3b5 +CSR_PMPADDR6=0x3b6 +CSR_PMPADDR7=0x3b7 +CSR_PMPADDR8=0x3b8 +CSR_PMPADDR9=0x3b9 +CSR_PMPADDR10=0x3ba +CSR_PMPADDR11=0x3bb +CSR_PMPADDR12=0x3bc +CSR_PMPADDR13=0x3bd +CSR_PMPADDR14=0x3be +CSR_PMPADDR15=0x3bf +CSR_MCYCLE=0xb00 +CSR_MINSTRET=0xb02 +CSR_MHPMCOUNTER3=0xb03 +CSR_MHPMCOUNTER4=0xb04 +CSR_MHPMCOUNTER5=0xb05 +CSR_MHPMCOUNTER6=0xb06 +CSR_MHPMCOUNTER7=0xb07 +CSR_MHPMCOUNTER8=0xb08 +CSR_MHPMCOUNTER9=0xb09 +CSR_MHPMCOUNTER10=0xb0a +CSR_MHPMCOUNTER11=0xb0b +CSR_MHPMCOUNTER12=0xb0c +CSR_MHPMCOUNTER13=0xb0d +CSR_MHPMCOUNTER14=0xb0e +CSR_MHPMCOUNTER15=0xb0f +CSR_MHPMCOUNTER16=0xb10 +CSR_MHPMCOUNTER17=0xb11 +CSR_MHPMCOUNTER18=0xb12 +CSR_MHPMCOUNTER19=0xb13 +CSR_MHPMCOUNTER20=0xb14 +CSR_MHPMCOUNTER21=0xb15 +CSR_MHPMCOUNTER22=0xb16 +CSR_MHPMCOUNTER23=0xb17 +CSR_MHPMCOUNTER24=0xb18 +CSR_MHPMCOUNTER25=0xb19 +CSR_MHPMCOUNTER26=0xb1a +CSR_MHPMCOUNTER27=0xb1b +CSR_MHPMCOUNTER28=0xb1c +CSR_MHPMCOUNTER29=0xb1d +CSR_MHPMCOUNTER30=0xb1e +CSR_MHPMCOUNTER31=0xb1f +CSR_MCYCLEH=0xb80 +CSR_MINSTRETH=0xb82 +CSR_MHPMCOUNTER3H=0xb83 +CSR_MHPMCOUNTER4H=0xb84 +CSR_MHPMCOUNTER5H=0xb85 +CSR_MHPMCOUNTER6H=0xb86 +CSR_MHPMCOUNTER7H=0xb87 +CSR_MHPMCOUNTER8H=0xb88 +CSR_MHPMCOUNTER9H=0xb89 +CSR_MHPMCOUNTER10H=0xb8a +CSR_MHPMCOUNTER11H=0xb8b +CSR_MHPMCOUNTER12H=0xb8c +CSR_MHPMCOUNTER13H=0xb8d +CSR_MHPMCOUNTER14H=0xb8e +CSR_MHPMCOUNTER15H=0xb8f +CSR_MHPMCOUNTER16H=0xb90 +CSR_MHPMCOUNTER17H=0xb91 +CSR_MHPMCOUNTER18H=0xb92 +CSR_MHPMCOUNTER19H=0xb93 +CSR_MHPMCOUNTER20H=0xb94 +CSR_MHPMCOUNTER21H=0xb95 +CSR_MHPMCOUNTER22H=0xb96 +CSR_MHPMCOUNTER23H=0xb97 +CSR_MHPMCOUNTER24H=0xb98 +CSR_MHPMCOUNTER25H=0xb99 +CSR_MHPMCOUNTER26H=0xb9a +CSR_MHPMCOUNTER27H=0xb9b +CSR_MHPMCOUNTER28H=0xb9c +CSR_MHPMCOUNTER29H=0xb9d +CSR_MHPMCOUNTER30H=0xb9e +CSR_MHPMCOUNTER31H=0xb9f +CSR_MHPMEVENT3=0x323 +CSR_MHPMEVENT4=0x324 +CSR_MHPMEVENT5=0x325 +CSR_MHPMEVENT6=0x326 +CSR_MHPMEVENT7=0x327 +CSR_MHPMEVENT8=0x328 +CSR_MHPMEVENT9=0x329 +CSR_MHPMEVENT10=0x32a +CSR_MHPMEVENT11=0x32b +CSR_MHPMEVENT12=0x32c +CSR_MHPMEVENT13=0x32d +CSR_MHPMEVENT14=0x32e +CSR_MHPMEVENT15=0x32f +CSR_MHPMEVENT16=0x330 +CSR_MHPMEVENT17=0x331 +CSR_MHPMEVENT18=0x332 +CSR_MHPMEVENT19=0x333 +CSR_MHPMEVENT20=0x334 +CSR_MHPMEVENT21=0x335 +CSR_MHPMEVENT22=0x336 +CSR_MHPMEVENT23=0x337 +CSR_MHPMEVENT24=0x338 +CSR_MHPMEVENT25=0x339 +CSR_MHPMEVENT26=0x33a +CSR_MHPMEVENT27=0x33b +CSR_MHPMEVENT28=0x33c +CSR_MHPMEVENT29=0x33d +CSR_MHPMEVENT30=0x33e +CSR_MHPMEVENT31=0x33f +CSR_TSELECT=0x7a0 +CSR_TDATA1=0x7a1 +CSR_TDATA2=0x7a2 +CSR_TDATA3=0x7a3 +CSR_DCSR=0x7b0 +CSR_DPC=0x7b1 +CSR_DSCRATCH=0x7b2 +CSR_HSTATUS=0x200 +CSR_HEDELEG=0x202 +CSR_HIDELEG=0x203 +CSR_HIE=0x204 +CSR_HTVEC=0x205 +CSR_HSCRATCH=0x240 +CSR_HEPC=0x241 +CSR_HCAUSE=0x242 +CSR_HBADADDR=0x243 +CSR_HIP=0x244 +CSR_MBASE=0x380 +CSR_MBOUND=0x381 +CSR_MIBASE=0x382 +CSR_MIBOUND=0x383 +CSR_MDBASE=0x384 +CSR_MDBOUND=0x385 +CSR_MUCOUNTEREN=0x320 +CSR_MSCOUNTEREN=0x321 +CSR_MHCOUNTEREN=0x322 +CAUSE_MISALIGNED_FETCH=0x0 +CAUSE_FAULT_FETCH=0x1 +CAUSE_ILLEGAL_INSTRUCTION=0x2 +CAUSE_BREAKPOINT=0x3 +CAUSE_MISALIGNED_LOAD=0x4 +CAUSE_FAULT_LOAD=0x5 +CAUSE_MISALIGNED_STORE=0x6 +CAUSE_FAULT_STORE=0x7 +CAUSE_USER_ECALL=0x8 +CAUSE_SUPERVISOR_ECALL=0x9 +CAUSE_HYPERVISOR_ECALL=0xa +CAUSE_MACHINE_ECALL=0xb + +MASK_RD=0x1f + +OP_MASK_OP=0x7f +OP_SH_OP=0 +OP_MASK_RS2=0x1f +OP_SH_RS2=20 +OP_MASK_RS1=0x1f +OP_SH_RS1=15 +OP_MASK_RS3=0x1f +OP_SH_RS3=27 +OP_MASK_RD=0x1f +OP_SH_RD=7 +OP_MASK_SHAMT=0x3f +OP_SH_SHAMT=20 +OP_MASK_SHAMTW=0x1f +OP_SH_SHAMTW=20 +OP_MASK_RM=0x7 +OP_SH_RM=12 +OP_MASK_PRED=0xf +OP_SH_PRED=24 +OP_MASK_SUCC=0xf +OP_SH_SUCC=20 +OP_MASK_AQ=0x1 +OP_SH_AQ=26 +OP_MASK_RL=0x1 +OP_SH_RL=25 +OP_MASK_CUSTOM_IMM=0x7f +OP_SH_CUSTOM_IMM=25 +OP_MASK_CSR=0xfff +OP_SH_CSR=20 +OP_MASK_FUNCT3=0x7 +OP_SH_FUNCT3=12 +OP_MASK_FUNCT7=0x7f +OP_SH_FUNCT7=25 +OP_MASK_FUNCT2=0x3 +OP_SH_FUNCT2=25 +OP_MASK_OP2=0x3 +OP_SH_OP2=0 + +OP_MASK_CRS2=0x1f +OP_SH_CRS2=2 +OP_MASK_CRS1S=0x7 +OP_SH_CRS1S=7 +OP_MASK_CRS2S=0x7 +OP_SH_CRS2S=2 + +OP_MASK_CFUNCT6=0x3f +OP_SH_CFUNCT6=10 +OP_MASK_CFUNCT4=0xf +OP_SH_CFUNCT4=12 +OP_MASK_CFUNCT3=0x7 +OP_SH_CFUNCT3=13 +OP_MASK_CFUNCT2=0x3 +OP_SH_CFUNCT2=5 + +M_LA=0 +M_LLA=1 +M_LA_TLS_GD=2 +M_LA_TLS_IE=3 +M_LB=4 +M_LBU=5 +M_LH=6 +M_LHU=7 +M_LW=8 +M_LWU=9 +M_LD=10 +M_SB=11 +M_SH=12 +M_SW=13 +M_SD=14 +M_FLW=15 +M_FLD=16 +M_FLQ=17 +M_FSW=18 +M_FSD=19 +M_FSQ=20 +M_CALL=21 +M_J=22 +M_LI=23 +M_NUM_MACROS=24 + + + +X_RA=1 +X_SP=2 +X_GP=3 +X_TP=4 +X_T0=5 +X_T1=6 +X_T2=7 +X_T3=28 + +NGPR=32 +NFPR=32 + + + + +ISAC = 1 +ISAI = 2 +ISAA = 3 +ISAM = 4 +ISAF = 5 +ISAFC = 6 +ISADC = 7 +ISAD = 8 +ISAQ = 9 + +INSN_TYPE=0x0000000e +INSN_MACRO=0xffffffff +INSN_ALIAS=0x00000001 +INSN_BRANCH=0x00000002 +INSN_CONDBRANCH=0x00000004 +INSN_JSR=0x00000006 +INSN_DREF=0x00000008 + + +INSN_DATA_SIZE=0x00000070 +INSN_DATA_SIZE_SHIFT=4 +INSN_1_BYTE=0x00000010 +INSN_2_BYTE=0x00000020 +INSN_4_BYTE=0x00000030 +INSN_8_BYTE=0x00000040 +INSN_16_BYTE=0x0000050 + + + + +def RV_X(x, s, n): + return (((x) >> (s)) & ((1 << (n)) - 1)) + +def RV_IMM_SIGN(x): + return (-(((x) >> 31) & 1)) + +def EXTRACT_ITYPE_IMM(x): + return (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) +def EXTRACT_STYPE_IMM(x): + return (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) +def EXTRACT_SBTYPE_IMM(x): + return ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) +def EXTRACT_UTYPE_IMM(x): + return ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) +def EXTRACT_UJTYPE_IMM(x): + return ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) +def EXTRACT_RVC_IMM(x): + return (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) +def EXTRACT_RVC_LUI_IMM(x): + return (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) +def EXTRACT_RVC_SIMM3(x): + return (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) +def EXTRACT_RVC_UIMM8(x): + return (RV_X(x, 5, 8)) +def EXTRACT_RVC_ADDI4SPN_IMM(x): + return ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) +def EXTRACT_RVC_ADDI16SP_IMM(x): + return ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) +def EXTRACT_RVC_LW_IMM(x): + return ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) +def EXTRACT_RVC_LD_IMM(x): + return ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) +def EXTRACT_RVC_LWSP_IMM(x): + return ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) +def EXTRACT_RVC_LDSP_IMM(x): + return ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) +def EXTRACT_RVC_SWSP_IMM(x): + return ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) +def EXTRACT_RVC_SDSP_IMM(x): + return ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) +def EXTRACT_RVC_B_IMM(x): + return ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) +def EXTRACT_RVC_J_IMM(x): + return ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) + +def ENCODE_ITYPE_IMM(x): + return (RV_X(x, 0, 12) << 20) +def ENCODE_STYPE_IMM(x): + return ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) +def ENCODE_SBTYPE_IMM(x): + return ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) +def ENCODE_UTYPE_IMM(x): + return (RV_X(x, 12, 20) << 12) +def ENCODE_UJTYPE_IMM(x): + return ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) +def ENCODE_RVC_IMM(x): + return ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) +def ENCODE_RVC_LUI_IMM(x): + return ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) +def ENCODE_RVC_SIMM3(x): + return (RV_X(x, 0, 3) << 10) +def ENCODE_RVC_UIMM8(x): + return (RV_X(x, 0, 8) << 5) +def ENCODE_RVC_ADDI4SPN_IMM(x): + return ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) +def ENCODE_RVC_ADDI16SP_IMM(x): + return ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) +def ENCODE_RVC_LW_IMM(x): + return ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) +def ENCODE_RVC_LD_IMM(x): + return ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) +def ENCODE_RVC_LWSP_IMM(x): + return ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) +def ENCODE_RVC_LDSP_IMM(x): + return ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) +def ENCODE_RVC_SWSP_IMM(x): + return ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) +def ENCODE_RVC_SDSP_IMM(x): + return ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) +def ENCODE_RVC_B_IMM(x): + return ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) +def ENCODE_RVC_J_IMM(x): + return ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) + + + +MASK_RS1= (OP_MASK_RS1 << OP_SH_RS1) +MASK_RS2= (OP_MASK_RS2 << OP_SH_RS2) +MASK_RD= (OP_MASK_RD << OP_SH_RD) +MASK_CRS2= (OP_MASK_CRS2 << OP_SH_CRS2) +MASK_IMM= ENCODE_ITYPE_IMM(-1) +MASK_RVC_IMM= ENCODE_RVC_IMM(-1) +MASK_UIMM= ENCODE_UTYPE_IMM(-1) +MASK_RM= (OP_MASK_RM << OP_SH_RM) +MASK_PRED= (OP_MASK_PRED << OP_SH_PRED) +MASK_SUCC= (OP_MASK_SUCC << OP_SH_SUCC) +MASK_AQ= (OP_MASK_AQ << OP_SH_AQ) +MASK_RL= (OP_MASK_RL << OP_SH_RL) +MASK_AQRL= (MASK_AQ | MASK_RL) + + +def match_opcode(op, insn): + print("match_opcode: %08x %08x %08x %08x %08x" % (op.match, op.mask, insn, insn ^ op.match, (insn ^ op.match) & op.mask)) + return ((insn ^ op.match) & op.mask) == 0 + +def match_never(op, insn): + return False + +def match_rs1_eq_rs2(op, insn): + rs1 = (insn & MASK_RS1) >> OP_SH_RS1 + rs2 = (insn & MASK_RS2) >> OP_SH_RS2 + return match_opcode(op, insn) and rs1 == rs2 + +def match_rd_nonzero(op, insn): + return match_opcode(op, insn) and ((insn & MASK_RD) != 0) + +def match_c_add(op, insn): + return match_rd_nonzero(op, insn) and ((insn & MASK_CRS2) != 0) + +def match_c_add_with_hint(op, insn): + return match_opcode(op, insn) and ((insn & MASK_CRS2) != 0) + +def match_c_nop(op, insn): + return match_opcode(op, insn) and (((insn & MASK_RD) >> OP_SH_RD) == 0) + +def match_c_add16sp(op, insn): + return match_opcode(op, insn) and (((insn & MASK_RD) >> OP_SH_RD) == 2) + +def match_c_lui(op, insn): + return False + +def match_c_addi4spn(op, insn): + return False + +def match_c_addi16sp(op, insn): + return False + +def match_slli_as_c_slli(op, insn): + return False + +def match_srxi_as_c_srxi(op, insn): + return False + +def match_c_lui_with_hint(op, insn): + return False + +def match_c_slli(op, insn): + return False + +def match_c_slli64(op, insn): + return False + + + +class OpCode: + def __init__(self, op): + self.name = op[0] + self.xlen = op[1] + self.isa = op[2] + self.operands = op[3] + self.match = op[4] + self.mask = op[5] + self.func = op[6] + self.pinfo = op[7] + self.size = 0 + if self.pinfo & INSN_DATA_SIZE: + self.size = ((self.pinfo & INSN_DATA_SIZE) >> INSN_DATA_SIZE_SHIFT) + self.size = 1 << (self.size - 1) + def __str__(self): + return "%s %s %08x %08x %08x (%d, %d) " % (self.name, self.operands, self.match, self.mask, self.pinfo, self.xlen, self.size) + def __eq__(self, other): + if other is None: + return False + if self.name != other.name: + return False + if self.mask != other.mask: + return False + if self.match != other.match: + return False + if self.operands != other.operands: + return False + if self.pinfo != other.pinfo: + return False + if self.xlen != other.xlen: + return False + return True + +# name, xlen, isa, operands, match, mask, match_func, pinfo +opcodes = [ + ("unimp", 0, ISAC, "", 0, 0xffff, match_opcode, INSN_ALIAS ), + ("unimp", 0, ISAI, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffff, match_opcode, 0 ), #/* csrw cycle, x0 */ + ("ebreak", 0, ISAC, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS ), + ("ebreak", 0, ISAI, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 ), + #("sbreak", 0, ISAC, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS ), + #("sbreak", 0, ISAI, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS ), + ("ret", 0, ISAC, "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("ret", 0, ISAI, "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("jr", 0, ISAC, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH ), + ("jr", 0, ISAI, "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("jr", 0, ISAI, "o(s)", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("jr", 0, ISAI, "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("jalr", 0, ISAC, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR ), + ("jalr", 0, ISAI, "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR ), + ("jalr", 0, ISAI, "o(s)", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ), + ("jalr", 0, ISAI, "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ), + ("jalr", 0, ISAI, "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR ), + ("jalr", 0, ISAI, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR ), + ("jalr", 0, ISAI, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR ), + ("j", 0, ISAC, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("j", 0, ISAI, "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH ), + ("jal", 0, ISAI, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR ), + ("jal", 32, ISAC, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR ), + ("jal", 0, ISAI, "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR ), + ("call", 0, ISAI, "d,c", (X_T1 << OP_SH_RS1), M_CALL, match_never, INSN_MACRO ), + ("call", 0, ISAI, "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), M_CALL, match_never, INSN_MACRO ), + ("tail", 0, ISAI, "c", (X_T1 << OP_SH_RS1), M_CALL, match_never, INSN_MACRO ), + ("jump", 0, ISAI, "c,s", 0, M_CALL, match_never, INSN_MACRO ), + ("nop", 0, ISAC, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS ), + ("nop", 0, ISAI, "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS ), + ("lui", 0, ISAC, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS ), + ("lui", 0, ISAI, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 ), + ("li", 0, ISAC, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS ), + ("li", 0, ISAC, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS ), + ("li", 0, ISAI, "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS ), #/* addi */ + ("li", 0, ISAI, "d,I", 0, M_LI, match_never, INSN_MACRO ), + ("mv", 0, ISAC, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS ), + ("mv", 0, ISAI, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS ), + ("move", 0, ISAC, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS ), + ("move", 0, ISAI, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS ), + ("andi", 0, ISAC, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS ), + ("andi", 0, ISAI, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 ), + ("and", 0, ISAC, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS ), + ("and", 0, ISAC, "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS ), + ("and", 0, ISAC, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS ), + ("and", 0, ISAI, "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 ), + ("and", 0, ISAI, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS ), + ("beqz", 0, ISAC, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("beqz", 0, ISAI, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("beq", 0, ISAC, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("beq", 0, ISAI, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH ), + ("blez", 0, ISAI, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bgez", 0, ISAI, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bge", 0, ISAI, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH ), + ("bgeu", 0, ISAI, "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH ), + ("ble", 0, ISAI, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bleu", 0, ISAI, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bltz", 0, ISAI, "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bgtz", 0, ISAI, "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("blt", 0, ISAI, "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH ), + ("bltu", 0, ISAI, "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_CONDBRANCH ), + ("bgt", 0, ISAI, "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bgtu", 0, ISAI, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bnez", 0, ISAC, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bnez", 0, ISAI, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bne", 0, ISAC, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH ), + ("bne", 0, ISAI, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH ), + ("addi", 0, ISAC, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS ), + ("addi", 0, ISAC, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS ), + ("addi", 0, ISAC, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS ), + ("addi", 0, ISAC, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS ), + ("addi", 0, ISAI, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 ), + ("add", 0, ISAC, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS ), + ("add", 0, ISAC, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS ), + ("add", 0, ISAC, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS ), + ("add", 0, ISAC, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS ), + ("add", 0, ISAC, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS ), + ("add", 0, ISAI, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 ), + #/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc + #applied to an add instruction, for relaxation to use. */ + #("add", 0, ISAI, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 ), + ("add", 0, ISAI, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS ), + ("la", 0, ISAI, "d,B", 0, M_LA, match_never, INSN_MACRO ), + ("lla", 0, ISAI, "d,B", 0, M_LLA, match_never, INSN_MACRO ), + ("la.tls.gd", 0, ISAI, "d,A", 0, M_LA_TLS_GD, match_never, INSN_MACRO ), + ("la.tls.ie", 0, ISAI, "d,A", 0, M_LA_TLS_IE, match_never, INSN_MACRO ), + ("neg", 0, ISAI, "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS ), #/* sub 0 */ + ("slli", 0, ISAC, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS ), + ("slli", 0, ISAI, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 ), + ("sll", 0, ISAC, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS ), + ("sll", 0, ISAI, "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 ), + ("sll", 0, ISAI, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS ), + ("srli", 0, ISAC, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS ), + ("srli", 0, ISAI, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 ), + ("srl", 0, ISAC, "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS ), + ("srl", 0, ISAI, "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 ), + ("srl", 0, ISAI, "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS ), + ("srai", 0, ISAC, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS ), + ("srai", 0, ISAI, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 ), + ("sra", 0, ISAC, "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS ), + ("sra", 0, ISAI, "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 ), + ("sra", 0, ISAI, "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS ), + ("sub", 0, ISAC, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS ), + ("sub", 0, ISAI, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 ), + ("lb", 0, ISAI, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE ), + ("lb", 0, ISAI, "d,A", 0, M_LB, match_never, INSN_MACRO ), + ("lbu", 0, ISAI, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE ), + ("lbu", 0, ISAI, "d,A", 0, M_LBU, match_never, INSN_MACRO ), + ("lh", 0, ISAI, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE ), + ("lh", 0, ISAI, "d,A", 0, M_LH, match_never, INSN_MACRO ), + ("lhu", 0, ISAI, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE ), + ("lhu", 0, ISAI, "d,A", 0, M_LHU, match_never, INSN_MACRO ), + ("lw", 0, ISAC, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("lw", 0, ISAC, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("lw", 0, ISAI, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lw", 0, ISAI, "d,A", 0, M_LW, match_never, INSN_MACRO ), + ("not", 0, ISAI, "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS ), + ("ori", 0, ISAI, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 ), + ("or", 0, ISAC, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS ), + ("or", 0, ISAC, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS ), + ("or", 0, ISAI, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 ), + ("or", 0, ISAI, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS ), + ("auipc", 0, ISAI, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 ), + ("seqz", 0, ISAI, "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS ), + ("snez", 0, ISAI, "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS ), + ("sltz", 0, ISAI, "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS ), + ("sgtz", 0, ISAI, "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS ), + ("slti", 0, ISAI, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 ), + ("slt", 0, ISAI, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 ), + ("slt", 0, ISAI, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS ), + ("sltiu", 0, ISAI, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 ), + ("sltu", 0, ISAI, "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 ), + ("sltu", 0, ISAI, "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS ), + ("sgt", 0, ISAI, "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS ), + ("sgtu", 0, ISAI, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS ), + ("sb", 0, ISAI, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE ), + ("sb", 0, ISAI, "t,A,s", 0, M_SB, match_never, INSN_MACRO ), + ("sh", 0, ISAI, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE ), + ("sh", 0, ISAI, "t,A,s", 0, M_SH, match_never, INSN_MACRO ), + ("sw", 0, ISAC, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("sw", 0, ISAC, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("sw", 0, ISAI, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("sw", 0, ISAI, "t,A,s", 0, M_SW, match_never, INSN_MACRO ), + ("fence", 0, ISAI, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS ), + ("fence", 0, ISAI, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 ), + ("fence.i", 0, ISAI, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 ), + ("fence.tso", 0, ISAI, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS ), + ("rdcycle", 0, ISAI, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS ), + ("rdinstret", 0, ISAI, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS ), + ("rdtime", 0, ISAI, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS ), + ("rdcycleh", 32, ISAI, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS ), + ("rdinstreth", 32, ISAI, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS ), + ("rdtimeh", 32, ISAI, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS ), + ("ecall", 0, ISAI, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 ), + #("scall", 0, ISAI, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 ), + ("xori", 0, ISAI, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 ), + ("xor", 0, ISAC, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS ), + ("xor", 0, ISAC, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS ), + ("xor", 0, ISAI, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 ), + ("xor", 0, ISAI, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS ), + ("lwu", 64, ISAI, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lwu", 64, ISAI, "d,A", 0, M_LWU, match_never, INSN_MACRO ), + ("ld", 64, ISAC, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("ld", 64, ISAC, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("ld", 64, ISAI, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("ld", 64, ISAI, "d,A", 0, M_LD, match_never, INSN_MACRO ), + ("sd", 64, ISAC, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("sd", 64, ISAC, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("sd", 64, ISAI, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("sd", 64, ISAI, "t,A,s", 0, M_SD, match_never, INSN_MACRO ), + ("sext.w", 64, ISAC, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS ), + ("sext.w", 64, ISAI, "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS ), + ("addiw", 64, ISAC, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS ), + ("addiw", 64, ISAI, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 ), + ("addw", 64, ISAC, "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS ), + ("addw", 64, ISAC, "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS ), + ("addw", 64, ISAC, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS ), + ("addw", 64, ISAI, "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 ), + ("addw", 64, ISAI, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS ), + ("negw", 64, ISAI, "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS ), #/* sub 0 */ + ("slliw", 64, ISAI, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 ), + ("sllw", 64, ISAI, "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 ), + ("sllw", 64, ISAI, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS ), + ("srliw", 64, ISAI, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 ), + ("srlw", 64, ISAI, "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 ), + ("srlw", 64, ISAI, "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS ), + ("sraiw", 64, ISAI, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 ), + ("sraw", 64, ISAI, "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 ), + ("sraw", 64, ISAI, "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS ), + ("subw", 64, ISAC, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS ), + ("subw", 64, ISAI, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 ), + +#/* Atomic memory operation instruction subset */ + ("lr.w", 0, ISAA, "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("sc.w", 0, ISAA, "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoadd.w", 0, ISAA, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoswap.w", 0, ISAA, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoand.w", 0, ISAA, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoor.w", 0, ISAA, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoxor.w", 0, ISAA, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomax.w", 0, ISAA, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomaxu.w", 0, ISAA, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomin.w", 0, ISAA, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amominu.w", 0, ISAA, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lr.w.aq", 0, ISAA, "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("sc.w.aq", 0, ISAA, "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoadd.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoswap.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoand.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoor.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoxor.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomax.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomaxu.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomin.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amominu.w.aq", 0, ISAA, "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lr.w.rl", 0, ISAA, "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("sc.w.rl", 0, ISAA, "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoadd.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoswap.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoand.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoor.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoxor.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomax.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomaxu.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomin.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amominu.w.rl", 0, ISAA, "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lr.w.aqrl", 0, ISAA, "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("sc.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoadd.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoswap.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoand.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoor.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amoxor.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomax.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomaxu.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amomin.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("amominu.w.aqrl", 0, ISAA, "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("lr.d", 64, ISAA , "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("sc.d", 64, ISAA , "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoadd.d", 64, ISAA , "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoswap.d", 64, ISAA , "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoand.d", 64, ISAA , "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoor.d", 64, ISAA , "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoxor.d", 64, ISAA , "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomax.d", 64, ISAA , "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomaxu.d", 64, ISAA , "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomin.d", 64, ISAA , "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amominu.d", 64, ISAA , "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("lr.d.aq", 64, ISAA , "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("sc.d.aq", 64, ISAA , "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoadd.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoswap.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoand.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoor.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoxor.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomax.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomaxu.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomin.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amominu.d.aq", 64, ISAA , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("lr.d.rl", 64, ISAA , "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("sc.d.rl", 64, ISAA , "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoadd.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoswap.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoand.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoor.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoxor.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomax.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomaxu.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomin.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amominu.d.rl", 64, ISAA , "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("lr.d.aqrl", 64, ISAA , "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("sc.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoadd.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoswap.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoand.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoor.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amoxor.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomax.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomaxu.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amomin.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("amominu.d.aqrl", 64, ISAA , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE ), + +#/* Multiply/Divide instruction subset */ + ("mul", 0, ISAM, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 ), + ("mulh", 0, ISAM, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 ), + ("mulhu", 0, ISAM, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 ), + ("mulhsu", 0, ISAM, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 ), + ("div", 0, ISAM, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 ), + ("divu", 0, ISAM, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 ), + ("rem", 0, ISAM, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 ), + ("remu", 0, ISAM, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 ), + ("mulw", 64, ISAM, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 ), + ("divw", 64, ISAM, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 ), + ("divuw", 64, ISAM, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 ), + ("remw", 64, ISAM, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 ), + ("remuw", 64, ISAM, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 ), + +#/* Single-precision floating-point instruction subset */ + ("frsr", 0, ISAF, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 ), + ("fssr", 0, ISAF, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 ), + ("fssr", 0, ISAF, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 ), + ("frcsr", 0, ISAF, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 ), + ("fscsr", 0, ISAF, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 ), + ("fscsr", 0, ISAF, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 ), + ("frrm", 0, ISAF, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 ), + ("fsrm", 0, ISAF, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 ), + ("fsrm", 0, ISAF, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 ), + ("fsrmi", 0, ISAF, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 ), + ("fsrmi", 0, ISAF, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 ), + ("frflags", 0, ISAF, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 ), + ("fsflags", 0, ISAF, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 ), + ("fsflags", 0, ISAF, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 ), + ("fsflagsi", 0, ISAF, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 ), + ("fsflagsi", 0, ISAF, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 ), + ("flw", 32, ISAFC, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("flw", 32, ISAFC, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("flw", 0, ISAF, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("flw", 0, ISAF, "D,A,s", 0, M_FLW, match_never, INSN_MACRO ), + ("fsw", 32, ISAFC, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("fsw", 32, ISAFC, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE ), + ("fsw", 0, ISAF, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("fsw", 0, ISAF, "T,A,s", 0, M_FSW, match_never, INSN_MACRO ), + + ("fmv.x.w", 0, ISAF, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 ), + ("fmv.w.x", 0, ISAF, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 ), + + ("fmv.x.s", 0, ISAF, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 ), + ("fmv.s.x", 0, ISAF, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 ), + + ("fmv.s", 0, ISAF, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS ), + ("fneg.s", 0, ISAF, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS ), + ("fabs.s", 0, ISAF, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS ), + ("fsgnj.s", 0, ISAF, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 ), + ("fsgnjn.s", 0, ISAF, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 ), + ("fsgnjx.s", 0, ISAF, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 ), + ("fadd.s", 0, ISAF, "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 ), + ("fadd.s", 0, ISAF, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 ), + ("fsub.s", 0, ISAF, "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 ), + ("fsub.s", 0, ISAF, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 ), + ("fmul.s", 0, ISAF, "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 ), + ("fmul.s", 0, ISAF, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 ), + ("fdiv.s", 0, ISAF, "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 ), + ("fdiv.s", 0, ISAF, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 ), + ("fsqrt.s", 0, ISAF, "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 ), + ("fsqrt.s", 0, ISAF, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 ), + ("fmin.s", 0, ISAF, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 ), + ("fmax.s", 0, ISAF, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 ), + ("fmadd.s", 0, ISAF, "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 ), + ("fmadd.s", 0, ISAF, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 ), + ("fnmadd.s", 0, ISAF, "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 ), + ("fnmadd.s", 0, ISAF, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 ), + ("fmsub.s", 0, ISAF, "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 ), + ("fmsub.s", 0, ISAF, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 ), + ("fnmsub.s", 0, ISAF, "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 ), + ("fnmsub.s", 0, ISAF, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 ), + ("fcvt.w.s", 0, ISAF, "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 ), + ("fcvt.w.s", 0, ISAF, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 ), + ("fcvt.wu.s", 0, ISAF, "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 ), + ("fcvt.wu.s", 0, ISAF, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 ), + ("fcvt.s.w", 0, ISAF, "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 ), + ("fcvt.s.w", 0, ISAF, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 ), + ("fcvt.s.wu", 0, ISAF, "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 ), + ("fcvt.s.wu", 0, ISAF, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 ), + ("fclass.s", 0, ISAF, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 ), + ("feq.s", 0, ISAF, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 ), + ("flt.s", 0, ISAF, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 ), + ("fle.s", 0, ISAF, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 ), + ("fgt.s", 0, ISAF, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 ), + ("fge.s", 0, ISAF, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 ), + ("fcvt.l.s", 64, ISAF, "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 ), + ("fcvt.l.s", 64, ISAF, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 ), + ("fcvt.lu.s", 64, ISAF, "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 ), + ("fcvt.lu.s", 64, ISAF, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 ), + ("fcvt.s.l", 64, ISAF, "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 ), + ("fcvt.s.l", 64, ISAF, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 ), + ("fcvt.s.lu", 64, ISAF, "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 ), + ("fcvt.s.lu", 64, ISAF, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 ), + +#/* Double-precision floating-point instruction subset */ + ("fld", 0, ISADC, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("fld", 0, ISADC, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("fld", 0, ISAD, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("fld", 0, ISAD, "D,A,s", 0, M_FLD, match_never, INSN_MACRO ), + ("fsd", 0, ISADC, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("fsd", 0, ISADC, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE ), + ("fsd", 0, ISAD, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("fsd", 0, ISAD, "T,A,s", 0, M_FSD, match_never, INSN_MACRO ), + ("fmv.d", 0, ISAD, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS ), + ("fneg.d", 0, ISAD, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS ), + ("fabs.d", 0, ISAD, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS ), + ("fsgnj.d", 0, ISAD, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 ), + ("fsgnjn.d", 0, ISAD, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 ), + ("fsgnjx.d", 0, ISAD, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 ), + ("fadd.d", 0, ISAD, "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 ), + ("fadd.d", 0, ISAD, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 ), + ("fsub.d", 0, ISAD, "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 ), + ("fsub.d", 0, ISAD, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 ), + ("fmul.d", 0, ISAD, "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 ), + ("fmul.d", 0, ISAD, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 ), + ("fdiv.d", 0, ISAD, "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 ), + ("fdiv.d", 0, ISAD, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 ), + ("fsqrt.d", 0, ISAD, "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 ), + ("fsqrt.d", 0, ISAD, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 ), + ("fmin.d", 0, ISAD, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 ), + ("fmax.d", 0, ISAD, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 ), + ("fmadd.d", 0, ISAD, "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 ), + ("fmadd.d", 0, ISAD, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 ), + ("fnmadd.d", 0, ISAD, "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 ), + ("fnmadd.d", 0, ISAD, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 ), + ("fmsub.d", 0, ISAD, "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 ), + ("fmsub.d", 0, ISAD, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 ), + ("fnmsub.d", 0, ISAD, "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 ), + ("fnmsub.d", 0, ISAD, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 ), + ("fcvt.w.d", 0, ISAD, "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 ), + ("fcvt.w.d", 0, ISAD, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 ), + ("fcvt.wu.d", 0, ISAD, "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 ), + ("fcvt.wu.d", 0, ISAD, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 ), + ("fcvt.d.w", 0, ISAD, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 ), + ("fcvt.d.wu", 0, ISAD, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 ), + ("fcvt.d.s", 0, ISAD, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 ), + ("fcvt.s.d", 0, ISAD, "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 ), + ("fcvt.s.d", 0, ISAD, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 ), + ("fclass.d", 0, ISAD, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 ), + ("feq.d", 0, ISAD, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 ), + ("flt.d", 0, ISAD, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 ), + ("fle.d", 0, ISAD, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 ), + ("fgt.d", 0, ISAD, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 ), + ("fge.d", 0, ISAD, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 ), + ("fmv.x.d", 64, ISAD, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 ), + ("fmv.d.x", 64, ISAD, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 ), + ("fcvt.l.d", 64, ISAD, "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 ), + ("fcvt.l.d", 64, ISAD, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 ), + ("fcvt.lu.d", 64, ISAD, "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 ), + ("fcvt.lu.d", 64, ISAD, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 ), + ("fcvt.d.l", 64, ISAD, "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 ), + ("fcvt.d.l", 64, ISAD, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 ), + ("fcvt.d.lu", 64, ISAD, "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 ), + ("fcvt.d.lu", 64, ISAD, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 ), + +#/* Quad-precision floating-point instruction subset */ + ("flq", 0, ISAQ, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE ), + ("flq", 0, ISAQ, "D,A,s", 0, M_FLQ, match_never, INSN_MACRO ), + ("fsq", 0, ISAQ, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE ), + ("fsq", 0, ISAQ, "T,A,s", 0, M_FSQ, match_never, INSN_MACRO ), + ("fmv.q", 0, ISAQ, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS ), + ("fneg.q", 0, ISAQ, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS ), + ("fabs.q", 0, ISAQ, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS ), + ("fsgnj.q", 0, ISAQ, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 ), + ("fsgnjn.q", 0, ISAQ, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 ), + ("fsgnjx.q", 0, ISAQ, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 ), + ("fadd.q", 0, ISAQ, "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 ), + ("fadd.q", 0, ISAQ, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 ), + ("fsub.q", 0, ISAQ, "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 ), + ("fsub.q", 0, ISAQ, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 ), + ("fmul.q", 0, ISAQ, "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 ), + ("fmul.q", 0, ISAQ, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 ), + ("fdiv.q", 0, ISAQ, "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 ), + ("fdiv.q", 0, ISAQ, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 ), + ("fsqrt.q", 0, ISAQ, "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 ), + ("fsqrt.q", 0, ISAQ, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 ), + ("fmin.q", 0, ISAQ, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 ), + ("fmax.q", 0, ISAQ, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 ), + ("fmadd.q", 0, ISAQ, "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 ), + ("fmadd.q", 0, ISAQ, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 ), + ("fnmadd.q", 0, ISAQ, "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 ), + ("fnmadd.q", 0, ISAQ, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 ), + ("fmsub.q", 0, ISAQ, "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 ), + ("fmsub.q", 0, ISAQ, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 ), + ("fnmsub.q", 0, ISAQ, "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 ), + ("fnmsub.q", 0, ISAQ, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 ), + ("fcvt.w.q", 0, ISAQ, "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.w.q", 0, ISAQ, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 ), + ("fcvt.wu.q", 0, ISAQ, "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.wu.q", 0, ISAQ, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 ), + ("fcvt.q.w", 0, ISAQ, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 ), + ("fcvt.q.wu", 0, ISAQ, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 ), + ("fcvt.q.s", 0, ISAQ, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 ), + ("fcvt.q.d", 0, ISAQ, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 ), + ("fcvt.s.q", 0, ISAQ, "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.s.q", 0, ISAQ, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 ), + ("fcvt.d.q", 0, ISAQ, "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.d.q", 0, ISAQ, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 ), + ("fclass.q", 0, ISAQ, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 ), + ("feq.q", 0, ISAQ, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 ), + ("flt.q", 0, ISAQ, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 ), + ("fle.q", 0, ISAQ, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 ), + ("fgt.q", 0, ISAQ, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 ), + ("fge.q", 0, ISAQ, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 ), + ("fmv.x.q", 64, ISAQ, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 ), + ("fmv.q.x", 64, ISAQ, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 ), + ("fcvt.l.q", 64, ISAQ, "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.l.q", 64, ISAQ, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 ), + ("fcvt.lu.q", 64, ISAQ, "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 ), + ("fcvt.lu.q", 64, ISAQ, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 ), + ("fcvt.q.l", 64, ISAQ, "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 ), + ("fcvt.q.l", 64, ISAQ, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 ), + ("fcvt.q.lu", 64, ISAQ, "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 ), + ("fcvt.q.lu", 64, ISAQ, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 ), + +#/* Compressed instructions. */ + ("c.unimp", 0, ISAC, "", 0, 0xffff, match_opcode, 0 ), + ("c.ebreak", 0, ISAC, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 ), + ("c.jr", 0, ISAC, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH ), + ("c.jalr", 0, ISAC, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR ), + ("c.j", 0, ISAC, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_BRANCH ), + ("c.jal", 32, ISAC, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_JSR ), + ("c.beqz", 0, ISAC, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_CONDBRANCH ), + ("c.bnez", 0, ISAC, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_CONDBRANCH ), + ("c.lwsp", 0, ISAC, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 ), + ("c.lw", 0, ISAC, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.swsp", 0, ISAC, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.sw", 0, ISAC, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.nop", 0, ISAC, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS ), + ("c.nop", 0, ISAC, "Cj", MATCH_C_ADDI, MASK_C_ADDI | MASK_RD, match_opcode, INSN_ALIAS ), + ("c.mv", 0, ISAC, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 ), + ("c.lui", 0, ISAC, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 ), + ("c.li", 0, ISAC, "d,Co", MATCH_C_LI, MASK_C_LI, match_opcode, 0 ), + ("c.addi4spn", 0, ISAC, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 ), + ("c.addi16sp", 0, ISAC, "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 ), + ("c.addi", 0, ISAC, "d,Co", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 ), + ("c.add", 0, ISAC, "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add_with_hint, 0 ), + ("c.sub", 0, ISAC, "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 ), + ("c.and", 0, ISAC, "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 ), + ("c.or", 0, ISAC, "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 ), + ("c.xor", 0, ISAC, "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 ), + ("c.slli", 0, ISAC, "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 ), + ("c.srli", 0, ISAC, "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 ), + ("c.srai", 0, ISAC, "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 ), + ("c.slli64", 0, ISAC, "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 ), + ("c.srli64", 0, ISAC, "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 ), + ("c.srai64", 0, ISAC, "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 ), + ("c.andi", 0, ISAC, "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 ), + ("c.addiw", 64, ISAC, "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 ), + ("c.addw", 64, ISAC, "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 ), + ("c.subw", 64, ISAC, "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 ), + ("c.ldsp", 64, ISAC, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE ), + ("c.ld", 64, ISAC, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.sdsp", 64, ISAC, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.sd", 64, ISAC, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.fldsp", 0, ISADC, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.fld", 0, ISADC, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.fsdsp", 0, ISADC, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.fsd", 0, ISADC, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE ), + ("c.flwsp", 32, ISAFC, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.flw", 32, ISAFC, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.fswsp", 32, ISAFC, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE ), + ("c.fsw", 32, ISAFC, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE ), + +#/* Supervisor instructions */ + ("csrr", 0, ISAI, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS ), + ("csrwi", 0, ISAI, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrsi", 0, ISAI, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrci", 0, ISAI, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrw", 0, ISAI, "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrw", 0, ISAI, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrs", 0, ISAI, "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrs", 0, ISAI, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrc", 0, ISAI, "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrc", 0, ISAI, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS ), + ("csrrwi", 0, ISAI, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 ), + ("csrrsi", 0, ISAI, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 ), + ("csrrci", 0, ISAI, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 ), + ("csrrw", 0, ISAI, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 ), + ("csrrw", 0, ISAI, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS ), + ("csrrs", 0, ISAI, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 ), + ("csrrs", 0, ISAI, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS ), + ("csrrc", 0, ISAI, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 ), + ("csrrc", 0, ISAI, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS ), + ("uret", 0, ISAI, "", MATCH_URET, MASK_URET, match_opcode, 0 ), + ("sret", 0, ISAI, "", MATCH_SRET, MASK_SRET, match_opcode, 0 ), + ("hret", 0, ISAI, "", MATCH_HRET, MASK_HRET, match_opcode, 0 ), + ("mret", 0, ISAI, "", MATCH_MRET, MASK_MRET, match_opcode, 0 ), + ("dret", 0, ISAI, "", MATCH_DRET, MASK_DRET, match_opcode, 0 ), + ("sfence.vm", 0, ISAI, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 ), + ("sfence.vm", 0, ISAI, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 ), + ("sfence.vma", 0, ISAI, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS ), + ("sfence.vma", 0, ISAI, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS ), + ("sfence.vma", 0, ISAI, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 ), + ("wfi", 0, ISAI, "", MATCH_WFI, MASK_WFI, match_opcode, 0 )] + + + +# expanded +# 16 xxxxxxxxxxxxxxaa != 11 +# 32 xxxxxxxxxxxbbb11 != 111 +# 48 xxxxxxxxxx011111 +# 64 xxxxxxxxx0111111 +# 80 xnnnxxxxx1111111 != 111 +# 192 x111xxxxx1111111 + +# print("immI: op2031 is op2031 { local tmp:4 = op2031; export tmp; }") +# print("immS: imm is op0711 & op2531 [ imm = (op2531 << 5) | op0711; ] { local tmp:4 = zext(imm); export tmp; }") +# print("immSB: imm is op0707 & op0811 & op2530 & op3131 [ imm = (op3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11); ] { local tmp:4 = zext(imm); export tmp; }") +# print("immU: imm is op1231 [ imm = (op1231 << 12); ] { local tmp:4 = zext(imm); export tmp; }") +# print("immUJ: imm is op1219 & op2020 & op2130 & op3131 [ imm = (op3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12); ] { local tmp:4 = zext(imm); export tmp; }") + +# print("shamt5: op2024 is op2024 { local tmp:4 = op2024; export tmp; }") +# print("shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:4 = imm; export tmp; }") + +# print("fmt: \".s\" is op2526=0 {}") +# print("fmt: \".d\" is op2526=1 {}") +# print("fmt: \".h\" is op2526=2 {}") +# print("fmt: \".q\" is op2526=3 {}") + + + +def parse_operand(op): + dis = op.operands + is16 = op.match & 3 != 3 + x = 0 + out = "" + cons=[] + while x < len(dis): + if dis[x] == 'C': + x += 1 + if dis[x] == 'a': + out += "cjimm" + cons.append("cjimm") + elif dis[x] == 'c': + out += "sp" + cons.append("cop0711=2") + cons.append("sp") + elif dis[x] == 'i': + out += "csimm3" + cons.append("csimm3") + elif dis[x] == 'o' or dis[x] == 'j': + out += "cimmI" + cons.append("cimmI") + elif dis[x] == 'k': + out += "clwimm" + cons.append("clwimm") + elif dis[x] == 'l': + out += "cldimm" + cons.append("cldimm") + elif dis[x] == 'm': + out += "clwspimm" + cons.append("clwspimm") + elif dis[x] == 'n': + out += "cldspimm" + cons.append("cldspimm") + elif dis[x] == 'p': + out += "cbimm" + cons.append("cbimm") + elif dis[x] == 's': + out += "cr0709s" + cons.append("cr0709s") + elif dis[x] == 't': + out += "cr0204s" + cons.append("cr0204s") + elif dis[x] == 'w': + out += "cd0709s" + cons.append("cd0709s") + elif dis[x] == 'x': + out += "cr0204s" + cons.append("cr0204s") + elif dis[x] == 'u' or dis[x] == 'v': + out += "cbigimm" + cons.append("cbigimm") + elif dis[x] == 'z': + out += "zero" + cons.append("cop0206=0") + cons.append("zero") + elif dis[x] == 'U': + out += "cr0711" + cons.append("cr0711") + elif dis[x] == 'V': + out += "cr0206" + cons.append("cr0206") + elif dis[x] == 'K': + out += "caddi4spnimm" + cons.append("caddi4spnimm") + elif dis[x] == 'L': + out += "caddi16spimm" + cons.append("caddi16spimm") + elif dis[x] == 'M': + out += "cswspimm" + cons.append("cswspimm") + elif dis[x] == 'N': + out += "csdspimm" + cons.append("csdspimm") + elif dis[x] == '>': + out += "c6imm" + cons.append("c6imm") + elif dis[x] == '<': + out += "c5imm" + cons.append("c5imm") + elif dis[x] == 'T': + out += "cfr0206" + cons.append("cfr0206") + elif dis[x] == 'D': + out += "cfr0204s" + cons.append("cfr0204s") + else: + print("BAD C case %c" % (dis[x])) + print(op) + exit(1) + elif dis[x] in [',', '(', ')', '[', ']']: + out += dis[x] + elif dis[x] == '0': + if x+1 == len(dis): + out += "0" + elif dis[x] == 'b' or dis[x] == 's': + if is16: + out += "cr1519" + cons.append("cr1519") + else: + out += "r1519" + cons.append("r1519") + elif dis[x] == 't': + if is16: + out += "cr2024" + cons.append("cr2024") + else: + out += "r2024" + cons.append("r2024") + elif dis[x] == 'u': + out += "immU" + cons.append("immU") + elif dis[x] == 'm': + out += "frm" + cons.append("frm") + elif dis[x] == 'P': + out += "pred" + cons.append("pred") + elif dis[x] == 'Q': + out += "succ" + cons.append("succ") + elif dis[x] == 'o': + out += "immI" + cons.append("immI") + elif dis[x] == 'j': + out += "immI" + cons.append("immI") + elif dis[x] == 'q': + out += "immS" + cons.append("immS") + elif dis[x] == 'a': + out += "immUJ" + cons.append("immUJ") + elif dis[x] == 'p': + out += "immSB" + cons.append("immSB") + elif dis[x] == 'd': + if is16: + out += "cd0711" + cons.append("cd0711") + else: + out += "r0711" + cons.append("r0711") + elif dis[x] == 'z': + out += "zero" + cons.append("zero") + elif dis[x] == '>': + out += "shamt6" + cons.append("shamt6") + elif dis[x] == '<': + out += "shamt5" + cons.append("shamt5") + elif dis[x] == 'S' or dis[x] == 'U': + if is16: + out += "cfr1519" + cons.append("cfr1519") + else: + out += "fr1519" + cons.append("fr1519") + elif dis[x] == 'T': + if is16: + out += "cfr2024" + cons.append("cfr2024") + else: + out += "fr2024" + cons.append("fr2024") + elif dis[x] == 'D': + if is16: + out += "cfr0711" + cons.append("cfr0711") + else: + out += "fr0711" + cons.append("fr0711") + elif dis[x] == 'R': + if is16: + out += "cfr2731" + cons.append("cfr2731") + else: + out += "fr2731" + cons.append("fr2731") + elif dis[x] == 'E': + out += "csr" + cons.append("csr") + elif dis[x] == 'Z': + if is16: + out += "cr1519" + cons.append("cr1519") + else: + out += "r1519" + cons.append("r1519") + else: + print("BAD top case %c" % (dis[x])) + print(op) + exit(1) + x += 1 + # print("DISPLAY: %s" % out) + return (out, cons) + +def parse_r(op): + funct3 = (op.match >> 12) & ((1<<3) - 1) + funct7 = (op.match >> 25) & ((1<<7) - 1) + op.bitpattern.append("funct3=0x%x" % funct3) + op.bitpattern.append("funct7=0x%x" % funct7) + return + +def parse_i(op): + funct3 = (op.match >> 12) & ((1<<3) - 1) + op.bitpattern.append("funct3=0x%x" % funct3) + return + +def parse_s(op): + funct3 = (op.match >> 12) & ((1<<3) - 1) + op.bitpattern.append("funct3=0x%x" % funct3) + return + +def parse_u(op): + return + +def parse_b(op): + funct3 = (op.match >> 12) & ((1<<3) - 1) + op.bitpattern.append("funct3=0x%x" % funct3) + return + +def parse_j(op): + return + +def parse_misc_mem(op): + fm = (op.match >> 28) & ((1<<4) - 1) + funct3 = (op.match >> 12) & ((1<<3) - 1) + op.bitpattern.append("funct3=0x%x" % funct3) + op.bitpattern.append("fm=0x%x" % fm) + return + + +def parse_CR(op, rv): + return + +def parse_CI(op, rv): + x = (op.match >> 13) & 7 + if op.bitpattern.count("clwspimm") == 1: + op.bitpattern.remove("clwspimm") + if x == 2 or (x == 3 and rv == 32): + op.display = op.display.replace("clwspimm", "clwspimm54276") + op.bitpattern.append("clwspimm54276") + elif x == 1 and rv == 128: + op.display = op.display.replace("clwspimm", "clwspimm5496") + op.bitpattern.append("clwspimm5496") + elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)): + op.display = op.display.replace("clwspimm", "clwspimm54386") + op.bitpattern.append("clwspimm54386") + if op.bitpattern.count("cldspimm") == 1: + op.bitpattern.remove("cldspimm") + if x == 2 or (x == 3 and rv == 32): + op.display = op.display.replace("cldspimm", "cldspimm54276") + op.bitpattern.append("cldspimm54276") + elif x == 1 and rv == 128: + op.display = op.display.replace("cldspimm", "cldspimm5496") + op.bitpattern.append("cldspimm5496") + elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)): + op.display = op.display.replace("cldspimm", "cldspimm54386") + op.bitpattern.append("cldspimm54386") + return + +def parse_CSS(op, rv): + x = (op.match >> 13) & 7 + if op.bitpattern.count("cswspimm") == 1: + op.bitpattern.remove("cswspimm") + if (x == 5 and (rv == 32 or rv == 64)) or (x == 7 and (rv == 128 or rv == 64)): + op.display = op.display.replace("cswspimm", "cswspimm5386") + op.bitpattern.append("cswspimm5386") + elif (x == 5 and rv == 128): + op.display = op.display.replace("cswspimm", "cswspimm5496") + op.bitpattern.append("cswspimm5496") + elif (x == 7 and rv == 32) or (x == 6): + op.display = op.display.replace("cswspimm", "cswspimm5276") + op.bitpattern.append("cswspimm5276") + if op.bitpattern.count("csdspimm") == 1: + op.bitpattern.remove("csdspimm") + if (x == 5 and (rv == 32 or rv == 64)) or (x == 7 and (rv == 128 or rv == 64)): + op.display = op.display.replace("csdspimm", "csdspimm5386") + op.bitpattern.append("csdspimm5386") + elif (x == 5 and rv == 128): + op.display = op.display.replace("csdspimm", "csdspimm5496") + op.bitpattern.append("csdspimm5496") + elif (x == 7 and rv == 32) or (x == 6): + op.display = op.display.replace("csdspimm", "csdspimm5276") + op.bitpattern.append("csdspimm5276") + return + +def parse_CIW(op, rv): + return + +def parse_CL(op, rv): + x = (op.match >> 13) & 7 + if op.bitpattern.count("cldspimm") == 1: + op.bitpattern.remove("cldspimm") + if x == 2 or (x == 3 and rv == 32): + op.display = op.display.replace("cldspimm", "cldspimm54276") + op.bitpattern.append("cldspimm54276") + elif x == 1 and rv == 128: + op.display = op.display.replace("cldspimm", "cldspimm5496") + op.bitpattern.append("cldspimm5496") + elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)): + op.display = op.display.replace("cldspimm", "cldspimm54386") + op.bitpattern.append("cldspimm54386") + if op.bitpattern.count("clwspimm") == 1: + op.bitpattern.remove("clwspimm") + if x == 2 or (x == 3 and rv == 32): + op.display = op.display.replace("clwspimm", "clwspimm54276") + op.bitpattern.append("clwspimm54276") + elif x == 1 and rv == 128: + op.display = op.display.replace("clwspimm", "clwspimm5496") + op.bitpattern.append("clwspimm5496") + elif (x == 1 and (rv == 32 or rv == 64)) or (x == 3 and (rv == 64 or rv == 128)): + op.display = op.display.replace("clwspimm", "clwspimm54386") + op.bitpattern.append("clwspimm54386") + if op.bitpattern.count("cldimm") == 1: + op.bitpattern.remove("cldimm") + if None == rv: + op.display = op.display.replace("cldimm", "cldimm5326") + op.bitpattern.append("cldimm5326") + elif 32 == rv and (x == 3 or x == 7): + op.display = op.display.replace("cldimm", "cldimm5326") + op.bitpattern.append("cldimm5326") + elif (32 == rv or 64 == rv) and (x == 1 or x == 5): + op.display = op.display.replace("cldimm", "cldimm5376") + op.bitpattern.append("cldimm5376") + elif (128 == rv or 64 == rv) and (x == 3 or x == 7): + op.display = op.display.replace("cldimm", "cldimm5376") + op.bitpattern.append("cldimm5376") + elif 128 == rv and (x == 1 or x == 7): + op.display = op.display.replace("cldimm", "cldimm54876") + op.bitpattern.append("cldimm54876") + else: + print("BAD CL rv %r" % (rv)) + exit(1) + if op.bitpattern.count("clwimm") == 1: + op.bitpattern.remove("clwimm") + if None == rv: + op.display = op.display.replace("clwimm", "clwimm5326") + op.bitpattern.append("clwimm5326") + elif 32 == rv and (x == 3 or x == 7): + op.display = op.display.replace("clwimm", "clwimm5326") + op.bitpattern.append("clwimm5326") + elif (32 == rv or 64 == rv) and (x == 1 or x == 5): + op.display = op.display.replace("clwimm", "clwimm5376") + op.bitpattern.append("clwimm5376") + elif (128 == rv or 64 == rv) and (x == 3 or x == 7): + op.display = op.display.replace("clwimm", "clwimm5376") + op.bitpattern.append("clwimm5376") + elif 128 == rv and (x == 1 or x == 7): + op.display = op.display.replace("clwimm", "clwimm54876") + op.bitpattern.append("clwimm54876") + else: + print("BAD CL rv %r" % (rv)) + exit(1) + return + +def parse_CS(op, rv): + x = (op.match >> 13) & 7 + if op.bitpattern.count("clwimm") == 1: + op.bitpattern.remove("clwimm") + if None == rv: + op.display = op.display.replace("clwimm", "clwimm5326") + op.bitpattern.append("clwimm5326") + elif 32 == rv and (x == 3 or x == 7): + op.display = op.display.replace("clwimm", "clwimm5326") + op.bitpattern.append("clwimm5326") + elif (32 == rv or 64 == rv) and (x == 1 or x == 5): + op.display = op.display.replace("clwimm", "clwimm5376") + op.bitpattern.append("clwimm5376") + elif (128 == rv or 64 == rv) and (x == 3 or x == 7): + op.display = op.display.replace("clwimm", "clwimm5376") + op.bitpattern.append("clwimm5376") + elif 128 == rv and (x == 1 or x == 7): + op.display = op.display.replace("clwimm", "clwimm54876") + op.bitpattern.append("clwimm54876") + else: + print("BAD CL rv %r" % (rv)) + exit(1) + if op.bitpattern.count("cldimm") == 1: + op.bitpattern.remove("cldimm") + if None == rv: + op.display = op.display.replace("cldimm", "cldimm5326") + op.bitpattern.append("cldimm5326") + elif 32 == rv and (x == 3 or x == 7): + op.display = op.display.replace("cldimm", "cldimm5326") + op.bitpattern.append("cldimm5326") + elif (32 == rv or 64 == rv) and (x == 1 or x == 5): + op.display = op.display.replace("cldimm", "cldimm5376") + op.bitpattern.append("cldimm5376") + elif (128 == rv or 64 == rv) and (x == 3 or x == 7): + op.display = op.display.replace("cldimm", "cldimm5376") + op.bitpattern.append("cldimm5376") + elif 128 == rv and (x == 1 or x == 7): + op.display = op.display.replace("cldimm", "cldimm54876") + op.bitpattern.append("cldimm54876") + else: + print("BAD CL rv %r" % (rv)) + exit(1) + return + +def parse_CA(op, rv): + return + +def parse_CB(op, rv): + return + +def parse_CJ(op, rv): + return + + +def opcode_map_c(op): + ''' + CR |funct4 | cr0711 | cr0206 | op | + CI |funct3 | cop1212 | cr0711 | cop0206 | op | + CSS |funct3 | cop0712 | cr0206 | op | + CIW |funct3 | cop0512 | cr0204s | op | + CL |funct3 | cop1012 | cs0709s | cop0506 | cr0204s | op | + CS |funct3 | cop1012 | cr0709s | cop0506 | cr0204s | op | + CA |funct6 | cr0709s | funct2 | cr0204s | op | + CB |funct3 | off1012 | cr0709s | off0206 | op | + CJ |funct3 | target | op | + ''' + x = (op.match >> 13) & 7 + y = op.match & 3 + op.bitpattern.append("cop0001=0x%x" % y) + op.bitpattern.append("cop1315=0x%x" % x) + # print("CMAP: RV32, RV64, RV128") + if x == 0 and y == 0: + # ADDI4SPN + parse_CIW(op, None) + elif x == 0 and y == 1: + # ADDI + parse_CI(op, None) + elif x == 0 and y == 2: + # SLLI + parse_CI(op, None) + elif x == 1 and y == 0: + # FLD FLD LQ + # print("CMAP: FLD FLD LQ") + if op.name.find("fld") >= 0: + print("#TODO 32 64") + parse_CL(op, 32) + parse_CL(op, 64) + elif op.name.find("lq") >= 0: parse_CL(op, 128) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 1 and y == 1: + # JAL ADDIW ADDIW + # print("CMAP: JAL ADDIW ADDIW") + if op.name.find("jal") >= 0: parse_CJ(op, 32) + elif op.name.find("addiw") >= 0: + print("#TODO 32 64") + parse_CI(op, 64) + parse_CI(op, 128) + elif op.name == "sext.w": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "addw": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 1 and y == 2: + # LW LI LWSP + # print("CMAP: FLDSP FLDSP LQSP") + if op.name.find("fldsp") >= 0: + print("#TODO 32 64") + parse_CI(op, 32) + parse_CI(op, 64) + elif op.name.find("lqsp") >= 0: parse_CI(op, 128) + elif op.name == "fld": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 2 and y == 0: + # FW + parse_CL(op, None) + elif x == 2 and y == 1: + # LI + # print("CMAP: LI") + if op.name.find("li") >= 0: parse_CI(op, None) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 2 and y == 2: + # LWSP + parse_CI(op, None) + elif x == 3 and y == 0: + # FLW LD LD + # print("CMAP: FLW LD LD") + if op.name.find("flw") >= 0: parse_CL(op, 32) + elif op.name.find("ld") >= 0: + print("#TODO 64 128") + parse_CL(op, 64) + parse_CL(op, 128) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 3 and y == 1: + # LUI ADDI16SP + # print("CMAP: LUI ADDI16SP") + if op.name.find("lui") >= 0: parse_CI(op, None) + elif op.name.find("addi16sp") >= 0: parse_CJ(op, None) + elif op.name == "li": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "addi": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "add": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 3 and y == 2: + # FLWSP LDSP LDSP + # print("CMAP: FLWSP LDSP LDSP") + if op.name.find("flwsp") >= 0: parse_CI(op, 32) + elif op.name.find("ldsp") >= 0: + print("#TODO 64 128") + parse_CI(op, 64) + parse_CI(op, 128) + elif op.name == "ld": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "flw": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 4 and y == 0: + # RESERVED + # print("CMAP: RESERVED C 3 0") + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif x == 4 and y == 1: + # MISC-ALU + # print("CMAP: MISC-ALU") + if (op.match >> 10) & 3 == 3: + parse_CA(op, None) + else: + parse_CB(op, None) + pass + elif x == 4 and y == 2: + # JR JALR MV ADD + # print("CMAP: JR JALR MV ADD") + if op.name.find("jr") >= 0: parse_CI(op, None) + elif op.name.find("jalr") >= 0: parse_CI(op, None) + elif op.name.find("mv") >= 0: parse_CR(op, None) + elif op.name.find("add") >= 0: parse_CR(op, None) + elif op.name == "ebreak": parse_CJ(op, None) + elif op.name == "c.ebreak": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "ret": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "move": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 5 and y == 0: + # FSD FSD SQ + # print("CMAP: FSD FSD SQ") + if op.name.find("fsd") >= 0: + print("#TODO 32 64") + parse_CS(op, 32) + parse_CS(op, 64) + elif op.name.find("sq") >= 0: parse_CS(op, 128) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 5 and y == 1: + # J + # print("CMAP: J") + if op.name.find("j") >= 0: parse_CJ(op, None) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 5 and y == 2: + # FSDSP FSDSP SQSP + # print("CMAP: FSDSP FSDSP SQSP") + if op.name.find("fsdsp") >= 0: + print("#TODO 32 64") + parse_CSS(op, 32) + parse_CSS(op, 64) + elif op.name.find("sqsp") >= 0: parse_CSS(op, 128) + elif op.name == "fsd": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 6 and y == 0: + # SW + # print("CMAP: SW") + if op.name.find("sw") >= 0: parse_CS(op, None) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 6 and y == 1: + # BEQZ + parse_CB(op, None) + elif x == 6 and y == 2: + # SWSP + parse_CSS(op, None) + elif x == 7 and y == 0: + # FSW SD SD + # print("CMAP: FSW SD SD") + if op.name.find("fsw") >= 0: parse_CS(op, 32) + elif op.name.find("sd") >= 0: + print("#TODO 64 128") + parse_CS(op, 64) + parse_CS(op, 128) + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + elif x == 7 and y == 1: + # BNEZ + parse_CB(op, None) + elif x == 7 and y == 2: + # + # print("CMAP: FSWSP SDSP SDSP") + if op.name.find("fswsp") >= 0: parse_CSS(op, 32) + elif op.name.find("sdsp") >= 0: + print("#TODO 64 128") + parse_CSS(op, 64) + parse_CSS(op, 128) + elif op.name == "sd": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + elif op.name == "fsw": + print("#TODO %s %s" % (op.display, ' & '.join(op.bitpattern))) + pass + else: + print("CMAP -- %s" % (op.name)) + print(op) + exit(1) + pass + else: + print("CBAD X %x Y %x" % (x, y)) + print(op) + exit(1) + + +def opcode_map(op): + x = (op.match >> 2) & 7 + y = (op.match >> 5) & 3 + op.bitpattern.append("op0001=0x3") + op.bitpattern.append("op0204=0x%x" % x) + op.bitpattern.append("op0506=0x%x" % y) + if x == 0: + if y == 0: + # LOAD + # print("MAP: LOAD") + parse_i(op) + pass + elif y == 1: + # STORE + # print("MAP: STORE") + parse_s(op) + pass + elif y == 2: + # MADD + # print("MAP: MADD") + parse_r(op) + pass + elif y == 3: + # BRANCH + # print("MAP: BRANCH") + parse_b(op) + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 1: + if y == 0: + # LOAD-FP + # print("MAP: LOAD-FP") + parse_i(op) + pass + elif y == 1: + # STORE-FP + # print("MAP: STORE-FP") + parse_s(op) + pass + elif y == 2: + # MSUB + # print("MAP: MSUB") + parse_r(op) + pass + elif y == 3: + # JALR + # print("MAP: JALR") + parse_i(op) + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 2: + if y == 0: + # CUSTOM0 + print("MAP: CUSTOM0") + pass + elif y == 1: + # CUSTOM1 + print("MAP: CUSTOM1") + pass + elif y == 2: + # NMSUB + # print("MAP: NMSUB") + parse_r(op) + pass + elif y == 3: + # RESERVED + print("MAP: RESERVED 2 3") + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 3: + if y == 0: + # MISC-MEM + # print("MAP: MISC-MEM") + parse_misc_mem(op) + pass + elif y == 1: + # AMO + # print("MAP: AMO") + parse_r(op) + pass + elif y == 2: + # NMADD + # print("MAP: NMADD") + parse_r(op) + pass + elif y == 3: + # JAL + # print("MAP: JAL") + parse_j(op) + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 4: + if y == 0: + # OP-IMM + # print("MAP: OP-IMM") + parse_i(op) + elif y == 1: + # OP + # print("MAP: OP") + parse_r(op) + pass + elif y == 2: + # OP-FP + # print("MAP: OP-FP") + parse_r(op) + pass + elif y == 3: + # SYSTEM + # print("MAP: SYSTEM") + parse_i(op) + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 5: + if y == 0: + # AUIPC + # print("MAP: AUIPC") + parse_u(op) + pass + elif y == 1: + # LUI + # print("MAP: LUI") + parse_u(op) + pass + elif y == 2: + # RESERVED + print("MAP: RESERVED 5 2") + pass + elif y == 3: + # RESERVED + print("MAP: RESERVED 5 3") + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + elif x == 6: + if y == 0: + # OP-IMM-32 + # print("MAP: OP-IMM-32") + parse_i(op) + pass + elif y == 1: + # OP-32 + # print("MAP: OP-32") + parse_r(op) + pass + elif y == 2: + # CUSTOM2 + print("MAP: CUSTOM2") + pass + elif y == 3: + # CUSTOM3 + print("MAP: CUSTOM3") + pass + else: + print("BAD Y %x X %x" % (y,x)) + print(op) + exit(1) + else: + print("BAD X %x" % (x)) + print(op) + exit(1) + + + +def find_gaps(op): + """Account for all the bits in the pattern + dummy style just added as they got added""" + gap = { + 'op0001': (0,1), + 'op0204': (2,4), + 'op0506': (5,6), + 'op0707': (7,7), + 'op0711': (7,11), + 'r0711': (7,11), + 'fr0711': (7,11), + 'op0811': (8,11), + 'op1214': (12,14), + 'funct3': (12,14), + 'op1219': (12,19), + 'op1231': (12,31), + 'sop1231': (12,31), + 'r1519': (15,19), + 'fr1519': (15,19), + 'fd1519': (15,19), + 'op1527': (15,27), + 'op1531': (15,31), + 'op2020': (20,20), + 'succ': (20,23), + 'op2024': (20,24), + 'r2024': (20,24), + 'fr2024': (20,24), + 'op2031': (20,31), + 'sop2031': (20,31), + 'op2130': (21,30), + 'pred': (24,27), + 'op2525': (25,25), + 'op2526': (25,26), + 'op2530': (25,30), + 'op2531': (25,31), + 'sop2531': (25,31), + 'op2631': (26,31), + 'funct7': (25,31), + 'op2731': (27,31), + 'r2731': (27,31), + 'fr2731': (27,31), + 'fm': (28,31), + 'sop3131': (31,31), + 'cop0001': (0,1), + 'cop0202': (2,2), + 'cop0203': (2,3), + 'cop0204': (2,4), + 'cr0204s': (2,4), + 'cfr0204s': (2,4), + 'cop0205': (2,5), + 'cop0206': (2,6), + 'cr0206': (2,6), + 'cfr0206': (2,6), + 'cop0212': (2,12), + 'cop0304': (3,4), + 'cop0305': (3,5), + 'cop0406': (4,6), + 'cop0505': (5,5), + 'cop0506': (5,6), + 'cop0512': (5,12), + 'cop0606': (6,6), + 'cop0707': (7,7), + 'cop0708': (7,8), + 'cop0709': (7,9), + 'cr0709s': (7,9), + 'cd0709s': (7,9), + 'cfr0709s': (7,9), + 'cop0710': (7,10), + 'cop0711': (7,11), + 'cr0711': (7,11), + 'cd0711': (7,11), + 'cfr0711': (7,11), + 'cop0712': (7,12), + 'cop0808': (8,8), + 'cop0910': (9,10), + 'cop0912': (9,12), + 'cop1010': (10,10), + 'cop1011': (10,11), + 'cop1012': (10,12), + 'cop1111': (11,11), + 'cop1112': (11,12), + 'cop1212': (12,12), + 'scop1212': (12,12), + 'cop1315': (13,15), + 'immI': "sop2031", + 'immS': "op0711 & sop2531", + 'immSB': "op0707 & op0811 & op2530 & sop3131", + 'immU': "sop1231", + 'immUJ': "op1219 & op2020 & op2130 & sop3131", + 'shamt5': "op2024", + 'shamt6': "op2024 & op2525", + 'frm': "op1214=0", + 'frm': "op1214=1", + 'frm': "op1214=2", + 'frm': "op1214=3", + 'frm': "op1214=4", + 'frm': "op1214=7", + 'fmt': "op2526=0", + 'fmt': "op2526=1", + 'fmt': "op2526=2", + 'fmt': "op2526=3", + 'csr1': "op2031", + 'csr2': "op2031", + 'csr4': "op2031", + 'csr8': "op2031", + 'csr': "op2031", + 'cimmI': "cop1212 & cop0204 & cop0506", + 'cbimm': "scop1212 & cop1011 & cop0506 & cop0304 & cop0202", + 'cjimm': "scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202", + 'c6imm': "cop1212 & cop0206", + 'cbigimm': "scop1212 & cop0206", + 'caddi4spnimm': "cop1112 & cop0710 & cop0606 & cop0505", + 'caddi16spimm': "scop1212 & cop0606 & cop0505 & cop0304 & cop0202", + 'cldimm': "cop1012 & cop0506", + 'cldimm5376': "cop1012 & cop0506", + 'cldimm54876': "cop1112 & cop1010 & cop0506", + 'cldimm5326': "cop1012 & cop0606 & cop0505", + 'clwimm': "cop1012 & cop0506", + 'clwimm5376': "cop1012 & cop0506", + 'clwimm54876': "cop1112 & cop1010 & cop0506", + 'clwimm5326': "cop1012 & cop0606 & cop0505", + 'cldspimm': "cop1212 & cop0506 & cop0204", + 'cldspimm54386': "cop1212 & cop0506 & cop0204", + 'cldspimm5496': "cop1212 & cop0606 & cop0205", + 'cldspimm54276': "cop1212 & cop0406 & cop0203", + 'clwspimm': "cop1212 & cop0506 & cop0204", + 'clwspimm54386': "cop1212 & cop0506 & cop0204", + 'clwspimm5496': "cop1212 & cop0606 & cop0205", + 'clwspimm54276': "cop1212 & cop0406 & cop0203", + 'csdspimm': "cop0709 & cop1012", + 'csdspimm5386': "cop0709 & cop1012", + 'csdspimm5496': "cop0710 & cop1112", + 'csdspimm5276': "cop0708 & cop0912", + 'cswspimm': "cop0709 & cop1012", + 'cswspimm5386': "cop0709 & cop1012", + 'cswspimm5496': "cop0710 & cop1112", + 'cswspimm5276': "cop0708 & cop0912", + 'sp': None, + 'zero': None + } + pattern = 0x0 + for x in op.bitpattern: + x = x.split('=')[0] + if not x in gap.keys(): + print("GAP: %r" % x) + exit(1) + x = gap[x] + if isinstance(x, str): + y = x.split('&') + for _ in y: + w = gap[_.strip().split('=')[0]] + pattern |= (((1 << (w[1] - w[0] + 1)) - 1) << w[0]) + if isinstance(x, tuple): + pattern |= (((1 << (x[1] - x[0] + 1)) - 1) << x[0]) + # print("# %s 10987654321098765432109876543210" % (op.name)) + # print("# %s %s" % (op.name, '{:032b}'.format(pattern))) + z = '{:032b}'.format(pattern)[::-1] + z0 = '{:032b}'.format(op.match)[::-1] + z1 = '{:032b}'.format(op.mask)[::-1] + # print("# %s %s" % (op.name, '{:032b}'.format(op.match))) + # print("# %s %s" % (op.name, '{:032b}'.format(op.mask))) + x = 0 + y = 32 if op.match & 3 == 3 else 16 + while x < y: + start = z.find('0', x) + if start > 0 and start < y: + # print("# START %d %d %d" % (x, start, y)) + end = z.find('1', start) + if end < 0: + end = y + # print("# chunk %d - %d (%d) " % (start, end - 1, x)) + t0 = z1[start:end] + # print("# THING %s %s" % (t0, z1)) + if t0.find('0') > 0: + print("damnit %s" % (z1[start:end])) + exit(1) + t0 = int(z0[start:end][::-1], 2) + t1 = int(z1[start:end][::-1], 2) + # print("# %d %d" % (t0, t1)) + if 16 == y: + bp = "cop%02d%02d=0x%x" % (start, end - 1, t0 & t1) + else: + bp = "op%02d%02d=0x%x" % (start, end - 1, t0 & t1) + # print("# BP = %s " % bp) + op.bitpattern.append(bp) + x = end + 1 + + else: + # print("#END 1") + break + + +def parse(): + sorted_opcodes = sorted(opcodes, key=lambda x: x[0]) + for op in sorted_opcodes: + size = 0 + op = OpCode(op) + if op.xlen: + print("@if defined(RISCV%d)" % (op.xlen)) + if INSN_MACRO == op.pinfo: + print("#TODO MACRO") + print("# %s" % op) + if op.xlen: + print("@endif") + print("") + continue + if INSN_ALIAS & op.pinfo != 0: + print("#TODO ALIAS") + print("# %s" % op) + op.display, op.bitpattern = parse_operand(op) + op.bitpattern = list(set(op.bitpattern)) + if op.match & 3 == 3: + opcode_map(op) + else: + opcode_map_c(op) + find_gaps(op) + if INSN_ALIAS & op.pinfo != 0: + print("#:%s %s is %s\n#{\n#}" % (op.name, op.display, ' & '.join(op.bitpattern))) + else: + print(":%s %s is %s\n{\n}" % (op.name, op.display, ' & '.join(op.bitpattern))) + if op.xlen: + print("@endif") + print("") + return + + +def make_unique(): + sorted_opcodes = sorted(opcodes, key=lambda x: x[0]) + for opX in sorted_opcodes: + print("-------------------------") + opX = OpCode(opX) + print("X: %s" % (opX)) + for opY in sorted_opcodes: + opY = OpCode(opY) + if opY == opX: + continue + if opX.mask != opY.mask: + continue + if opX.match != opY.match: + continue + if opX.xlen != opY.xlen: + continue + print("Y: %s" % (opY)) + +if __name__ == "__main__": + parse() + # make_unique() + diff --git a/Ghidra/Processors/RISCV/src/main/java/ghidra/app/plugin/core/analysis/RISCVAddressAnalyzer.java b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/plugin/core/analysis/RISCVAddressAnalyzer.java new file mode 100644 index 0000000000..b789a638b2 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/plugin/core/analysis/RISCVAddressAnalyzer.java @@ -0,0 +1,146 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import ghidra.program.model.listing.ContextChangeException; +import ghidra.program.model.listing.Function; +import ghidra.program.model.listing.Instruction; +import ghidra.program.model.listing.Program; +import ghidra.program.model.listing.ProgramContext; + +import java.math.BigInteger; + +import ghidra.app.util.importer.MessageLog; +import ghidra.program.model.address.Address; +import ghidra.program.model.address.AddressSet; +import ghidra.program.model.address.AddressSetView; +import ghidra.program.model.lang.Processor; +import ghidra.program.model.lang.Register; +import ghidra.program.model.lang.RegisterValue; +import ghidra.program.model.symbol.Symbol; +import ghidra.program.model.symbol.SymbolUtilities; +import ghidra.program.util.SymbolicPropogator; +import ghidra.program.util.VarnodeContext; +import ghidra.util.task.TaskMonitor; +import ghidra.util.Msg; +import ghidra.util.exception.AssertException; +import ghidra.util.exception.CancelledException; + +public class RISCVAddressAnalyzer extends ConstantPropagationAnalyzer { + + public static final String RISCV___GLOBAL_POINTER = "__global_pointer$"; + + private Address gp_assumption_value; + + private static final String REGISTER_GP = "gp"; + private Register gp; + + private static final String PROCESSOR_NAME = "RISCV"; + + public RISCVAddressAnalyzer() { + super(PROCESSOR_NAME); + } + + @Override + public boolean canAnalyze(Program program) { + boolean canAnalyze = program.getLanguage().getProcessor().equals( + Processor.findOrPossiblyCreateProcessor(PROCESSOR_NAME)); + + if (!canAnalyze) { + return false; + } + + gp = program.getRegister(REGISTER_GP); + + return true; + } + + @Override + public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log) + throws CancelledException { + + gp_assumption_value = null; + + // check for the __global_pointer$ symbol to see what the global gp + // value should be + checkForGlobalGP(program, set, monitor); + + return super.added(program, set, monitor, log); + } + + @Override + public AddressSetView flowConstants(final Program program, Address flowStart, + AddressSetView flowSet, final SymbolicPropogator symEval, final TaskMonitor monitor) + throws CancelledException { + + // get the function body + final Function func = program.getFunctionManager().getFunctionContaining(flowStart); + + final AddressSet coveredSet = new AddressSet(); + + if (func != null && gp_assumption_value != null) { + ProgramContext programContext = program.getProgramContext(); + RegisterValue gpVal = programContext.getRegisterValue(gp, flowStart); + if (gpVal == null || !gpVal.hasValue()) { + gpVal = new RegisterValue(gp, BigInteger.valueOf(gp_assumption_value.getOffset())); + try { + program.getProgramContext().setRegisterValue(func.getEntryPoint(), + func.getEntryPoint(), gpVal); + } + catch (ContextChangeException e) { + // only happens for context register + throw new AssertException("unexpected", e); + } + } + } + + // follow all flows building up context + ConstantPropagationContextEvaluator eval = + new ConstantPropagationContextEvaluator(trustWriteMemOption) { + private boolean mustStopNow = false; + + @Override + public boolean evaluateContextBefore(VarnodeContext context, Instruction instr) { + return mustStopNow; + } + + @Override + public boolean evaluateContext(VarnodeContext context, Instruction instr) { + return mustStopNow; + } + }; + AddressSet resultSet = symEval.flowConstants(flowStart, null, eval, true, monitor); + resultSet.add(coveredSet); + + return resultSet; + } + + /** + * Check for a global GP register symbol or discovered symbol + * @param program + * @param set + * @param monitor + */ + private void checkForGlobalGP(Program program, AddressSetView set, TaskMonitor monitor) { + Symbol symbol = SymbolUtilities.getLabelOrFunctionSymbol(program, + RISCV___GLOBAL_POINTER, + err -> Msg.error(this, err)); + if (symbol != null) { + gp_assumption_value = symbol.getAddress(); + return; + } + } +} diff --git a/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/extend/RISCV_ElfExtension.java b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/extend/RISCV_ElfExtension.java new file mode 100644 index 0000000000..766a3dbe16 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/extend/RISCV_ElfExtension.java @@ -0,0 +1,49 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf.extend; + +import ghidra.app.util.bin.format.elf.*; +import ghidra.program.model.address.Address; +import ghidra.program.model.lang.*; +import ghidra.program.model.listing.Program; +import ghidra.program.model.listing.ContextChangeException; + +public class RISCV_ElfExtension extends ElfExtension { + + //TODO not sure about these + public static final String RISCV_PROC="RISCV"; + public static final String RISCV_SUFFIX="_RISCV"; + + @Override + public boolean canHandle(ElfHeader elf) { + return elf.e_machine() == ElfConstants.EM_RISCV; + } + + @Override + public boolean canHandle(ElfLoadHelper elfLoadHelper) { + if (!canHandle(elfLoadHelper.getElfHeader())) + return false; + + Language language = elfLoadHelper.getProgram().getLanguage(); + int size =language.getLanguageDescription().getSize(); + return ((32 == size || 64 == size) && language.getProcessor().toString().equals(RISCV_PROC)); + } + + @Override + public String getDataTypeSuffix() { + return RISCV_SUFFIX; + } +} diff --git a/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationConstants.java b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationConstants.java new file mode 100644 index 0000000000..2d39f5d500 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationConstants.java @@ -0,0 +1,84 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package ghidra.app.util.bin.format.elf.relocation; + +public class RISCV_ElfRelocationConstants { + + /* + * A Addend field in the relocation entry associated with the symbol + * B Base address of a shared object loaded into memory + * G Offset of the symbol into the GOT (Global Offset Table) + * S Value of the symbol in the symbol table + * GP Global Pointer register (x3) + */ + public static final int R_RISCV_NONE = 0; // None + public static final int R_RISCV_32 = 1; // Runtime relocation word32 = S + A + public static final int R_RISCV_64 = 2; // Runtime relocation word64 = S + A + public static final int R_RISCV_RELATIVE = 3; // Runtime relocation word32,64 = B + A + public static final int R_RISCV_COPY = 4; // Runtime relocation must be in executable. not allowed in shared library + public static final int R_RISCV_JUMP_SLOT = 5; // Runtime relocation word32,64 = S ;handled by PLT unless LD_BIND_NOW + public static final int R_RISCV_TLS_DTPMOD32 = 6; // TLS relocation word32 = S->TLSINDEX + public static final int R_RISCV_TLS_DTPMOD64 = 7; // TLS relocation word64 = S->TLSINDEX + public static final int R_RISCV_TLS_DTPREL32 = 8; // TLS relocation word32 = TLS + S + A - TLS_TP_OFFSET + public static final int R_RISCV_TLS_DTPREL64 = 9; // TLS relocation word64 = TLS + S + A - TLS_TP_OFFSET + public static final int R_RISCV_TLS_TPREL32 = 10; // TLS relocation word32 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET + public static final int R_RISCV_TLS_TPREL64 = 11; // TLS relocation word64 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET + public static final int R_RISCV_BRANCH = 16; // PC-relative branch (SB-Type) + public static final int R_RISCV_JAL = 17; // PC-relative jump (UJ-Type) + public static final int R_RISCV_CALL = 18; // PC-relative call MACRO call,tail (auipc+jalr pair) + public static final int R_RISCV_CALL_PLT = 19; // PC-relative call (PLT) MACRO call,tail (auipc+jalr pair) PIC + public static final int R_RISCV_GOT_HI20 = 20; // PC-relative GOT reference MACRO la + public static final int R_RISCV_TLS_GOT_HI20 = 21; // PC-relative TLS IE GOT offset MACRO la.tls.ie + public static final int R_RISCV_TLS_GD_HI20 = 22; // PC-relative TLS GD reference MACRO la.tls.gd + public static final int R_RISCV_PCREL_HI20 = 23; // PC-relative reference %pcrel_hi(symbol) (U-Type) + public static final int R_RISCV_PCREL_LO12_I = 24; // PC-relative reference %pcrel_lo(symbol) (I-Type) + public static final int R_RISCV_PCREL_LO12_S = 25; // PC-relative reference %pcrel_lo(symbol) (S-Type) + public static final int R_RISCV_HI20 = 26; // Absolute address %hi(symbol) (U-Type) + public static final int R_RISCV_LO12_I = 27; // Absolute address %lo(symbol) (I-Type) + public static final int R_RISCV_LO12_S = 28; // Absolute address %lo(symbol) (S-Type) + public static final int R_RISCV_TPREL_HI20 = 29; // TLS LE thread offset %tprel_hi(symbol) (U-Type) + public static final int R_RISCV_TPREL_LO12_I = 30; // TLS LE thread offset %tprel_lo(symbol) (I-Type) + public static final int R_RISCV_TPREL_LO12_S = 31; // TLS LE thread offset %tprel_lo(symbol) (S-Type) + public static final int R_RISCV_TPREL_ADD = 32; // TLS LE thread usage %tprel_add(symbol) + public static final int R_RISCV_ADD8 = 33; // 8-bit label addition word8 = old + S + A + public static final int R_RISCV_ADD16 = 34; // 16-bit label addition word16 = old + S + A + public static final int R_RISCV_ADD32 = 35; // 32-bit label addition word32 = old + S + A + public static final int R_RISCV_ADD64 = 36; // 64-bit label addition word64 = old + S + A + public static final int R_RISCV_SUB8 = 37; // 8-bit label subtraction word8 = old - S - A + public static final int R_RISCV_SUB16 = 38; // 16-bit label subtraction word16 = old - S - A + public static final int R_RISCV_SUB32 = 39; // 32-bit label subtraction word32 = old - S - A + public static final int R_RISCV_SUB64 = 40; // 64-bit label subtraction word64 = old - S - A + public static final int R_RISCV_GNU_VTINHERIT = 41; // GNU C++ vtable hierarchy + public static final int R_RISCV_GNU_VTENTRY = 42; // GNU C++ vtable member usage + public static final int R_RISCV_ALIGN = 43; // Alignment statement + public static final int R_RISCV_RVC_BRANCH = 44; // PC-relative branch offset (CB-Type) + public static final int R_RISCV_RVC_JUMP = 45; // PC-relative jump offset (CJ-Type) + public static final int R_RISCV_RVC_LUI = 46; // Absolute address (CI-Type) + public static final int R_RISCV_GPREL_I = 47; // GP-relative reference (I-Type) + public static final int R_RISCV_GPREL_S = 48; // GP-relative reference (S-Type) + public static final int R_RISCV_TPREL_I = 49; // TP-relative TLS LE load (I-Type) + public static final int R_RISCV_TPREL_S = 50; // TP-relative TLS LE store (S-Type) + public static final int R_RISCV_RELAX = 51; // Instruction pair can be relaxed + public static final int R_RISCV_SUB6 = 52; // Local label subtraction + public static final int R_RISCV_SET6 = 53; // Local label subtraction + public static final int R_RISCV_SET8 = 54; // Local label subtraction + public static final int R_RISCV_SET16 = 55; // Local label subtraction + public static final int R_RISCV_SET32 = 56; // Local label subtraction + public static final int R_RISCV_32_PCREL = 57; // 32-bit PC relative + // 58-191 Reserved Reserved for future standard use + // 192-255 Reserved Reserved for nonstandard ABI extensions +} diff --git a/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationHandler.java b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationHandler.java new file mode 100644 index 0000000000..940f03b7e8 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/main/java/ghidra/app/util/bin/format/elf/relocation/RISCV_ElfRelocationHandler.java @@ -0,0 +1,459 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package ghidra.app.util.bin.format.elf.relocation; + +import ghidra.app.util.bin.format.elf.*; +import ghidra.program.model.address.Address; +import ghidra.program.model.listing.Program; +import ghidra.program.model.mem.Memory; +import ghidra.program.model.mem.MemoryAccessException; +import ghidra.util.exception.NotFoundException; + +public class RISCV_ElfRelocationHandler extends ElfRelocationHandler { + + @Override + public boolean canRelocate(ElfHeader elf) { + return elf.e_machine() == ElfConstants.EM_RISCV; + } + + @Override + public void relocate(ElfRelocationContext elfRelocationContext, ElfRelocation relocation, + Address relocationAddress) throws MemoryAccessException, NotFoundException { + ElfHeader elf = elfRelocationContext.getElfHeader(); + if (!canRelocate(elf)) { + return; + } + + Program program = elfRelocationContext.getProgram(); + Memory memory = program.getMemory(); + boolean is32 = elf.is32Bit(); + int type = relocation.getType(); + if (RISCV_ElfRelocationConstants.R_RISCV_NONE == type) { + return; + } + + long addend = relocation.hasAddend() ? relocation.getAddend() : is32 ? memory.getInt(relocationAddress) : memory.getLong(relocationAddress); + long offset = relocationAddress.getOffset(); + long base = elfRelocationContext.getImageBaseWordAdjustmentOffset(); + ElfSymbol sym = null; + long symbolValue = 0; + String symbolName = null; + + int symbolIndex = relocation.getSymbolIndex(); + if (symbolIndex != 0) { + sym = elfRelocationContext.getSymbol(symbolIndex); + } + + if (null != sym) { + symbolValue = elfRelocationContext.getSymbolValue(sym); + symbolName = sym.getNameAsString(); + } + + //TODO remove debug + switch(type) { + case 2: + case 3: + case 5: + break; + default: + System.out.println("DEBUG RISCV: " + + type + " " + relocationAddress + " " + + String.format("%x", symbolValue) + " " + + String.format("%x", addend) + " " + + String.format("%x", offset) + " " + + String.format("%x", base));// + " " + + //String.format("%x", memory.getInt(relocationAddress))); + break; + } + + long value64 = 0; + int value32 = 0; + short value16 = 0; + byte value8 = 0; + + switch (type) { + case RISCV_ElfRelocationConstants.R_RISCV_32: + // Runtime relocation word32 = S + A + value32 = (int)(symbolValue + addend); + memory.setInt(relocationAddress, value32); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_64: + // Runtime relocation word64 = S + A + value64 = symbolValue + addend; + memory.setLong(relocationAddress, value64); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_RELATIVE: + // Runtime relocation word32,64 = B + A + if (is32) { + value32 = (int)(base + addend); + memory.setInt(relocationAddress, value32); + } + else { + value64 = base + addend; + memory.setLong(relocationAddress, value64); + } + break; + + case RISCV_ElfRelocationConstants.R_RISCV_COPY: + // Runtime relocation must be in executable. not allowed in shared library + markAsWarning(program, relocationAddress, "R_RISCV_COPY", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_JUMP_SLOT: + // Runtime relocation word32,64 = S ;handled by PLT unless LD_BIND_NOW + if (is32) { + value32 = (int)(symbolValue); + memory.setInt(relocationAddress, value32); + } + else { + value64 = symbolValue; + memory.setLong(relocationAddress, value64); + } + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPMOD32: + // TLS relocation word32 = S->TLSINDEX + markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPMOD32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPMOD64: + // TLS relocation word64 = S->TLSINDEX + markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPMOD32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPREL32: + // TLS relocation word32 = TLS + S + A - TLS_TP_OFFSET + markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPREL32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_DTPREL64: + // TLS relocation word64 = TLS + S + A - TLS_TP_OFFSET + markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTPREL64", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_TPREL32: + // TLS relocation word32 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET + markAsWarning(program, relocationAddress, "R_RISCV_TLS_DTREL32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_TPREL64: + // TLS relocation word64 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET + markAsWarning(program, relocationAddress, "R_RISCV_TLS_TPREL64", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_BRANCH: + // PC-relative branch (SB-Type) + markAsWarning(program, relocationAddress, "R_RISCV_BRANCH", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_JAL: + // PC-relative jump (UJ-Type) + markAsWarning(program, relocationAddress, "R_RISCV_JAL", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_CALL: + // PC-relative call MACRO call,tail (auipc+jalr pair) + markAsWarning(program, relocationAddress, "R_RISCV_CALL", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_CALL_PLT: + // PC-relative call (PLT) MACRO call,tail (auipc+jalr pair) PIC + markAsWarning(program, relocationAddress, "R_RISCV_CALL_PLT", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_GOT_HI20: + // PC-relative GOT reference MACRO la + markAsWarning(program, relocationAddress, "R_RISCV_GOT_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_GOT_HI20: + // PC-relative TLS IE GOT offset MACRO la.tls.ie + markAsWarning(program, relocationAddress, "R_RISCV_TLS_GOT_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TLS_GD_HI20: + // PC-relative TLS GD reference MACRO la.tls.gd + markAsWarning(program, relocationAddress, "R_RISCV_TLS_GD_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_PCREL_HI20: + // PC-relative reference %pcrel_hi(symbol) (U-Type) + markAsWarning(program, relocationAddress, "R_RISCV_PCREL_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_PCREL_LO12_I: + // PC-relative reference %pcrel_lo(symbol) (I-Type) + markAsWarning(program, relocationAddress, "R_RISCV_PCREL_LO12_I", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_PCREL_LO12_S: + // PC-relative reference %pcrel_lo(symbol) (S-Type) + markAsWarning(program, relocationAddress, "R_RISCV_PCREL_LO12_S", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_HI20: + // Absolute address %hi(symbol) (U-Type) + markAsWarning(program, relocationAddress, "R_RISCV_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_LO12_I: + // Absolute address %lo(symbol) (I-Type) + markAsWarning(program, relocationAddress, "R_RISCV_LO12_I", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_LO12_S: + // Absolute address %lo(symbol) (S-Type) + markAsWarning(program, relocationAddress, "R_RISCV_LO12_S", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_HI20: + // TLS LE thread offset %tprel_hi(symbol) (U-Type) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_HI20", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_LO12_I: + // TLS LE thread offset %tprel_lo(symbol) (I-Type) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_LO12_I", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_LO12_S: + // TLS LE thread offset %tprel_lo(symbol) (S-Type) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_LO12_S", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_ADD: + // TLS LE thread usage %tprel_add(symbol) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_ADD", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_ADD8: + // 8-bit label addition word8 = old + S + A + markAsWarning(program, relocationAddress, "R_RISCV_ADD8", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value8 = memory.getByte(relocationAddress); + value8 += (byte)symbolValue; + value8 += (byte)addend; + memory.setByte(relocationAddress, value8); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_ADD16: + // 16-bit label addition word16 = old + S + A + markAsWarning(program, relocationAddress, "R_RISCV_ADD16", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value16 = memory.getShort(relocationAddress); + value16 += (short)symbolValue; + value16 += (short)addend; + memory.setShort(relocationAddress, value16); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_ADD32: + // 32-bit label addition word32 = old + S + A + markAsWarning(program, relocationAddress, "R_RISCV_ADD32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value32 = memory.getInt(relocationAddress); + value32 += (int)symbolValue; + value32 += (int)addend; + memory.setInt(relocationAddress, value32); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_ADD64: + // 64-bit label addition word64 = old + S + A + markAsWarning(program, relocationAddress, "R_RISCV_ADD64", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value64 = memory.getLong(relocationAddress); + value64 += symbolValue; + value64 += addend; + memory.setLong(relocationAddress, value64); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SUB8: + // 8-bit label subtraction word8 = old - S - A + markAsWarning(program, relocationAddress, "R_RISCV_SUB8", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value8 = memory.getByte(relocationAddress); + value8 -= (byte)symbolValue; + value8 -= (byte)addend; + memory.setByte(relocationAddress, value8); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SUB16: + // 16-bit label subtraction word16 = old - S - A + markAsWarning(program, relocationAddress, "R_RISCV_SUB16", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value16 = memory.getShort(relocationAddress); + value16 -= (short)symbolValue; + value16 -= (short)addend; + memory.setShort(relocationAddress, value16); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SUB32: + // 32-bit label subtraction word32 = old - S - A + markAsWarning(program, relocationAddress, "R_RISCV_SUB32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value32 = memory.getInt(relocationAddress); + value32 -= (int)symbolValue; + value32 -= (int)addend; + memory.setInt(relocationAddress, value32); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SUB64: + // 64-bit label subtraction word64 = old - S - A + markAsWarning(program, relocationAddress, "R_RISCV_SUB64", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + value64 = memory.getLong(relocationAddress); + value64 -= symbolValue; + value64 -= addend; + memory.setLong(relocationAddress, value64); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_GNU_VTINHERIT: + // GNU C++ vtable hierarchy + markAsWarning(program, relocationAddress, "R_RISCV_GNU_VTINHERIT", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_GNU_VTENTRY: + // GNU C++ vtable member usage + markAsWarning(program, relocationAddress, "R_RISCV_GNU_VTENTRY", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_ALIGN: + // Alignment statement + markAsWarning(program, relocationAddress, "R_RISCV_ALIGN", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_RVC_BRANCH: + // PC-relative branch offset (CB-Type) + markAsWarning(program, relocationAddress, "R_RISCV_RVC_BRANCH", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_RVC_JUMP: + // PC-relative jump offset (CJ-Type) + markAsWarning(program, relocationAddress, "R_RISCV_RVC_BRANCH", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_RVC_LUI: + // Absolute address (CI-Type) + markAsWarning(program, relocationAddress, "R_RISCV_RVC_LUI", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_GPREL_I: + // GP-relative reference (I-Type) + markAsWarning(program, relocationAddress, "R_RISCV_GPREL_I", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_GPREL_S: + // GP-relative reference (S-Type) + markAsWarning(program, relocationAddress, "R_RISCV_GPREL_S", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_I: + // TP-relative TLS LE load (I-Type) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_I", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_TPREL_S: + // TP-relative TLS LE store (S-Type) + markAsWarning(program, relocationAddress, "R_RISCV_TPREL_S", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_RELAX: + // Instruction pair can be relaxed + markAsWarning(program, relocationAddress, "R_RISCV_RELAX", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SUB6: + // Local label subtraction + markAsWarning(program, relocationAddress, "R_RISCV_SUB6", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SET6: + // Local label subtraction + markAsWarning(program, relocationAddress, "R_RISCV_SET6", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SET8: + // Local label subtraction + markAsWarning(program, relocationAddress, "R_RISCV_SET8", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SET16: + // Local label subtraction + markAsWarning(program, relocationAddress, "R_RISCV_SET16", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_SET32: + // Local label subtraction + markAsWarning(program, relocationAddress, "R_RISCV_SET32", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + case RISCV_ElfRelocationConstants.R_RISCV_32_PCREL: + // 32-bit PC relative + markAsWarning(program, relocationAddress, "R_RISCV_32_PCREL", symbolName, symbolIndex, + "TODO, needs support ", elfRelocationContext.getLog()); + break; + + default: + // 58-191 Reserved Reserved for future standard use + // 192-255 Reserved Reserved for nonstandard ABI extensions + markAsUnhandled(program, relocationAddress, type, symbolIndex, symbolName, elfRelocationContext.getLog()); + break; + + } + } +} diff --git a/Ghidra/Processors/RISCV/src/main/java/ghidra/program/emulation/RISCVEmulateInstructionStateModifier.java b/Ghidra/Processors/RISCV/src/main/java/ghidra/program/emulation/RISCVEmulateInstructionStateModifier.java new file mode 100644 index 0000000000..d3d54529c5 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/main/java/ghidra/program/emulation/RISCVEmulateInstructionStateModifier.java @@ -0,0 +1,61 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +import ghidra.pcode.emulate.EmulateInstructionStateModifier; +import ghidra.pcode.error.LowlevelError; +import ghidra.program.model.address.Address; +import ghidra.program.model.lang.RegisterValue; +import ghidra.program.model.pcode.PcodeOp; +import ghidra.pcode.emulate.Emulate; + +public class RISCVEmulateInstructionStateModifier extends EmulateInstructionStateModifier { + + public RISCVEmulateInstructionStateModifier(Emulate emu) { + super(emu); + } + + /** + * Emulation callback immediately before the first instruction is executed. + * This callback permits any language specific initializations to be performed. + * @param emulate + * @param current_address intial execute address + * @param contextRegisterValue initial context value or null if not applicable or unknown + * @throws LowlevelError + */ + @Override + public void initialExecuteCallback(Emulate emulate, Address current_address, RegisterValue contextRegisterValue) throws LowlevelError { + // no default implementation + } + + /** + * Emulation callback immediately following execution of the lastExecuteAddress. + * One use of this callback is to modify the flowing/future context state. + * @param emulate + * @param lastExecuteAddress + * @param lastExecutePcode + * @param lastPcodeIndex pcode index of last op or -1 if no pcode or fall-through occurred. + * @param currentAddress + * @throws LowlevelError + */ + @Override + public void postExecuteCallback(Emulate emulate, Address lastExecuteAddress, + PcodeOp[] lastExecutePcode, int lastPcodeIndex, Address currentAddress) + throws LowlevelError { + // no default implementation + } + +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O0_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O0_EmulatorTest.java new file mode 100644 index 0000000000..6847724e34 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O0_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV32GC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:32:RV32GC"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV32GC_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV32GC_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32GC_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O3_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O3_EmulatorTest.java new file mode 100644 index 0000000000..80d93e7f53 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32GC_O3_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV32GC_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:32:RV32GC"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV32GC_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV32GC_GCC_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32GC_O3_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32IMC_O0_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32IMC_O0_EmulatorTest.java new file mode 100644 index 0000000000..c50b59fbbd --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV32IMC_O0_EmulatorTest.java @@ -0,0 +1,39 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV32IMC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + private static final String LANGUAGE_ID = "RISCV:LE:32:RV32IMC"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV32IMC_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV32IMC_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV32IMC_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O0_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O0_EmulatorTest.java new file mode 100644 index 0000000000..3b4d636fb5 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O0_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV64GC_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:64:RV64GC"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV64GC_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV64GC_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64GC_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O3_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O3_EmulatorTest.java new file mode 100644 index 0000000000..f80c17faf3 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64GC_O3_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV64GC_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:64:RV64GC"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV64GC_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV64GC_GCC_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64GC_O3_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O0_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O0_EmulatorTest.java new file mode 100644 index 0000000000..e41bfb748a --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O0_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV64G_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:64:RV64G"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV64G_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV64G_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64G_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O3_EmulatorTest.java b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O3_EmulatorTest.java new file mode 100644 index 0000000000..cfaf3a78c5 --- /dev/null +++ b/Ghidra/Processors/RISCV/src/test.processors/java/ghidra/test/processors/RV64G_O3_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class RV64G_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "RISCV:LE:64:RV64G"; + private static final String COMPILER_SPEC_ID = "gcc"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public RV64G_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "RV64G_GCC_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(RV64G_O3_EmulatorTest.class); + } +}