From 6481044958dee1d029cd4f301932160902b08543 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Fri, 19 Jan 2024 19:51:23 +0000 Subject: [PATCH] GP-4249: Renamed pcodeops for x87 fbstp and fbld instructions --- Ghidra/Processors/x86/data/languages/ia.sinc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 027144c10b..dd7eaf7d43 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -4136,10 +4136,10 @@ define pcodeop f2xm1; :FIADD spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=0 ... & spec_m32 { ST0 = ST0 f+ int2float(spec_m32); } :FIADD spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=0 ... & spec_m16 { ST0 = ST0 f+ int2float(spec_m16); } -define pcodeop convert_bcd; -:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { fdec(); ST0 = convert_bcd(spec_m80); } - -:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = convert_bcd(ST0); fpop(); } +define pcodeop from_bcd; +:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { fdec(); ST0 = from_bcd(spec_m80); } +define pcodeop to_bcd; +:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = to_bcd(ST0); fpop(); } :FCHS is vexMode=0 & byte=0xD9; byte=0xE0 { ST0 = f- ST0; }